Prosecution Insights
Last updated: October 02, 2026

Examiner: GARBOWSKI, LEIGH M

Tech Center 2800 • Art Units: 1737 2825 2851

This examiner grants 88% of resolved cases

Analysis

Leigh M. Garbowski is an examiner in Tech Center 2800 and Art Unit 1737. Garbowski has handled 756 resolved cases, with an allowance rate of 88.0 percent. This 88.0 percent allowance rate indicates a very high probability of success for applications assigned to this docket. The 756 resolved cases provide a strong statistical basis for these performance metrics.

The data shows an interview lift of 10.4 percent. This 10.4 percent lift suggests that conducting an interview with the examiner is associated with a higher likelihood of allowance compared to cases without an interview. Even with an 88.0 percent allowance rate, the 10.4 percent lift indicates that direct communication remains a useful tool for resolving issues. Practitioners in Art Unit 1737 should consider the value of an interview in the context of this examiner's overall efficiency.

The median time to allowance is 807 days. This 807 day period is the typical duration from filing to patent issuance. This 807 day median suggests a relatively efficient prosecution cycle. Applicants can use this metric to forecast their pendency and plan their intellectual property strategy accordingly.

Written from this page's own data; every figure is computed from USPTO records and verified before publication.

Performance Statistics

88.0%
Allow Rate
+20.0% vs TC avg
765
Total Applications
+10.4%
Interview Lift
807
Avg Prosecution Days
Based on 756 resolved cases, 2023–2026

Rejection Statute Breakdown

18.9%
§101 Eligibility
31.6%
§102 Novelty
17.7%
§103 Obviousness
22.6%
§112 Clarity

Currently Pending Office Actions

App #TitleStatusAssignee
18564797 GENERATING LEARNED REPRESENTATIONS OF DIGITAL CIRCUIT DESIGNS Non-Final OA Google LLC
18120857 Systems And Methods For Generating Redacted Circuit Designs For Integrated Circuits Non-Final OA Intel Corporation
18350512 DESIGN-FOR-TEST CIRCUITS AND METHODS OF OPERATING THE SAME Non-Final OA Taiwan Semiconductor Manufacturing Company, Ltd.
18526337 METHOD FOR OPTIMIZING FLOOR PLAN FOR AN INTEGRATED CIRCUIT Non-Final OA TSMC NANJING COMPANY LIMITED
18170335 PHYSICAL LAYOUT SYNTHESIS FOR STANDARD CELLS USING SLICE LAYOUTS Non-Final OA Applied Materials, Inc.
18381052 EFFICIENT METHOD FOR THE LATCH TIMING ANALYSIS OF ELECTRONIC DESIGNS Non-Final OA XILINX, INC.
18387905 METHOD AND APPARATUS FOR PARTICLE BEAM-INDUCED PROCESSING OF A DEFECT OF A MICROLITHOGRAPHIC PHOTOMASK Non-Final OA Carl Zeiss SMT GmbH
18355754 CHIP PLACEMENT METHOD AND APPARATUS, AND STORAGE MEDIUM Non-Final OA The University of Hong Kong

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