DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office action is in response to the RCE filed 7/13/2026 in which claims 1, 2, 4, and 5 were amended, claims 3, 11-13, and 15-20 were cancelled, and claims 22-31 were added.
Claims 1-3, 5-10, 12, and 26-27 are pending with claims 1, 2, 4, 7, and 21-31 are presented for examination and claims 5, 6, 8, and 9 remain withdrawn.
Election/Restrictions
Examiner notes that claims 27 and 28 are drawn to Fig. 11, which was non-elected without traverse in the reply filed on 9/11/2025. Therefore, claims 27 and 28 are withdrawn from consideration.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4, 21-23, 25, 30, and 31 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nozu (US 2014/0077278 and Nozu hereinafter).
As to claims 1, 4, and 21: Nozu discloses [claim 1] a semiconductor device (Fig. 15), comprising: a semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13; [0026] and [0098]); a first electrode (51; [0028]) provided on a back surface (bottom surface of 10) of the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13); a second electrode (50; [0028]) provided on a front surface (top surface of 13) of the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) at a side opposite to the back surface (bottom surface of 10); a third electrode (40; [0028]) provided between the first electrode (51) and the second electrode (50), the third electrode (40) being provided in the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) with a first insulating film (comprising 41 between 40 and 11, 41 between 20 and 13, 41 between 20 and 12, and 41 between 30 and 13; [0030]) interposed, the third electrode (40) being electrically insulated from the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) by the first insulating film (portion comprising 41 between 40 and 11); a control electrode (20; [0027]) provided between the second electrode (50) and the third electrode (40), the control electrode (20) extending into the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) from the front side (top surface of 13) of the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) and facing the third electrode (40) with a second insulating film (portion of 41 between 20 and 40 and portion of 41 between 30 and 40 except the portion of 41 immediately touching 30 that is between 30 and 40; [0030]) interposed, the first insulating film (portion comprising 41 between 20 and 13) extending between the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) and the control electrode (20) and electrically insulating the control electrode (20) from the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13); and a fourth electrode (30; [0027]) provided between the second electrode (50) and the third electrode (40), the fourth electrode (30) extending into the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) from the front side (top surface of 13) of the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) and being positioned between the semiconductor part (portions of 12 and 13 on the right side of the gate trench and the semiconductor part comprising p+ layer between 10 and 11, 10, 11, 12, and 13) and the control electrode (20), the first insulating film (portion of 41 between 30 and 13) extending between the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) and the fourth electrode (30), the second insulating film (portion of 41 between 30 and 40) extending between the third electrode (40) and the fourth electrode (30), the fourth electrode (30) facing the control electrode (20) with a third insulating film (portion of 41 immediately touching 30 that is between 30 and 40) interposed therebetween, the fourth electrode (30) being electrically connected (through 50; [0096]) to the third electrode (40), wherein the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) includes first to fourth semiconductor layers (comprising p+ layer between 10 and 11, 10, 11, 12, and 13), the first semiconductor layer (11) being of a first conductivity type (n-type; [0026]) and extending between the first electrode (51) and the second electrode (50), the third electrode (40) facing the first semiconductor layer (11) via the first insulating film (comprising 41 between 40 and 11), the second semiconductor layer (12) being of a second conductivity type (p-type; [0026]) and provided between the first semiconductor layer (11) and the second electrode (50), the second semiconductor layer (12) facing the control electrode (20) with the first insulating film (comprising 41 between 20 and 12) interposed, the third semiconductor layer (13) being of the first conductivity type (n-type; [0026]) and partially provided on the second semiconductor layer (12), the third semiconductor layer (13) contacting the first insulating film (portion of 41 between 20 and 13 and 41 between 20 and 12) between the second semiconductor layer (12) and the second electrode (50), the fourth semiconductor layer (p+ layer between 10 and 11; [0098]) being of the second conductivity type (p-type; [0098]) and provided between the first semiconductor layer (11) and the first electrode (51), wherein the control electrode (20) and the fourth electrode (30) are electrically insulated from each other (20 is a gate electrode and is connected to the gate terminal and the fourth electrode is a field plate and is connected to the source terminal and are not electrically connected to one another; [0028]); and wherein the fourth electrode (30) faces (interpreted to mean -to have the front oriented toward-, as 30 has the outer vertical side, the front side, oriented toward the third semiconductor layer 13 along the horizontal direction) the third semiconductor layer (13) with the first insulating film (portion of 41 between 30 and 13) interposed therebetween; [claim 4] wherein the third semiconductor layer (13) faces the control electrode (20) with the first insulating film (portion of 41 between 20 and 13) interposed; [claim 21] further comprising: a second third-electrode (40 in second from the left trench) provided between the first electrode (51) and the second electrode (50), the second third-electrode (40) being provided in the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) with a second first-insulating film (comprising 41 between 40 and 11, 41 between 20 and 13, 41 between 20 and 12, and 41 between 30 and 13 in second from the left trench) interposed and being electrically insulated from the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) by the second first-insulating film (portion of 41 between 40 and 11); a second control electrode (20 in second from the left trench) provided between the second electrode (50) and the second third-electrode (40 in second from the left trench), the second control electrode (20 in second from the left trench) extending into the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) from the front side (top surface of 13) of the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) and facing the second third-electrode (40 in second from the left trench) with a second second-insulating film (portion of 41 between 20 and 40 and portion of 41 between 30 and 40 except the portion of 41 immediately touching 30 that is between 30 and 40 in second from the left trench) interposed, the second first-insulating film (portion of 41 between 20 and 12 and the portion of 41 between 20 and 13) extending between the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) and the second control electrode (20 in second from the left trench) and electrically insulating the second control electrode (second from the left trench) from the semiconductor part (portions 12 and 13); and a second fourth-electrode (30 in second from the left trench) provided between the second electrode (50) and the second third-electrode (40 in second from the left trench), the second fourth-electrode (30 in second from the left trench) extending into the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) from the front side (top surface of 13) of the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) and being positioned between the semiconductor part (portion of 12 and 13 on the right of the trench) and the second control electrode (20 in second from the left trench), the second first-insulating film (portion of 41 between 30 and 12) extending between the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) and the second fourth-electrode (30 in second from the left trench), the second second-insulating film (portion of 41 between 20 and 40 and portion of 41 between 30 and 40 except the portion of 41 immediately touching 30 that is between 30 and 40 in second from the left trench) extending between the second third-electrode (20 in second from the left trench) and the second fourth-electrode (30 in second from the left trench), the second fourth-electrode (30 in second from the left trench) facing the second control electrode (20 in second from the left trench) with a second third-insulating film (portion of 41 immediately touching 30 that is between 30 and 40 in second from the left trench) interposed and being electrically connected (through 50) to the second third-electrode (40 in second from the left trench), the second control electrode (20 in second from the left trench) facing the fourth electrode (30 in first trench from the left) via the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13).
As to claims 22, 23, 25, 30, and 31: Nozu discloses [claim 22] a semiconductor device (Fig. 15), comprising: a semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13; [0026] and [0098]); a first electrode (51; [0028]) provided on a back surface (bottom surface of 10) of the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13); a second electrode (50; [0028]) provided on a front surface (top surface of 13) of the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) at a side opposite to the back surface (bottom surface of 10); a third electrode (40; [0028]) provided between the first electrode (51) and the second electrode (50), the third electrode (40) being provided in the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) with a first insulating film (comprising 41 between 40 and 11, 41 between 20 and 13, 41 between 20 and 12, and 41 between 30 and 13; [0030]) interposed, the third electrode (40) being electrically insulated from the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) by the first insulating film (portion comprising 41 between 40 and 11); a control electrode (20; [0027]) provided between the second electrode (50) and the third electrode (40), the control electrode (20) extending into the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) from the front side (top surface of 13) of the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) and facing the third electrode (40) with a second insulating film (portion of 41 between 20 and 40 and portion of 41 between 30 and 40 except the portion of 41 immediately touching 30 that is between 30 and 40; [0030]) interposed, the first insulating film (portion comprising 41 between 20 and 13) extending between the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) and the control electrode (20) and electrically insulating the control electrode (20) from the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13); and a fourth electrode (30; [0027]) provided between the second electrode (50) and the third electrode (40), the fourth electrode (30) extending into the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) from the front side (top surface of 13) of the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) and being positioned between the semiconductor part (portions of 12 and 13 on the right side of the gate trench and the semiconductor part comprising p+ layer between 10 and 11, 10, 11, 12, and 13) and the control electrode (20), the first insulating film (portion of 41 between 30 and 13) extending between the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) and the fourth electrode (30), the second insulating film (portion of 41 between 30 and 40) extending between the third electrode (40) and the fourth electrode (30), the fourth electrode (30) facing the control electrode (20) with a third insulating film (portion of 41 immediately touching 30 that is between 30 and 40) interposed therebetween, the fourth electrode (30) being electrically connected (through 50; [0096]) to the third electrode (40), wherein the third electrode (40) and the fourth electrode (30) overlap each other (as shown in the Figure, there is a small amount of overlap between 30 and 40 at the inner edge of 30 and outer edge of 40 at the widest part) in a direction (vertical direction) from the back surface (bottom surface of 10) toward the front surface (top surface of 13) of the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13), wherein the third electrode (40) includes a draw-out portion (portion of 40 at the edge of the trench) at an end portion (edge portions) of a trench (11t; [0033]), and wherein the fourth electrode (30) is connected (30 is electrically connected to all portions of 40 as both are connected electrically through the source electrode and thus 40 is connected electrically to the draw-out portion, claim doesn’t state that they are physically connected at the end portion of the trench; [0028]) to the draw-out portion (portion of 40 at the edge of the trench) of the third electrode (40) at the end portion (edge portions) of the trench (11t); [claim 23] wherein: the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) includes first to fourth semiconductor layers (comprising p+ layer between 10 and 11, 10, 11, 12, and 13), the first semiconductor layer (11) being of a first conductivity type (n-type; [0026]) and extending between the first electrode (51) and the second electrode (50), the third electrode (40) facing the first semiconductor layer (11) via the first insulating film (comprising 41 between 40 and 11), the second semiconductor layer (12) being of a second conductivity type (p-type; [0026]) and provided between the first semiconductor layer (11) and the second electrode (50), the second semiconductor layer (12) facing the control electrode (20) with the first insulating film (comprising 41 between 20 and 12) interposed, the third semiconductor layer (13) being of the first conductivity type (n-type; [0026]) and partially provided on the second semiconductor layer (12), the third semiconductor layer (13) contacting the first insulating film (portion of 41 between 20 and 13 and 41 between 20 and 12) between the second semiconductor layer (12) and the second electrode (50), the fourth semiconductor layer (p+ layer between 10 and 11; [0098]) being of the second conductivity type (p-type; [0098]) and provided between the first semiconductor layer (11) and the first electrode (51), the control electrode (20) and the fourth electrode (30) are electrically insulated from each other (20 is a gate electrode and is connected to the gate terminal and the fourth electrode is a field plate and is connected to the source terminal and are not electrically connected to one another; [0028]); and the fourth electrode (30) faces (interpreted to mean -to have the front oriented toward-, as 30 has the outer vertical side, the front side, oriented toward the third semiconductor layer 13 along the horizontal direction) the third semiconductor layer (13) with the first insulating film (portion of 41 between 30 and 13) interposed therebetween; [claim 25] wherein: the second electrode (50) is provided on the control electrode (20) and the fourth electrode (30) with a fourth insulating film (41 on a top surface of 20, 30, and 40; [0030]) interposed, and the control electrode (20) and the fourth electrode (30) are electrically insulated from the second electrode (50) by the fourth insulating film (41 on a top surface of 20, 30, and 40); [claim 26] wherein a third semiconductor layer (13; [0030]) faces the control electrode (20) with the first insulating film (comprising 41 between 20 and 13) interposed; [claim 30] further comprising: a second third-electrode (40 in second from the left trench) provided between the first electrode (51) and the second electrode (50), the second third-electrode (40) being provided in the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) with a second first-insulating film (comprising 41 between 40 and 11, 41 between 20 and 13, 41 between 20 and 12, and 41 between 30 and 13 in second from the left trench) interposed and being electrically insulated from the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) by the second first-insulating film (portion of 41 between 40 and 11); a second control electrode (20 in second from the left trench) provided between the second electrode (50) and the second third-electrode (40 in second from the left trench), the second control electrode (20 in second from the left trench) extending into the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) from the front side (top surface of 13) of the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) and facing the second third-electrode (40 in second from the left trench) with a second second-insulating film (portion of 41 between 20 and 40 and portion of 41 between 30 and 40 except the portion of 41 immediately touching 30 that is between 30 and 40 in second from the left trench) interposed, the second first-insulating film (portion of 41 between 20 and 12 and the portion of 41 between 20 and 13) extending between the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) and the second control electrode (20 in second from the left trench) and electrically insulating the second control electrode (second from the left trench) from the semiconductor part (portions 12 and 13); and a second fourth-electrode (30 in second from the left trench) provided between the second electrode (50) and the second third-electrode (40 in second from the left trench), the second fourth-electrode (30 in second from the left trench) extending into the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) from the front side (top surface of 13) of the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) and being positioned between the semiconductor part (portion of 12 and 13 on the right of the trench) and the second control electrode (20 in second from the left trench), the second first-insulating film (portion of 41 between 30 and 12) extending between the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) and the second fourth-electrode (30 in second from the left trench), the second second-insulating film (portion of 41 between 20 and 40 and portion of 41 between 30 and 40 except the portion of 41 immediately touching 30 that is between 30 and 40 in second from the left trench) extending between the second third-electrode (20 in second from the left trench) and the second fourth-electrode (30 in second from the left trench), the second fourth-electrode (30 in second from the left trench) facing the second control electrode (20 in second from the left trench) with a second third-insulating film (portion of 41 immediately touching 30 that is between 30 and 40 in second from the left trench) interposed and being electrically connected (through 50) to the second third-electrode (40 in second from the left trench), the second fourth-electrode (30 in second from the left trench) facing the fourth electrode (30 in first trench from the left) via the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13); [claim 31] further comprising: a second third-electrode (40 in second from the left trench) provided between the first electrode (51) and the second electrode (50), the second third-electrode (40) being provided in the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) with a second first-insulating film (comprising 41 between 40 and 11, 41 between 20 and 13, 41 between 20 and 12, and 41 between 30 and 13 in second from the left trench) interposed and being electrically insulated from the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) by the second first-insulating film (portion of 41 between 40 and 11); a second control electrode (20 in second from the left trench) provided between the second electrode (50) and the second third-electrode (40 in second from the left trench), the second control electrode (20 in second from the left trench) extending into the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) from the front side (top surface of 13) of the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) and facing the second third-electrode (40 in second from the left trench) with a second second-insulating film (portion of 41 between 20 and 40 and portion of 41 between 30 and 40 except the portion of 41 immediately touching 30 that is between 30 and 40 in second from the left trench) interposed, the second first-insulating film (portion of 41 between 20 and 12 and the portion of 41 between 20 and 13) extending between the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) and the second control electrode (20 in second from the left trench) and electrically insulating the second control electrode (second from the left trench) from the semiconductor part (portions 12 and 13); and a second fourth-electrode (30 in second from the left trench) provided between the second electrode (50) and the second third-electrode (40 in second from the left trench), the second fourth-electrode (30 in second from the left trench) extending into the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) from the front side (top surface of 13) of the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) and being positioned between the semiconductor part (portion of 12 and 13 on the right of the trench) and the second control electrode (20 in second from the left trench), the second first-insulating film (portion of 41 between 30 and 12) extending between the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) and the second fourth-electrode (30 in second from the left trench), the second second-insulating film (portion of 41 between 20 and 40 and portion of 41 between 30 and 40 except the portion of 41 immediately touching 30 that is between 30 and 40 in second from the left trench) extending between the second third-electrode (20 in second from the left trench) and the second fourth-electrode (30 in second from the left trench), the second fourth-electrode (30 in second from the left trench) facing the second control electrode (20 in second from the left trench) with a second third-insulating film (portion of 41 immediately touching 30 that is between 30 and 40 in second from the left trench) interposed and being electrically connected (through 50) to the second third-electrode (40 in second from the left trench), the second control electrode (20 in second from the left trench) facing the control electrode (20 in first trench from the left) via the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2, 7, and 29 are rejected under 35 U.S.C. 103 as being unpatentable over Nozu in view of Tokuda (US 2024/0088238 and Tokuda hereinafter).
As to claims 2 and 7: Nozu combined with Nishiwaki discloses [claim 2] wherein: the second electrode (50) is provided on the control electrode (20) and the fourth electrode (30) with a fourth insulating film (Figs. 6A and 15; 60; [0045]) interposed between the second electrode (50) and the control electrode (20), and the control electrode (20) is electrically insulated from the second electrode (50) by the fourth insulating film (60).
Nozu fails to expressly disclose [claim 2] where the fourth insulating film is interposed between the second electrode and the fourth electrode and the fourth electrode is electrically insulated from the second electrode by the fourth insulating film; [claim 7] further comprising: a first control pad provided at the front side of the semiconductor part, the first control pad being apart from the second electrode and electrically connected to the control electrode via a first interconnect; and a second control pad provided at the front side of the semiconductor layer, the second control pad being apart from the second electrode and the first control pad and electrically connected to the third electrode via a second interconnect.
Nozu discloses a vertical semiconductor device with a gate electrode and field plate in a trench in the substrate where the third electrode (FP electrode) 40 is electrically connected to the fourth electrode 30 and to the second electrode 50.
Tokuda discloses in Figs. 1, 4, and 5 [0032]-[0034] a vertical semiconductor device with a gate electrode and field plate in a trench in the substrate where the field plate electrode FP is electrically isolated from the second electrode SE by the fourth insulating film IL and [claim 7] further comprising: a first control pad (Fig. 1; GP; [0034]) provided at the front side (top surface of SUB; [0043]) of the semiconductor part (SUB; [0043]), the first control pad (GP) being apart from the second electrode (SE; [0033]-[0034]) and electrically connected to the control electrode (GE; [0032]) via a first interconnect (Fig. 5; first interconnect GW; [0032]); and a second control pad (Fig. 1; FPP; [0034]) provided at the front side (top surface of SUB) of the semiconductor layer (SUB), the second control pad (FPP) being apart from the second electrode (SE) and the first control pad (GP) and electrically connected (through FPW; [0032]-[0034]) to the third electrode (FP; [0035]) via a second interconnect (Fig. 4; FPW; [0032]-[0034]).
When the structure of connecting the field plate electrode FP of Tokuda is used to modify the connection of the field plate comprising 30 and 40 of Nozu, 30 and 40 of Nozu will be connected to the field plate wiring FPW (as in Tokuda) and not to the fourth/source electrode 50 of Nozu and will be isolated from the fourth/source electrode 50 of Nozu by the fourth insulating layer (60 of Nozu/IL of Tokuda).
Given the teachings of Tokuda, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Nozu by employing the well-known or conventional features of vertical transistor fabrication, such as displayed by Tokuda, by employing a separate pad (from the source electrode and gate electrode/pad) for the field plate electrodes in order to independently control the voltage of the field plate in order to reduce the on-resistance of the device ([0009]).
As to claim 29: Although the structure disclosed by Nozu shows substantial features of the claimed invention (discussed in paragraph 9 above), it fails to expressly disclose:
further comprising: a first control pad provided at the front side of the semiconductor part, the first control pad being apart from the second electrode and electrically connected to the control electrode via a first interconnect; and a second control pad provided at the front side of a semiconductor layer, the second control pad being apart from the second electrode and the first control pad and electrically connected to the third electrode via a second interconnect.
Nozu discloses a vertical semiconductor device with a gate electrode and field plate in a trench in the substrate where the third electrode (FP electrode) 40 is electrically connected to the fourth electrode 30 and to the second electrode 50.
Tokuda discloses in Figs. 1, 4, and 5 [0032]-[0034] a vertical semiconductor device with a gate electrode and field plate in a trench in the substrate where the field plate electrode FP is electrically isolated from the second electrode SE by the fourth insulating film IL and further comprising: a first control pad (Fig. 1; GP; [0034]) provided at the front side (top surface of SUB; [0043]) of the semiconductor part (SUB; [0043]), the first control pad (GP) being apart from the second electrode (SE; [0033]-[0034]) and electrically connected to the control electrode (GE; [0032]) via a first interconnect (Fig. 5; first interconnect GW; [0032]); and a second control pad (Fig. 1; FPP; [0034]) provided at the front side (top surface of SUB) of a semiconductor layer (SUB), the second control pad (FPP) being apart from the second electrode (SE) and the first control pad (GP) and electrically connected (through FPW; [0032]-[0034]) to the third electrode (FP; [0035]) via a second interconnect (Fig. 4; FPW; [0032]-[0034]).
Given the teachings of Tokuda, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Nozu by employing the well-known or conventional features of vertical transistor fabrication, such as displayed by Tokuda, by employing a separate pad (from the source electrode and gate electrode/pad) for the field plate electrodes in order to independently control the voltage of the field plate in order to reduce the on-resistance of the device ([0009]).
Allowable Subject Matter
Claim 24 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 7/13/2026 have been fully considered but they are not persuasive.
In the remarks, applicant argues in substance that:
Nozu does not disclose or suggest wherein the control electrode and the fourth electrode are electrically insulated from each other, and wherein the fourth electrode faces the third semiconductor layer with the first insulating film interposed therebetween. Nozu discloses that electrode 30 is fixed at the source potential. However, Nozu does not disclose or suggest at least rearranging electrode 30 to face a layer corresponding to the N+ emitter layer 13 while the control electrode and the fourth electrode are electrically insulated from each other.
Nozu does not disclose wherein the third electrode and the fourth electrode overlap each other in a direction from the back surface toward the front surface of the semiconductor part, wherein the third electrode includes a draw-out portion at an end portion of a trench, and wherein the fourth electrode is connected to the draw-out portion of the third electrode at the end portion of the trench.
Examiner respectfully traverses applicant’s remarks.
As to point a), Nozu discloses that the control electrode 20 is a gate electrode and is connected to the gate terminal and the fourth electrode is a field plate and is connected to the source terminal and are not electrically connected to one another ([0028]) and are thus electrically insulated from one another. Further, it appears as though applicant is taking a narrower interpretation of the term “faces”. A broadest reasonable interpretation of the term “faces” is -to have the front oriented toward-, as 30 has the outer vertical side, the front side, oriented toward the third semiconductor layer 13 along the horizontal direction. Applicant is perhaps arguing that the N+ emitter layer 13 and the fourth electrode should both physically contact opposite surfaces of the insulating layer between them, as applicant’s drawings show in Fig. 1 with the fourth electrode 60 and the third semiconductor layer 15 facing each other and both directly contacting the insulating layer 25 between them. However, this is not claimed and there is no special definition provided in the specification by applicant for the claimed term “faces” that would restrict one to the interpretation by applicant in the arguments.
As to point b), Nozu shows in Figure 1 that there is a small amount of overlap between 30 (the fourth electrode) and 40 (fourth electrode) at the inner edge of 30 and outer edge of 40 at the widest part in the vertical direction. Further, applicant doesn’t state in the claim what a draw-out portion is. Therefore, Examiner interprets it to be the portion of 40 that is adjacent to the sidewalls of the trench. Further, as 30 (the fourth electrode) is electrically connected to all portions of 40 (the third electrode), the third electrode’s draw-out portion and the fourth electrode are electrically connected. The claim doesn’t state that the fourth electrode and the draw-out portion are physically connected at the end portion of the trench.
Conclusion
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JOSEPH C. NICELY
Primary Examiner
Art Unit 2813
/JOSEPH C. NICELY/Primary Examiner, Art Unit 2813
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