DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I (claims 1-4, 7, and 21) in the reply filed on 9/11/2025 is acknowledged.
Claims 5, 6, and 8-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 9/11/2025.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3, 4, and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nozu (US 2014/0077278 and Nozu hereinafter).
As to claims 1, 3, 4, and 21: Nozu discloses [claim 1] a semiconductor device (Fig. 15), comprising: a semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13; [0026] and [0098]); a first electrode (51; [0028]) provided on a back surface (bottom surface of 10) of the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13); a second electrode (50; [0028]) provided on a front surface (top surface of 13) of the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) at a side opposite to the back surface (bottom surface of 10); a third electrode (40; [0028]) provided between the first electrode (51) and the second electrode (50), the third electrode (40) being provided in the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) with a first insulating film (comprising 41 between 40 and 11, 41 between 20 and 13, 41 between 20 and 12, and 41 between 30 and 13; [0030]) interposed, the third electrode (40) being electrically insulated from the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) by the first insulating film (portion comprising 41 between 40 and 11); a control electrode (20; [0027]) provided between the second electrode (50) and the third electrode (40), the control electrode (20) extending into the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) from the front side (top surface of 13) of the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) and facing the third electrode (40) with a second insulating film (portion of 41 between 20 and 40 and portion of 41 between 30 and 40 except the portion of 41 immediately touching 30 that is between 30 and 40; [0030]) interposed, the first insulating film (portion comprising 41 between 20 and 13) extending between the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) and the control electrode (20) and electrically insulating the control electrode (20) from the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13); and a fourth electrode (30; [0027]) provided between the second electrode (50) and the third electrode (40), the fourth electrode (30) extending into the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) from the front side (top surface of 13) of the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) and being positioned between the semiconductor part (portions of 12 and 13 on the right side of the gate trench and the semiconductor part comprising p+ layer between 10 and 11, 10, 11, 12, and 13) and the control electrode (20), the first insulating film (portion of 41 between 30 and 13) extending between the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) and the fourth electrode (30), the second insulating film (portion of 41 between 30 and 40) extending between the third electrode (40) and the fourth electrode (30), the fourth electrode (30) facing the control electrode (20) with a third insulating film (portion of 41 immediately touching 30 that is between 30 and 40) interposed, the fourth electrode (30) being electrically connected (through 50; [0096]) to the third electrode (40); [claim 3] wherein the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) includes first to fourth semiconductor layers (comprising p+ layer between 10 and 11, 10, 11, 12, and 13), the first semiconductor layer (11) being of a first conductivity type (n-type; [0026]) and extending between the first electrode (51) and the second electrode (50), the third electrode (40) facing the first semiconductor layer (11) via the first insulating film (comprising 41 between 40 and 11), the second semiconductor layer (12) being of a second conductivity type (p-type; [0026]) and provided between the first semiconductor layer (11) and the second electrode (50), the second semiconductor layer (12) facing the control electrode (20) with the first insulating film (comprising 41 between 20 and 12) interposed, the third semiconductor layer (13) being of the first conductivity type (n-type; [0026]) and partially provided on the second semiconductor layer (12), the third semiconductor layer (13) contacting the first insulating film (portion of 41 between 20 and 13 and 41 between 20 and 12) between the second semiconductor layer (12) and the second electrode (50), the fourth semiconductor layer (p+ layer between 10 and 11; [0098]) being of the second conductivity type (p-type; [0098]) and provided between the first semiconductor layer (11) and the first electrode (51); [claim 4] wherein the third semiconductor layer (13) faces the control electrode (20) with the first insulating film (portion of 41 between 20 and 13) interposed; [claim 21] further comprising: a second third-electrode (40 in second from the left trench) provided between the first electrode (51) and the second electrode (50), the second third-electrode (40) being provided in the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) with a second first-insulating film (comprising 41 between 40 and 11, 41 between 20 and 13, 41 between 20 and 12, and 41 between 30 and 13 in second from the left trench) interposed and being electrically insulated from the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) by the second first-insulating film (portion of 41 between 40 and 11); a second control electrode (20 in second from the left trench) provided between the second electrode (50) and the second third-electrode (40 in second from the left trench), the second control electrode (20 in second from the left trench) extending into the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) from the front side (top surface of 13) of the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) and facing the second third-electrode (40 in second from the left trench) with a second second-insulating film (portion of 41 between 20 and 40 and portion of 41 between 30 and 40 except the portion of 41 immediately touching 30 that is between 30 and 40 in second from the left trench) interposed, the second first-insulating film (portion of 41 between 20 and 12 and the portion of 41 between 20 and 13) extending between the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) and the second control electrode (20 in second from the left trench) and electrically insulating the second control electrode (second from the left trench) from the semiconductor part (portions 12 and 13); and a second fourth-electrode (30 in second from the left trench) provided between the second electrode (50) and the second third-electrode (40 in second from the left trench), the second fourth-electrode (30 in second from the left trench) extending into the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) from the front side (top surface of 13) of the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) and being positioned between the semiconductor part (portion of 12 and 13 on the right of the trench) and the second control electrode (20 in second from the left trench), the second first-insulating film (portion of 41 between 30 and 12) extending between the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13) and the second fourth-electrode (30 in second from the left trench), the second second-insulating film (portion of 41 between 20 and 40 and portion of 41 between 30 and 40 except the portion of 41 immediately touching 30 that is between 30 and 40 in second from the left trench) extending between the second third-electrode (20 in second from the left trench) and the second fourth-electrode (30 in second from the left trench), the second fourth-electrode (30 in second from the left trench) facing the second control electrode (20 in second from the left trench) with a second third-insulating film (portion of 41 immediately touching 30 that is between 30 and 40 in second from the left trench) interposed and being electrically connected (through 50) to the second third-electrode (40 in second from the left trench), the second control electrode (20 in second from the left trench) facing the fourth electrode (30 in first trench from the left) via the semiconductor part (comprising p+ layer between 10 and 11, 10, 11, 12, and 13).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Nozu in view of Tokuda (US 2024/0088238 and Tokuda hereinafter)
As to claims 2 and 7: Nozu discloses [claim 2] wherein the second electrode (50) is provided on the control electrode (20) and the fourth electrode (30) with a fourth insulating film (Figs. 6A and 15; 60; [0045]) interposed between the second electrode (50) and the control electrode (20), and the control electrode (20) is electrically insulated from the second electrode (50) by the fourth insulating film (60).
Nozu fails to expressly disclose [claim 2] where the fourth insulating film is interposed between the second electrode and the fourth electrode and the fourth electrode is electrically insulated from the second electrode by the fourth insulating film; [claim 7] further comprising: a first control pad provided at the front side of the semiconductor part, the first control pad being apart from the second electrode and electrically connected to the control electrode via a first interconnect; and a second control pad provided at the front side of the semiconductor layer, the second control pad being apart from the second electrode and the first control pad and electrically connected to the third electrode via a second interconnect.
Nozu discloses a vertical semiconductor device with a gate electrode and field plate in a trench in the substrate where the third electrode (FP electrode) 40 is electrically connected to the fourth electrode 30 and to the second electrode 50.
Tokuda discloses in Figs. 1, 4, and 5 [0032]-[0034] a vertical semiconductor device with a gate electrode and field plate in a trench in the substrate where the field plate electrode FP is electrically isolated from the second electrode SE by the fourth insulating film IL and [claim 7] further comprising: a first control pad (Fig. 1; GP; [0034]) provided at the front side (top surface of SUB; [0043]) of the semiconductor part (SUB; [0043]), the first control pad (GP) being apart from the second electrode (SE; [0033]-[0034]) and electrically connected to the control electrode (GE; [0032]) via a first interconnect (Fig. 5; first interconnect GW; [0032]); and a second control pad (Fig. 1; FPP; [0034]) provided at the front side (top surface of SUB) of the semiconductor layer (SUB), the second control pad (FPP) being apart from the second electrode (SE) and the first control pad (GP) and electrically connected (through FPW; [0032]-[0034]) to the third electrode (FP; [0035]) via a second interconnect (Fig. 4; FPW; [0032]-[0034]).
When the structure of connecting the field plate electrode FP of Tokuda is used to modify the connection of the field plate comprising 30 and 40 of Nozu, 30 and 40 of Nozu will be connected to the field plate wiring FPW (as in Tokuda) and not to the fourth/source electrode 50 of Nozu and will be isolated from the fourth/source electrode 50 of Nozu by the fourth insulating layer (60 of Nozu/IL of Tokuda).
Given the teachings of Tokuda, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Nozu by employing the well-known or conventional features of vertical transistor fabrication, such as displayed by Tokuda, by employing a separate pad (from the source electrode and gate electrode/pad) for the field plate electrodes in order to independently control the voltage of the field plate in order to reduce the on-resistance of the device ([0009]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH C NICELY whose telephone number is (571)270-3834. The examiner can normally be reached Monday-Friday 7:30 am - 4 pm, EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at (571) 270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
JOSEPH C. NICELY
Primary Examiner
Art Unit 2813
/JOSEPH C. NICELY/Primary Examiner, Art Unit 2813