Prosecution Insights
Last updated: April 19, 2026
Application No. 18/115,775

MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE

Non-Final OA §102§103
Filed
Mar 01, 2023
Examiner
NARAGHI, ALI
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
United Semiconductor Japan Co., Ltd.
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
2y 8m
To Grant
93%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allow Rate
666 granted / 771 resolved
+18.4% vs TC avg
Moderate +6% lift
Without
With
+6.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
24 currently pending
Career history
795
Total Applications
across all art units

Statute-Specific Performance

§101
1.1%
-38.9% vs TC avg
§103
61.6%
+21.6% vs TC avg
§102
19.0%
-21.0% vs TC avg
§112
13.1%
-26.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 771 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of claims 1-10 in the reply filed on 02/24/2026 is acknowledged. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wu et al (US Pub No. 20170125413). With respect to claim 1, Wu et al discloses :forming a fin-shaped structure (1615,1620,1650,Fig.17) on a semiconductor substrate (1605), wherein the fin-shaped structure extends upwards from a top surface of the semiconductor substrate in a vertical direction (Fig.17), and at least a part of a first doped region is located in the fin-shaped structure (1620); forming a second doped region in the fin-shaped structure (1650), wherein the second doped region is located above the first doped region in the vertical direction (Fig.17), and the second doped region is separated from the first doped region by an intermediate region located in the fin-shaped structure (Para 20-30,630 which is above the white line,Fig.13); and forming a gate structure (1770,1780) straddling a part of the fin-shaped structure (Fig.17), wherein a bottom surface of the gate structure is lower than (Fig.17) or coplanar with a top surface of the first doped region in the vertical direction (Fig.17). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 2-3,5-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al (US Pub No. 20170125413), in view of Hong et al (US Pub No. 20120292715). With respect to claim 2, Wu et al does not explicitly disclose, wherein a method of forming the gate structure comprises: forming a dummy gate straddling the fin-shaped structure; and replacing the dummy gate with the gate structure. On the other hand, Hong discloses forming a dummy gate straddling the fin-shaped structure (155’,Fig.5); and replacing the dummy gate with the gate structure (140,Fig.23). It would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Wu et al according to the teachings Hong et al such that dummy gate straddling the fin-shaped structure; and replacing the dummy gate with the gate structure, in order to protect the gate from further, processing. With respect to claim 3, Hong discloses forming a patterned material layer (155,Fig.4) on the semiconductor substrate (100) after the step of forming the fin-shaped structure (Fig.3); and performing an etching process to the patterned material layer (Para 69), wherein the patterned material layer is etched to be the dummy gate by the etching process (Fig.4). With respect to claim 5, Wu et al in view of Hong discloses wherein the dummy gate covers a part of a side surface of the intermediate region in a horizontal direction (Fig.4). With respect to claim 6, Wu et al in view of Hong et discloses wherein the dummy gate further covers a part of a side surface of the first doped region in the horizontal direction (Fig.4). With respect to claim 7, wherein the dummy gate comprises: a first portion (top portion of the 155); and a second portion disposed on the first portion (side portion of the 155), wherein a width of the first portion of the dummy gate is greater than a width of the second portion of the dummy gate (Fig.4). "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Claim(s) 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu et al (US Pub No. 20170125413). With respect to claim 9, the arts cited above do not explicitly disclose wherein a conductivity type of the second doped region is complementary to a conductivity type of the first doped region. On the other hand, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Wu et al such that the second and first doping are complementary to each other, in order to make source or drain for PMOS or NMOs device. With respect to claim 10, Wu et al discloses wherein a conductivity type of the intermediate region is identical to the conductivity type of the first doped region (Para 20-23, because they are all made from the same diffusion process), however, Wu et al does not explicitly disclose and an impurity concentration in the first doped region is higher than an impurity concentration in the intermediate region. However, "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Furthermore, it would have been obvious to one of ordinary skill in the art at the time of the filing of the invention to modify Wu et al such that an impurity concentration in the first doped region is higher than an impurity concentration in the intermediate region, as a design choice. Allowable Subject Matter Claims 4,8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALI N NARAGHI whose telephone number is (571)270-5720. The examiner can normally be reached 10am-6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ALI NARAGHI/Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Mar 01, 2023
Application Filed
Mar 07, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
93%
With Interview (+6.3%)
2y 8m
Median Time to Grant
Low
PTA Risk
Based on 771 resolved cases by this examiner. Grant probability derived from career allow rate.

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