Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed 02/26/2026 has been entered. Claims 1, 3, 10, 16, 18 are amended. Claims 2, 17 are canceled. Claims 1, 3 – 16, 18 – 20 remain pending in the application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4 – 6, 9, 16, 18 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng ( Pub. No. US 20200328180 A1 ), hereinafter Cheng, in view of Sharma (Pub. No. 20190393222 A1), hereinafter Sharma, and Liu ( Pub. No. 20200328176 A1), hereinafter Liu.
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Regarding Independent Claim 1 ( Currently Amended ), Cheng teaches a three-dimensional (3D) memory device ( Cheng, FIG. 7A, 700; [0078], semiconductor device 700 ), comprising:
a first die of a 3D memory structure ( Cheng, FIG. 7A, 702; [0078], first semiconductor structure 702; [0088], In some embodiments, first semiconductor structure 702 of semiconductor device 700 includes a NAND flash memory device in which memory cells are provided in the form of an array of 3D NAND memory strings 736 above interconnect layer 734 and bonding layer 730 ),
a second die ( Cheng, FIG. 7A, 704; [0078], second semiconductor structure 704; [0098], Second semiconductor structure 704 of semiconductor device 700 can further include an array of DRAM cells 756 above interconnect layer 754 and bonding layer 750 ) bonded with the first die; and
a third die ( Cheng, FIG. 7A, 706; [0078], third semiconductor structure 706 ) of a periphery structure (Cheng, FIG. 7A, 714, 716, 718, 720; [0081], SRAM cells 718 on substrate 712 and outside of processor 716. In some embodiments, device layer 714 further includes a peripheral circuit 720 on substrate 712 and outside of processor 716 ) bonded with the first die ( Cheng, FIG. 7A, 702; [0078] ) and/or the second die ( Cheng, FIG. 7A, 704; [0078] ), wherein the second die ( Cheng, FIG. 7A, 704, [0078] ) comprises a plurality of dynamic random-access memory (DRAM) cells, and
the 3D memory structure ( Cheng, FIG. 7A, 702; [0078] ) comprises a conductor/insulator stack ( Cheng, FIG. 7A, 738; [0088], The stacked and interleaved conductor layers and dielectric layer are also referred to herein as a memory stack 738 ) including a conductive layer and a dielectric layer alternatingly stacked, and a region of memory cells ( Cheng, FIG. 7A, 736; [0088], Each 3D NAND memory string 736 extends vertically through a plurality of pairs each including a conductor layer and a dielectric layer ) in the conductor/insulator stack.
Cheng fails to disclose:
wherein a DRAM cell of the plurality of DRAM cells includes a transistor, the transistor including a vertical gate structure, a source region, and a drain region, and the source region and the drain region are stacked along a vertical direction.
However, Sharma teaches:
wherein a DRAM cell of the plurality of DRAM cells includes a transistor, the transistor including a vertical gate structure ( Sharma, [0001], 4F2 DRAM cell that is implemented with vertical thin film transistors (VTFTs) ), a source region, and a drain region, and the source region and the drain region are stacked along a vertical direction ( Sharma, Abstract, a source region may be below the gate electrode and a drain region may be above the gate electrode … a channel region may be between the source region and the drain region; FIG. 3A, [0042], a source region 316 formed below a lowermost surface 363 of the gate electrode 312 and a drain region 318 formed above the uppermost surface 362 of the gate electrode 312. In an embodiment, a channel region 315 may be formed between the source region 316 and the drain region 318. For example, the channel region 315 may be formed along the sidewall surfaces 361 of the gate electrode 312 ).
Cheng and Sharma are both considered to be analogous to the claimed invention because they are forming DRAM. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Cheng ( Second semiconductor structure 704 of semiconductor device 700 can further include an array of DRAM cells 756 ), to incorporate the teachings of Sharma ( 4F2 DRAM cell that is implemented with vertical thin film transistors (VTFTs) ), to implement that wherein a DRAM cell of the plurality of DRAM cells includes a transistor, the transistor including a vertical gate structure, a source region, and a drain region, and the source region and the drain region are stacked along a vertical direction. Doing so would provide specific vertical channel transistors with low leakage for DRAM, and therefore the low-leakage DRAM devices by integrating double wall three-dimensional (DW3D) capacitors can be implemented.
Cheng and Sharma do not explicitly disclose:
the first die, the second die, and the third die are aligned in a vertical direction.
However, Liu teaches:
the first die, the second die, and the third die are aligned in a vertical direction ( Liu, FIG. 1, 102, 104, 106 ; FIG. 7A, 704, 706, 702; [0067], Second semiconductor structure 704 of 3D memory device 700 can include an array of DRAM cells 714; [0074] Third semiconductor structure 706 of 3D memory device 700 can also include array of SRAM cells 734 above and in contact with semiconductor layer 766. In some embodiments, a peripheral circuit is also formed above and in contact with semiconductor layer 766, i.e., in the same plane as array of SRAM cells 734; [0080], As shown in FIG. 7A, first semiconductor structure 702 of 3D memory device 700 includes a NAND flash memory device; [0054], By vertically integrating first, second, and third semiconductor structures 102, 104, and 106 having heterogeneous memories, the memory chip size can be reduced, and the memory cell density can be increased ).
Cheng and Sharma and Liu are all considered to be analogous to the claimed invention because they are forming three-dimensional (3D) memory and DRAM. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Cheng ( Second semiconductor structure 704 of semiconductor device 700 can further include an array of DRAM cells 756 ) and Sharma ( 4F2 DRAM cell that is implemented with vertical thin film transistors (VTFTs) ), to incorporate the teachings of Liu ( [0054], By vertically integrating first, second, and third semiconductor structures 102, 104, and 106 having heterogeneous memories, the memory chip size can be reduced, and the memory cell density can be increased ), to implement that the first die, the second die, and the third die are aligned in a vertical direction. Doing so would reduce memory chip size, and therefore memory cell density can be increased.
Regarding Claim 4 ( Previously Presented ), Cheng and Sharma and Liu teach the 3D memory device as claimed in claim 1 on which this claim is dependent, Cheng further teaches:
wherein the plurality of DRAM cells ( Cheng, FIG. 7A, 756; [0098], Second semiconductor structure 704 of semiconductor device 700 can further include an array of DRAM cells 756 above interconnect layer 754 and bonding layer 750 ) form a pattern ( Cheng, FIG. 7A, 756; [0098], array of DRAM cells 756 ) in a plane ( Cheng, FIG. 7A, 762; [0098], semiconductor layer 762 ), the vertical gate structure ( Cheng, FIG. 7A, 758; [0098], DRAM selection transistor 758; Sharma, [0001], 4F2 DRAM cell that is implemented with vertical thin film transistors (VTFTs) ) extending in a direction ( Cheng, FIG. 7A, 758; [0098], vertically formed DRAM selection transistor 758 ) perpendicular to the plane ( Cheng, FIG. 7A, 762; [0098] ).
Regarding Claim 5 ( Previously Presented ), Cheng and Sharma and Liu teach the 3D memory device as claimed in claim 1 on which this claim is dependent, Cheng further teaches:
wherein the DRAM cell further includes a capacitor ( Cheng, FIG. 7A, 760; [0098], Each capacitor 760 includes two electrodes, one of which is electrically connected to one node of respective DRAM selection transistor 758 ) stacked on the vertical gate structure with an electrode ( Cheng, FIG. 7A, 766; [0098], Another electrode of each capacitor 760 can be electrically connected to a common plate 766, e.g., a common ground ) extending in the vertical direction ( Cheng, FIG. 7A, 760; [0098], For example, capacitor 760 may be a planar capacitor, a stack capacitor, a multi-fins capacitor, a cylinder capacitor, a trench capacitor, or a substrate-plate capacitor ).
Regarding Claim 6 ( Original ), Cheng and Sharma and Liu teach the 3D memory device as claimed in claim 1 on which this claim is dependent, Cheng further teaches:
wherein the second die (Cheng, FIG. 7A, 704; [0098], second semiconductor structure 704, DRAM) further comprises:
a circuit ( Cheng, FIG. 7A, 758, 764, 754, 772; [0098], Another node of each DRAM selection transistor 758 is electrically connected to a bit line 764 of DRAM; [0101], In some embodiments, second semiconductor structure 704 further includes one or more contacts 772 extending through semiconductor layer 762 to electrically connect pad-out interconnect layer 768 and interconnect layers 754 and 724. As a result, processor 716 and array of SRAM cells 718 (and peripheral circuit 720 if any) can be electrically connected to array of DRAM cells 756 through interconnect layers 754 and 724 as well as bonding contacts 752 and 728 ) arranged to support operation of the 3D memory device.
Regarding Claim 9 ( Previously Presented ), Cheng and Sharma and Liu teach the 3D memory device as claimed in claim 1 on which this claim is dependent, Cheng further teaches:
wherein the second die ( Cheng, FIG. 7A, 704; [0098], second semiconductor structure 704, DRAM ) includes a substrate (Cheng, FIG. 7A, 762; [0098], semiconductor layer 762 supporting DRAM cells 756), the vertical gate structure is formed in the substrate, and a dielectric region ( Cheng, [0098], For example, capacitor 760 may be a planar capacitor, a stack capacitor, a multi-fins capacitor, a cylinder capacitor, a trench capacitor, or a substrate-plate capacitor ) is formed through the substrate.
Regarding Independent Claim 16 ( Currently Amended ), Cheng teaches a method for fabricating a three-dimensional (3D) memory device, comprising:
providing a first die of a 3D memory structure ( Cheng, FIG. 7A, 702; [0078], first semiconductor structure 702; [0088], In some embodiments, first semiconductor structure 702 of semiconductor device 700 includes a NAND flash memory device in which memory cells are provided in the form of an array of 3D NAND memory strings 736 above interconnect layer 734 and bonding layer 730 ), the 3D memory structure comprising a conductor/insulator stack ( Cheng, FIG. 7A, 738; [0088], The stacked and interleaved conductor layers and dielectric layer are also referred to herein as a memory stack 738 ) including a conductive layer and a dielectric layer alternatingly stacked, and a region of memory cells ( Cheng, FIG. 7A, 736; [0088], Each 3D NAND memory string 736 extends vertically through a plurality of pairs each including a conductor layer and a dielectric layer ) in the conductor/insulator stack;
providing a second die ( Cheng, FIG. 7A, 704; [0078], second semiconductor structure 704; [0098], Second semiconductor structure 704 of semiconductor device 700 can further include an array of DRAM cells 756 above interconnect layer 754 and bonding layer 750 ), the second die comprising a plurality of dynamic random-access memory (DRAM) cells; and
providing a third die ( Cheng, FIG. 7A, 706; [0078], third semiconductor structure 706 ) of a periphery structure (Cheng, FIG. 7A, 714, 716, 718, 720; [0081], SRAM cells 718 on substrate 712 and outside of processor 716. In some embodiments, device layer 714 further includes a peripheral circuit 720 on substrate 712 and outside of processor 716 ); and
bonding the first die the second die ( Cheng, FIG. 7A, 726, 730, 750; [0084], bonding layer 726; [0085], bonding layer 730; [0095], bonding layer 750 ), and the third die (Cheng, FIG. 7A, 706).
Cheng fails to disclose:
Wherein a DRAM cell of the plurality of DRAM cells includes a transistor, the transistor includes a vertical gate structure, a source region, and a drain region, and the source region and the drain region are stacked along a vertical direction.
However, Sharma teaches:
wherein a DRAM cell of the plurality of DRAM cells includes a transistor, the transistor including a vertical gate structure ( Sharma, [0001], 4F2 DRAM cell that is implemented with vertical thin film transistors (VTFTs) ), a source region, and a drain region, and the source region and the drain region are stacked along a vertical direction ( Sharma, Abstract, a source region may be below the gate electrode and a drain region may be above the gate electrode … a channel region may be between the source region and the drain region; FIG. 3A, [0042], a source region 316 formed below a lowermost surface 363 of the gate electrode 312 and a drain region 318 formed above the uppermost surface 362 of the gate electrode 312. In an embodiment, a channel region 315 may be formed between the source region 316 and the drain region 318. For example, the channel region 315 may be formed along the sidewall surfaces 361 of the gate electrode 312 ).
Cheng and Sharma are both considered to be analogous to the claimed invention because they are forming DRAM. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Cheng ( Second semiconductor structure 704 of semiconductor device 700 can further include an array of DRAM cells 756 ), to incorporate the teachings of Sharma ( 4F2 DRAM cell that is implemented with vertical thin film transistors (VTFTs) ), to implement that wherein a DRAM cell of the plurality of DRAM cells includes a transistor, the transistor including a vertical gate structure, a source region, and a drain region, and the source region and the drain region are stacked along a vertical direction. Doing so would provide specific vertical channel transistors with low leakage for DRAM, and therefore the low-leakage DRAM devices by integrating double wall three-dimensional (DW3D) capacitors can be implemented.
Cheng and Sharma do not explicitly disclose:
wherein the first die, the second die, and the third die are aligned in a vertical direction.
However, Liu teaches:
wherein the first die, the second die, and the third die are aligned in a vertical direction ( Liu, FIG. 1, 102, 104, 106 ; FIG. 7A, 704, 706, 702; [0067], Second semiconductor structure 704 of 3D memory device 700 can include an array of DRAM cells 714; [0074] Third semiconductor structure 706 of 3D memory device 700 can also include array of SRAM cells 734 above and in contact with semiconductor layer 766. In some embodiments, a peripheral circuit is also formed above and in contact with semiconductor layer 766, i.e., in the same plane as array of SRAM cells 734; [0080], As shown in FIG. 7A, first semiconductor structure 702 of 3D memory device 700 includes a NAND flash memory device; [0054], By vertically integrating first, second, and third semiconductor structures 102, 104, and 106 having heterogeneous memories, the memory chip size can be reduced, and the memory cell density can be increased ).
Cheng and Sharma and Liu are all considered to be analogous to the claimed invention because they are forming three-dimensional (3D) memory and DRAM. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Cheng ( Second semiconductor structure 704 of semiconductor device 700 can further include an array of DRAM cells 756 ) and Sharma ( 4F2 DRAM cell that is implemented with vertical thin film transistors (VTFTs) ), to incorporate the teachings of Liu ( [0054], By vertically integrating first, second, and third semiconductor structures 102, 104, and 106 having heterogeneous memories, the memory chip size can be reduced, and the memory cell density can be increased ), to implement that the first die, the second die, and the third die are aligned in a vertical direction. Doing so would reduce memory chip size, and therefore memory cell density can be increased.
Regarding Claim 18 ( Currently Amended ), Cheng and Sharma and Liu teach the method as claimed in claim 16, on which this claim is dependent, Cheng further teaches:
wherein the second die ( Cheng, FIG. 7A, 704; [0098], second semiconductor structure 704, DRAM ) further comprises:
a complementary metal-oxide semiconductor (CMOS) circuit ( Cheng, FIG. 7A, 758, 764, 754, 772; [0098], Another node of each DRAM selection transistor 758 is electrically connected to a bit line 764 of DRAM; [0101], In some embodiments, second semiconductor structure 704 further includes one or more contacts 772 extending through semiconductor layer 762 to electrically connect pad-out interconnect layer 768 and interconnect layers 754 and 724. As a result, processor 716 and array of SRAM cells 718 (and peripheral circuit 720 if any) can be electrically connected to array of DRAM cells 756 through interconnect layers 754 and 724 as well as bonding contacts 752 and 728 ).
Regarding Claim 19 ( Previously Presented ), Cheng and Sharma and Liu teach the method as claimed in claim 18, on which this claim is dependent, Cheng further teaches: wherein the second die further comprises:
a complementary metal-oxide semiconductor (CMOS) circuit ( Cheng, FIG. 7A, 758, 764, 754, 772; [0098], [0101] ), the method further comprising:
fabricating the plurality of DRAM cells ( Cheng, FIG. 7A, 756; [0098], Second semiconductor structure 704 of semiconductor device 700 can further include an array of DRAM cells 756 above interconnect layer 754 and bonding layer 750 ) using a first process; and
fabricating the CMOS circuit ( Cheng, FIG. 7A, 758, 764; [0098], Another node of each DRAM selection transistor 758 is electrically connected to a bit line 764 of DRAM ) using a second process, the first and second processes being a same process or similar processes ( Cheng’s FIG. 7A disclosed the integration of both DRAM cells 756 and CMOS circuits ( DRAM selection transistor 758, bit line 764 of DRAM ) on the same semiconductor substrate ).
Regarding Claim 20 ( Previously Presented ), Cheng and Sharma and Liu teach the method as claimed in claim 18, on which this claim is dependent, Cheng and Sharma further teach:
before bonding the first die with the second die ( Cheng, FIG. 7A, 704; [0098] ), thinning a substrate ( Cheng, [0099], Semiconductor layer 762 can be a thinned substrate on which DRAM selection transistors 758 are formed ) of the second die to expose a dielectric region ( Cheng, [0098], For example, capacitor 760 may be a planar capacitor, a stack capacitor, a multi-fins capacitor, a cylinder capacitor, a trench capacitor, or a substrate-plate capacitor ) and cause the dielectric region to penetrate through the substrate along the vertical direction, wherein the vertical gate structure ( Sharma, [0001], 4F2 DRAM cell that is implemented with vertical thin film transistors (VTFTs) ) is formed in the substrate (Cheng, [0098], In some embodiments, DRAM selection transistors 758 are formed “on” a semiconductor layer 762, in which the entirety or part of DRAM selection transistors 758 are formed in semiconductor layer 762 (e.g., below the top surface of semiconductor layer 762) and/or directly on semiconductor layer 762).
Claims 3, 8 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng, in view of Sharma and Liu, further in view of Liu2 (Pub. No. 20210210142 A1), hereinafter Liu2.
Regarding Claim 3 ( Currently Amended ), Cheng and Sharma and Liu teach the 3D memory device as claimed in claim 2 on which this claim is dependent,
Cheng and Sharma and Liu fail to disclose:
wherein the second die ( Cheng, FIG. 7A, 704; [0078] ) is bonded with and between the first and third dies along the vertical direction.
However, Liu2 teaches:
wherein the first ( Liu2, FIG. 7B, the die having 604 ) and second ( Liu2, FIG. 7B, the die having 508 ) dies are stacked ( Liu2, [0070], memory stack 604 can include interleaved conductor layers 606 and dielectric layers 608; [0067], a plurality of capacitors 508 are formed above and in contact with DRAM selection transistors 506 ).
Cheng and Sharma and Liu and Liu2 are all considered to be analogous to the claimed invention because they are forming 3D memory structure. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Cheng ( second die and third dies are stacked ), to incorporate the teachings of Liu2 ( first and second dies are stacked ), to implement that wherein the second die is bonded with and between the first and third dies along the vertical direction. Doing so would integrate more transistors into unit area, and therefore the chip size can be further improved.
Regarding Claim 8 ( Currently Amended ), Cheng and Sharma and Liu and Liu2 teach the 3D memory device as claimed in claim 3 on which this claim is dependent, Cheng further teaches: wherein
a conductive via ( Cheng, FIG. 7A, via under 772; [0101], one or more contacts 772 extending through semiconductor layer 762 to electrically connect pad-out interconnect layer 768 and interconnect layers 754 and 724 ) passes through the second die ( Cheng, FIG. 7A, 704; [0078] ) along the vertical direction, and
one end ( Cheng, FIG. 7A, 770; [0100], contact pads 770 ) of the conductive via connects ( Cheng, FIG. 7A, via under 772 ) with a conductor layer in the first die ( Cheng, [0101], Also, array of 3D NAND memory strings 736 in first semiconductor structure 702 can be electrically connected to array of DRAM cells 756 in second semiconductor structure 704 through interconnect layers 734 ) and another end ( Cheng, FIG. 7A, 750, 752; [0095], Bonding layer 750 can include a plurality of bonding contacts 752 ) of the conductive via connects ( Cheng, FIG. 7A, via under 772 ) with a conductor layer in the third die (Cheng, FIG. 7A, 706; [0078], third semiconductor structure 706).
Claims 7 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng, in view of Sharma and Liu, further in view of Ge (Pub. No. 20130033953 A1), hereinafter Ge.
Regarding Claim 7 ( Original ), Cheng and Sharma and Liu teach the 3D memory device as claimed in claim 6 on which this claim is dependent, Cheng further teaches:
wherein the circuit ( Cheng, FIG. 7A, 758, 764; [0098] ) includes a complementary metal-oxide semiconductor (CMOS) circuit ( Cheng, [0098], Another node of each DRAM selection transistor 758 is electrically connected to a bit line 764 of DRAM ) that has a low supply voltage below 30 volts.
Cheng and Sharma and Liu fail to disclose:
a low supply voltage below 30 volts.
However, Ge teaches:
a low supply voltage below 30 volts ( Ge, [0004], Specifically, the operation voltage of double data rate (DDR) DRAM is 2.5 volts (V), the operation voltage of DDR2 DRAM is 1.8V, and the operation voltage of DDR3 DRAM is 1.5V ).
Cheng and Sharma and Liu and Ge are all considered to be analogous to the claimed invention because they are forming DRAM. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Cheng ( DRAM selection transistor 758 is electrically connected to a bit line 764 of DRAM ), to incorporate the teachings of Ge ( operation voltage of double data rate (DDR) DRAM is 1.5 to 2.5 volts ), to implement that the circuit for DRAM has a low supply voltage below 30 volts. Doing so would provide specific range of supply voltage for DRAM, and therefore an example of DRAM can be implemented.
Claims 10 – 15 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng, in view of Sharma, in view of Liu2.
Regarding Independent Claim 10 ( Currently Amended ), Cheng teaches a memory device, comprising:
a first die of a memory structure ( Cheng, FIG. 7A, 702; [0078], first semiconductor structure 702; [0088], In some embodiments, first semiconductor structure 702 of semiconductor device 700 includes a NAND flash memory device in which memory cells are provided in the form of an array of 3D NAND memory strings 736 above interconnect layer 734 and bonding layer 730 ) comprising a plurality of memory cells;
a second die ( Cheng, FIG. 7A, 704; [0078], second semiconductor structure 704; [0098], Second semiconductor structure 704 of semiconductor device 700 can further include an array of DRAM cells 756 above interconnect layer 754 and bonding layer 750 ) comprising a plurality of dynamic random-access memory (DRAM) cells; and
a third die ( Cheng, FIG. 7A, 706; [0078], third semiconductor structure 706; 714, 716, 718, 720; [0081], SRAM cells 718 on substrate 712 and outside of processor 716. In some embodiments, device layer 714 further includes a peripheral circuit 720 on substrate 712 and outside of processor 716 ) of a periphery structure comprising a periphery circuit, wherein the first die, the second die, and the third die ( Cheng, FIG. 7A, 702 ( first die ) and 706 ( third die ) are stacked and aligned, 704 ( second die ) and 706 (third die ) are stacked and aligned ) are aligned along the vertical direction.
Cheng fails to disclose: wherein
a DRAM cell of the plurality of DRAM cells includes a transistor, the transistor including a vertical gate structure, a source region, and a drain region, and the source region and the drain region are stacked along a vertical direction.
However, Sharma teaches: wherein
a DRAM cell of the plurality of DRAM cells includes a transistor, the transistor including a vertical gate structure ( Sharma, [0001], 4F2 DRAM cell that is implemented with vertical thin film transistors (VTFTs) ), a source region, and a drain region, and the source region and the drain region are stacked along a vertical direction ( Sharma, Abstract, a source region may be below the gate electrode and a drain region may be above the gate electrode … a channel region may be between the source region and the drain region; FIG. 3A, [0042], a source region 316 formed below a lowermost surface 363 of the gate electrode 312 and a drain region 318 formed above the uppermost surface 362 of the gate electrode 312. In an embodiment, a channel region 315 may be formed between the source region 316 and the drain region 318. For example, the channel region 315 may be formed along the sidewall surfaces 361 of the gate electrode 312 ).
Cheng and Sharma are both considered to be analogous to the claimed invention because they are forming DRAM. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Cheng ( Second semiconductor structure 704 of semiconductor device 700 can further include an array of DRAM cells 756 ), to incorporate the teachings of Sharma ( 4F2 DRAM cell that is implemented with vertical thin film transistors (VTFTs) ), to implement that wherein a DRAM cell of the plurality of DRAM cells includes a transistor, the transistor including a vertical gate structure, a source region, and a drain region, and the source region and the drain region are stacked along a vertical direction. Doing so would provide specific vertical channel transistors with low leakage for DRAM, and therefore the low-leakage DRAM devices by integrating double wall three-dimensional (DW3D) capacitors can be implemented.
Cheng and Sharma fail to disclose:
wherein the first and second dies are stacked.
However, Liu2 teaches:
wherein the first ( Liu2, FIG. 7B, the die having 604 ) and second ( Liu2, FIG. 7B, the die having 508 ) dies are stacked ( Liu2, [0070], memory stack 604 can include interleaved conductor layers 606 and dielectric layers 608; [0067], a plurality of capacitors 508 are formed above and in contact with DRAM selection transistors 506 ).
Cheng and Sharma and Liu2 are all considered to be analogous to the claimed invention because they are forming 3D memory structure. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Cheng ( second die and third die are stacked and aligned ), to incorporate the teachings of Liu2 ( first die and second die are stacked and aligned ), to implement that the first die, the second die, and the third die are stacked and aligned along the vertical direction. Doing so would integrate more transistors into unit area, and therefore the chip size can be further improved.
Regarding Claim 11 ( Original ), Cheng and Sharma and Liu2 teach the memory device as claimed in claim 10 on which this claim is dependent, Cheng further teaches:
wherein the memory structure ( Cheng, FIG. 7A, 702; [0078] ) further comprises a conductor/insulator stack ( Cheng, FIG. 7A, 738; [0088], The stacked and interleaved conductor layers and dielectric layer are also referred to herein as a memory stack 738 ) including a conductive layer and a dielectric layer alternatingly stacked, and the plurality of memory cells ( Cheng, FIG. 7A, 736; [0088], Each 3D NAND memory string 736 extends vertically through a plurality of pairs each including a conductor layer and a dielectric layer ) are arranged in the conductor/insulator stack.
Regarding Claim 12 ( Original ), Cheng and Sharma and Liu2 teach the memory device as claimed in claim 10 on which this claim is dependent, Cheng further teaches:
wherein the first, second, and third dies are bonded together ( Cheng, FIG. 7A, 726, 730, 750; [0084], bonding layer 726; [0085], bonding layer 730; [0095], bonding layer 750 ).
Regarding Claim 13 ( Previously Presented ), Cheng and Sharma and Liu2 teach the memory device as claimed in claim 10 on which this claim is dependent, Cheng and Liu further teach:
wherein the second die ( Liu, FIG. 7B, the die having 508; Cheng, FIG. 7A, 704 ) is bonded with and between the first die ( Liu, FIG. 7B, the die having 604 ) and the third die ( Cheng, FIG. 7A, 706 ) ( Liu, FIG. 7B, “the die having 604” is above “the die having 508”; [0070], memory stack 604 can include interleaved conductor layers 606 and dielectric layers 608; [0067], a plurality of capacitors 508 are formed above and in contact with DRAM selection transistors 506 ) ( Cheng, FIG. 7A, 704 is above 706 ),
a conductive via ( Cheng, FIG. 7A, via under 772; [0101], one or more contacts 772 extending through semiconductor layer 762 to electrically connect pad-out interconnect layer 768 and interconnect layers 754 and 724 ) passes through the second die ( Cheng, FIG. 7A, 704; [0078] ) along the vertical direction, and
one end ( Cheng, FIG. 7A, 770; [0100], contact pads 770 ) of the conductive via connects ( Cheng, FIG. 7A, via under 772 ) with a conductor layer in the first die ( Cheng, [0101], Also, array of 3D NAND memory strings 736 in first semiconductor structure 702 can be electrically connected to array of DRAM cells 756 in second semiconductor structure 704 through interconnect layers 734 ) and another end ( Cheng, FIG. 7A, 750, 752; [0095], Bonding layer 750 can include a plurality of bonding contacts 752 ) of the conductive via connects ( Cheng, FIG. 7A, via under 772 ) with a conductor layer in the third die ( Cheng, FIG. 7A, 706; [0078], third semiconductor structure 706 ).
Regarding Claim 14 ( Previously Presented ), Cheng and Sharma and Liu2 teach the memory device as claimed in claim 10 on which this claim is dependent, Cheng and Sharma further teach:
wherein the plurality of DRAM cells form a pattern ( Cheng, FIG. 7A, 756; [0098], array of DRAM cells 756 ) in a plane ( Cheng, FIG. 7A, 762; [0098], semiconductor layer 762 ), the vertical gate structure ( Cheng, FIG. 7A, 758; [0098], DRAM selection transistor 758; Sharma, [0001], 4F2 DRAM cell that is implemented with vertical thin film transistors (VTFTs) ) extending in a direction perpendicular to the plane ( Cheng, FIG. 7A, 762; [0098] ).
Regarding Claim 15 ( Previously Presented ), Cheng and Sharma and Liu2 teach the memory device as claimed in claim 10 on which this claim is dependent, Cheng further teaches:
wherein the DRAM cell further includes a capacitor ( Cheng, FIG. 7A, 760; [0098], Each capacitor 760 includes two electrodes, one of which is electrically connected to one node of respective DRAM selection transistor 758 ) stacked on the vertical gate structure with an electrode ( Cheng, FIG. 7A, 766; [0098], Another electrode of each capacitor 760 can be electrically connected to a common plate 766, e.g., a common ground ) extending in the vertical direction ( Cheng, FIG. 7A, 760; [0098], For example, capacitor 760 may be a planar capacitor, a stack capacitor, a multi-fins capacitor, a cylinder capacitor, a trench capacitor, or a substrate-plate capacitor ).
Response to Arguments
Applicant's remarks filed 02/26/2026 have been fully considered but they are not persuasive.
Applicant’s remarks regarding ( Currently Amended ) Claim 1: on page 9, line 8 from bottom, cited “ Cheng and Sharma do not disclose, teach, or suggest the claimed invention, either alone or in combination. For example, Cheng aligns semiconductor structures 702 and 704 in a horizontal direction, instead a vertical direction (Cheng, FIG. 7A; [0078]). Sharma does not disclose stack dies together, let alone aligning three dies along a vertical direction. ”.
Examiner’s response: please refer to claim 1 in Claim Rejections - 35 USC § 103 of this office action, cited “
However, Liu teaches:
the first die, the second die, and the third die are aligned in a vertical direction ( Liu, FIG. 1, 102, 104, 106 ; FIG. 7A, 704, 706, 702; [0067], Second semiconductor structure 704 of 3D memory device 700 can include an array of DRAM cells 714; [0074] Third semiconductor structure 706 of 3D memory device 700 can also include array of SRAM cells 734 above and in contact with semiconductor layer 766. In some embodiments, a peripheral circuit is also formed above and in contact with semiconductor layer 766, i.e., in the same plane as array of SRAM cells 734; [0080], As shown in FIG. 7A, first semiconductor structure 702 of 3D memory device 700 includes a NAND flash memory device; [0054], By vertically integrating first, second, and third semiconductor structures 102, 104, and 106 having heterogeneous memories, the memory chip size can be reduced, and the memory cell density can be increased ).
Cheng and Sharma and Liu are all considered to be analogous to the claimed invention because they are forming three-dimensional (3D) memory and DRAM. Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have modified Cheng ( Second semiconductor structure 704 of semiconductor device 700 can further include an array of DRAM cells 756 ) and Sharma ( 4F2 DRAM cell that is implemented with vertical thin film transistors (VTFTs) ), to incorporate the teachings of Liu ( [0054], By vertically integrating first, second, and third semiconductor structures 102, 104, and 106 having heterogeneous memories, the memory chip size can be reduced, and the memory cell density can be increased ), to implement that the first die, the second die, and the third die are aligned in a vertical direction. Doing so would reduce memory chip size, and therefore memory cell density can be increased. ”.
Applicant’s remarks regarding Claims 3 and 8: on page 10, line 3, cited “ Liu ( ps. Liu in the last Final Rejection office action is Liu2 in this RCE Non-Final Rejection office action ) fails to disclose aligning three dies (including a die of DRAM cells) along a vertical direction, resulting in lower DRAM capacity. ”.
Examiner’s response: please refer to claims 3 and 8 in this office action, cited “ Claims 3, 8 are rejected under 35 U.S.C. 103 as being unpatentable over Cheng, in view of Sharma and Liu, further in view of Liu2 (Pub. No. 20210210142 A1), hereinafter Liu2. ”. The limitation “ aligning three dies (including a die of DRAM cells) along a vertical direction ” is mapped by Liu, as shown claim 1 in this office action. For claims 3 and 8, Liu2 is used to map “ first and second dies are stacked ”.
Applicant’s remarks regarding Claim 7: on page 10, line 8, cited “ Ge teaches a voltage adjustment circuit. Ge does not disclose stacking dies together, let alone aligning three dies along a vertical direction. ”.
Examiner’s response: please refer to claim 7 in this office action, cited “ Claims 7 is rejected under 35 U.S.C. 103 as being unpatentable over Cheng, in view of Sharma and Liu, further in view of Ge (Pub. No. 20130033953 A1), hereinafter Ge. ”. The limitation “ aligning three dies along a vertical direction ” is mapped by Liu, as shown claim 1 in this office action. For claim 7, Ge is used to map “ a low supply voltage below 30 volts ”.
Conclusion
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/DA-WEI LEE/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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