DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because the equations present (p. 17 [0081]; p. 29 [0147-0148]) raise legibility issues for reproduction purposes (see C.F.R. 1.52(a)(1)(iv)).
Appropriate correction is required.
Claim Objections
Claims 6-7 are objected to because the preambles refer to “the 3D IMC device of claim 1”, however there is no previous instance of “a 3D IMC device”. Examiner suggests amending claims 6-7 to recite “the apparatus of claim 1” as in other dependent claims to claim 1 for better consistency and clarity of the claims.
Claim 20 is objected to because the acronym SRAM is used to mean “static read-only access memory” when in claim 9 the acronym SRAM is used to mean “static random access memory”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11, 17-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 recites the limitation "plural with multiple vias" in line 2. This limitation renders the claim indefinite as it is unclear what is meant by ‘plural with multiple vias.’ The metes and bounds of the claim are indefinite as it unclear if the metal layer is plural with multiple vias, if the logic layer is plural with multiple vias, or other.
Claim 17 recites the limitation "the 3D IMC devices" in line 2. There is insufficient antecedent basis for this limitation in the claim. Claims 18-19 inherit this deficiency by reasons of dependence on claim 17 and are similarly rejected.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4, 7, 11-13, 16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 20230022115 A1 Lee et al. (hereinafter “Lee”).
Regarding claim 1, Lee discloses an apparatus comprising:
a memory layer (Fig. 12 “1210-1220” [0037]) comprising a plurality of front-end-of-line (FEOL) memory cells (Fig. 12 “metal gate / drain / source” [0037] transistors that form amplifiers, drivers, and memory cell); and
a logic layer (Fig. 12 “1240-1250” [0037]) comprising plural arithmetic logic gates comprising a plurality of backend-of-line (BEOL) transistors (Fig. 12 “1242” [0037]; “120” in Fig. 1 [0024], [0028]), the plurality of BEOL transistors being vertically stacked on respective upper ends of the plurality of memory cells (arrangement illustrated in Fig. 12 [0037], with reference to three axes of Fig. 1 “120” connection to “110” [0026]), wherein each of multiple transistors of the plurality of BEOL transistors operates as a multiplier (Fig. 4 “420” [0028], [0032] multiply-accumulate) and is configured to provide an operation result ([0032] products) with respect to first values stored in corresponding memory cells of the plurality of memory cells ([0032] stored weights from Fig. 1 “110, 112” [0026]).
Regarding claim 2, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Lee discloses wherein:
the multiple transistors (Fig. 12 “1242” [0037]; “120” in Fig. 1 [0024]) are configured to share an input data line connected in a row direction in the logic layer through respective gate terminals of the multiple transistors (Fig. 4 “WL(r,l)” [0032]), and
wherein the multiplier operation results are multiplier results ([0032] products) between the first values ([0032] stored weights) and a second value applied through the input data line ([0032] input signals), and are output ([0032] products) for each column of a memory array (Fig. 12 “1210-1220” memory layer & “1240-1250” logic layer [0037]) comprising multiple memory cells of the plurality of memory cells ([0032] stored weights from Fig. 1 “110, 112” [0026]).
Regarding claim 3, the teachings addressed in the claim 2 analysis and rejection are incorporated, and Lee discloses wherein:
a total number of the multiple transistors (Fig. 12 “1242” [0037]; “120” in Fig. 1 [0024]) is equal ([0034]) to a total number of the plurality of memory cells (Fig. 12 “metal gate / drain / source” [0037] transistors that form amplifiers, drivers, and memory cell), and
wherein a total number of the multiple memory cells ([0032] stored weights from Fig. 1 “110, 112” [0026]) is equal ([0034]) to a total number of the plurality of memory cells (Fig. 12 “metal gate / drain / source” [0037] transistors that form amplifiers, drivers, and memory cell).
Regarding claim 4, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Lee discloses wherein:
the plural arithmetic logic gates (Fig. 12 “1242” [0037]; “120” in Fig. 1 [0024], [0028]) are vertically stacked to respectively correspond (arrangement illustrated in Fig. 12 [0037], with reference to three axes of Fig. 1 “120” connection to “110” [0026]) to the plurality of memory cells (Fig. 12 “metal gate / drain / source” [0037] transistors that form amplifiers, drivers, and memory cell).
Regarding claim 7, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Lee discloses wherein:
the plurality of BEOL transistors (Fig. 12 “1242” [0037]; “120” in Fig. 1 [0024]) comprise any one or any combination of two or more of a thin film transistor (TFT), a ferroelectric field-effect transistor (FeFET) ([0028]), a two-dimensional (2D) field effect transistor (FET), and a polycrystalline silicon (poly-Si) channel FET (any one being ferroelectric).
Regarding claim 11, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Lee discloses wherein:
the logic layer (Fig. 12 “1240-1250” [0037]) comprises a metal layer (Fig. 12 “1240” [0037] metal) and plural with multiple vias of the plurality of vias being disposed to interconnect (Fig. 12 “V1, V2, …, V(n-1)” [0037] interconnected by pillars (vias)) the multiple transistors (Fig. 12 “1242” [0037]; “120” in Fig. 1 [0024]) to the first values stored in the corresponding memory cells ([0032] stored weights from Fig. 1 “110, 112” [0026]).
Regarding claim 12, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Lee discloses further comprising
a second memory layer (Fig. 4 layer above base layer 0 [0028]),
wherein the second memory layer is vertically stacked on an upper end (Fig. 4 layer above base layer 0 in the z direction [0028]) of the logic layer (Fig. 12 “1240-1250” [0037]) connected to a respective gate terminal of the plurality of transistors (Fig. 4 “430” G in above layer [0028]), and
wherein the second memory layer is vertically stacked by a back-end-of-line (BEOL) process ([0037-0038]), and 3-D stacked by one of a through silicon via (TSV) method ([0037] pillars (via) on Si) or a monolithic method (TSV out of list of alternatives).
Regarding claim 13, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Lee discloses further comprising
a second memory layer (Fig. 4 layer above base layer 0 [0028]),
wherein the second memory layer is vertically stacked on an upper end (Fig. 4 layer above base layer 0 in the z direction [0028]) of the logic layer (Fig. 12 “1240-1250” [0037]) connected to a respective gate terminal of the plurality of transistors (Fig. 4 “430” G in above layer [0028]),
wherein the second memory layer includes a plurality of second layer memory cells (Fig. 4 “430” in layer above base layer 0 [0028]), wherein multiple second layer memory cells of the plurality of second layer cells respectively store second values ([0032] stored state corresponds to a binary 1 and the input signals), and
wherein the respective multiplier operations of the multiple transistors (Fig. 4 “420” [0028], [0032] multiply-accumulate) are performed with respect to the first values ([0032] stored weights) and the second values ([0032] input signals) input to the multiple transistors in the vertical direction through respective vias formed in the logic layer (Fig. 12 “V1, V2, …, V(n-1)” [0037] interconnected by pillars (vias)).
Regarding claim 16, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Lee discloses wherein
the apparatus is an electronic device (Fig. 1 “100” [0024]), and is a mobile device, a mobile computing device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer ([0020] compute-in-memory of computers), a wearable device, a laptop computer, a server, a music player, a video player, an entertainment unit, a navigation device, a communication device, an Internet of Things (IoT) device, a global positioning system (GPS) device, a television, a tuner, an automobile, an automotive part, an avionics system, a drone, a multi-copter, an electric vertical takeoff and landing ( e VTOL) aircraft, or a medical device (a computer out of the list of alternatives).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-10, 17-18, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of US 20220027723 A1 Kolter et al. (hereinafter “Kolter”).
Regarding claim 8, the teachings addressed in the claim 1 analysis and rejection are incorporated, and Lee discloses wherein
the logic layer (Fig. 12 “1240-1250” [0037]) includes a plurality of logic layer memory cells (Fig. 4 “430” [0028]),
wherein a unit cell (Fig. 4 columns or rows of “430” arranged in layers [0028]) represents a collection of one memory cell of the plurality of logic layer memory cells ([0024]), and one arithmetic logic gate of the plurality of arithmetic logic gates, corresponding to the one memory cell (Fig. 12 “1242” [0037]; “120” in Fig. 1 [0024]), and
wherein multiple unit cells, of the plurality of unit cells represent a memory array (Fig. 4 “420” [0029]) configured to perform a matrix operation sharing a data line of the corresponding memory cells (Fig. 4 “WL(r,l)” [0032]).
Although Lee discloses the cells, they appear to be silent to explicitly disclosing using the memory array is configured to perform a matrix operation.
Kolter discloses a matrix operation ([0167]).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Pareek with Kolter’s matrix operation feature because they are in the claimed invention’s same field of endeavor in-memory compute multiply-accumulate architecture ([0160]). Modifying with Kolter’s features would have yielded predictable results of performing matrix computations of inputs and weights as doing so would provide the modified apparatus the capability of processing neural network data ([0165], [0167]). It would have been obvious that one of ordinary skill in the art would have been able to implement the matrix operation feature as a person of ordinary skill in the art would look to Kolter’s features before the effective filing date to utilize matrices for neural network processing purposes.
Regarding claim 9, the teachings addressed in the claim 8 analysis and rejection are incorporated, and Lee discloses further comprising
one or more static random access memory (SRAM) crossbar arrays, wherein the unit cell (Fig. 4 columns or rows of “430” arranged in layers [0028]) corresponds to one bit cell of one of the SRAM crossbar arrays.
Lee appears to be silent to disclosing one or more static random access memory (SRAM) crossbar arrays, and corresponds to one bit cell of one of the SRAM crossbar arrays.
Kolter discloses one or more static random access memory (SRAM) crossbar arrays (Fig. 33a [0157]), and corresponds to one bit cell of one of the SRAM crossbar arrays (Fig. 33a “SRAM” [0157], Fig. 33b [0157]).
In addition to the motivation to combine provided with respect to claim 8, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify Pareek with Kolter’s SRAM crossbar feature because modifying with Kolter’s features would have yielded predictable results of performing matrix computations of inputs and weights using a combination of ROM and RAM as doing so would provide the modified apparatus the capability of processing neural network data ([0165], [0167]). It would have been obvious that one of ordinary skill in the art would have been able to implement the matrix operation feature using a combination of ROM and RAM as a person of ordinary skill in the art would look to Kolter’s features before the effective filing date to take advantage of both technologies ([0100], [0154]) whereas in previous SRAM-only technologies suffer from leaks that consume significant power ([0101]).
Regarding claim 10, the teachings addressed in the claim 8 analysis and rejection are incorporated, and Lee discloses wherein
the memory layer (Fig. 12 “1210-1220” [0037]) comprises:
a plurality of word lines ([0026] WLs connected via WL driver [0032, 0035]);
a plurality of bit lines (BLs) ([0027] BLs comprised via intersection connection) intersecting ([0021]) with the plurality of word lines ([0026]); and
the corresponding memory cells (Fig. 12 “metal gate / drain / source” [0037] transistors that form amplifiers, drivers, and memory cell) being disposed at intersecting points between the plurality of word lines and the plurality of bit lines (Fig. 12 “metal gate / drain / source” [0037] transistors that form amplifiers, drivers, and memory cell).
Claim 17 is directed to an electronic device which recites similar limitation to claim 1. The claim 1 analysis similarly applies and claim 17 is similarly rejected. Claim 17 additionally recites the following: an array circuit comprising a plurality of the 3D IMC devices; and a controller configured to implement a neural network through a provision of input second values to each of the plurality of 3D IMC devices and control of the plurality of 3D IMC devices.
Lee discloses an array circuit (Fig. 7 collection of “720” [0034]) comprising a plurality of the 3D IMC devices (Fig. 1 “720” [0034]); and a controller (Fig. 1 “116” [0026]) configured to implement a neural network through a provision of input second values to each of the plurality of 3D IMC devices and control ([0026], [0035]) of the plurality of 3D IMC devices (Fig. 1 “720” [0034]).
However, Lee appears to be silent to disclosing a neural network through a provision of input second values.
Kolter discloses a neural network ([0165] neural network) through a provision of input second values ([0166] weights).
In addition to the motivation to combine provided with respect to claim 8, it would have been obvious to one of ordinary skill in the art before the effective filing date to modify Pareek with Kolter’s neural network feature because modifying with Kolter’s features would have yielded predictable results of performing matrix computations of inputs and weights of a neural network using a combination of ROM and RAM as doing so would provide the modified apparatus the capability of processing neural network data ([0165-0167]). It would have been obvious that one of ordinary skill in the art would have been able to implement matrix operations of the neural network feature using a combination of ROM and RAM as a person of ordinary skill in the art would look to Kolter’s features before the effective filing date to take advantage of both technologies ([0100], [0154]) whereas in previous SRAM-only technologies suffer from leaks that consume significant power ([0101]).
Claim 18 is directed to an electronic device that recites similar limitations to claims 12-13. The claims 12-13 analysis similarly applies and claim 18 is similarly rejected.
Claim 20 is directed to a method that would be practiced by the apparatus of claim 1. The claim 1 analysis similarly applies. Claim 20 additionally recites the following: storing first values in static read-only access memory (SRAM) cells of a front-end-of-line
(FEOL) memory array; and outputting a result of a summation from the summing.
Lee discloses storing first values ([0032] stored weights) in a front-end-of-line (FEOL) memory array (Fig. 12 “metal gate / drain / source” [0037] transistors that form amplifiers, drivers, and memory cell); outputting a result of a summation from the summing ([0032] output voltage).
However, Lee appears to be silent to disclosing static read-only access memory (SRAM) cells.
Kolter discloses static read-only access memory (SRAM) cells (Fig. 33A ROM and RAM [0157] SRAM).
The motivation to combine provided with respect to claim 8 similarly applies.
Allowable Subject Matter
Claims 5-6, 14-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 19 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
A statement of reasons for the indication of allowable subject matter will be given after amendments are made to overcome the objections and 35 USC 112(b) rejections.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARKUS A VILLANUEVA whose telephone number is (703)756-1603. The examiner can normally be reached M - F 8:30 am - 5:30 pm.
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/MARKUS ANTHONY VILLANUEVA/Examiner, Art Unit 2151
/James Trujillo/Supervisory Patent Examiner, Art Unit 2151
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