DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e).
Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Applicant cannot rely upon the certified copy of the foreign priority application to overcome this rejection because a translation of said application has not been made of record in accordance with 37 CFR 1.55. When an English language translation of a non-English language foreign application is required, the translation must be that of the certified copy (of the foreign application as filed) submitted together with a statement that the translation of the certified copy is accurate. See MPEP §§ 215 and 216.
Response to Amendment
This office Action is in response to Applicant’s amendment filed on 01/23/2026. Claims 1, 3, 12, 13 and 19 have been amended. Claim 23 has been added. Claim 2, 8, and 14 have been canceled. Currently claims 1, 3-7, 9-13 and 15-20 are pending.
Applicant’s amendments to claim 19 successfully overcome the 35 U.S.C. 112(b) rejections.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 3-7, 9-13 and 15-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed
invention is not identically disclosed as set forth in section 102, if the differences between the
claimed invention and the prior art are such that the claimed invention as a whole would have
been obvious before the effective filing date of the claimed invention to a person having
ordinary skill in the art to which the claimed invention pertains. Patentability shall not be
negated by the manner in which the invention was made.
Claims 1, 3-4, 9-13, 16 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw, Jhon Jhy () “Liaw et al.” in view of KIM, Bo Soon (US 20170200738 A1) “KIM et al.” further in view of Lee, Sanghoon (US 20200381555 A1) “Lee et al.”.
With Regard to Independent claim 1, Liaw et al. Figs. 1B and 12-15 discloses a semiconductor device (“6T SP SRAM cell 104” ¶ [0024]) comprising:
a substrate (“substrate 202” ¶ [0051]);
a static random-access memory (SRAM) cell (“SRAM macro 102” ¶ [0050]) comprising a pass-gate transistor PG-1 (“two NMOS transistors as pass-gate (or access) transistors PG-1 and PG-2.” ¶ [0024]), a pull- down transistor PD-1 (“two NMOS transistors as pull-down transistors PD-1 and PD-2” ¶ [0024]), and a pull-up transistor PU-1 (“two PMOS transistors as pull-up transistors PU-1 and PU-2) on the substrate 202,
wherein each of the pass-gate transistor PG-1, the pull-down transistor PD-1 , and the pull-up transistor PU-1 comprises:
an active fin 205 (“the active regions 205 (205A, 205B, 205C, and 205D) in the HD SRAM macro 102 (or in the HD SRAM cell 104) include horizontally oriented vertically stacked transistor channels” ¶ [0050]) extending in a first direction and protruding upwardly of a device isolation layer (“an isolation structure (or isolation features) 230 over the substrate 202 and isolating the adjacent active regions 205.” ¶ [0031]);
channel layers (“the active regions 205 (205A, 205B, 205C, and 205D) in the HD SRAM macro 102 (or in the HD SRAM cell 104) include horizontally oriented vertically stacked transistor channels 215 (215A, 215B, 215C, 215D, 215E, and 215F) in the respective channel regions,” ¶ [0050]) disposed on the active fin 205 and spaced apart from each other (Fig. 12-14 shows the channel layers (215A, 215B, 215C, 215D, 215E, and 215F) are spaced apart from each other);
a gate electrode (“gate electrodes 350 of the n-type and p-type FinFET (PG-1, PG-2, PD-1, PD-2, PU-1, PU-2)” ¶ [0056]) intersecting the active fin 205, extending in a second direction, and surrounding the channel layers (“a gate electrode 350) wraps around each of the channel layer 215A (FIG. 13), forming an NMOS gate-all-round (GAA) transistor PG-1. The other transistors PU-1, PU-2, PD-1, PD-2, and PG-2 are similarly configured as GAA transistors.” ¶ [0051]),
the gate electrode 350 comprising inner portions (Fig. 14 shows gate electrode 350 has inner portions between the spacers 255) disposed between the channel layers 215 and between the active fin 205 and a lowermost channel layer (the lowest layer of 215 in Fig. 14) among the channel layers 215;
a gate dielectric layer (“a gate dielectric layer 282” ¶ [0051]) disposed between the channel layers 215 and the gate electrode 350;
source/drain regions 260 (“source/drain feature 260 (including 260P for PMOSFET and 260N for NMOSFET) in the source/drain regions” ¶ [0050]) disposed on the active fin 205 on opposite sides of the gate electrode 350, and connected (“connecting a pair of source/drain features” ¶ [0051]) to the channel layers 215; and
inner spacers (“spacers 255” ¶ [0053]) disposed between the inner portions of the gate electrode 350 and the source/drain regions 260,
wherein the inner spacers 255 of the pass-gate transistor PG-1 comprise first inner spacers (255 on PG-1 in Fig. 14),
wherein the inner spacers 255 of the pull-down transistor PD-1 comprise second inner spacers (255 on PD-1 in Fig. 14),
wherein the source/drain regions 260 comprise a shared source/drain region (Fig. 14 shows the middle source/drain region 260N is shared between PG-1 and PD-1),
wherein the channel layers 215 of the pass-gate transistor PG-1 comprise first channel layers 215A (“the channels 215A and 215F (for the transistors PG-1 and PG-2 respectively)” ¶ [0050]),
wherein the channel layers 215 of the pull-down transistor PD-1 comprise second channel layers 215B (“the channels 215B and 215E (for the transistors PD-1 and PD-2 respectively)” ¶ [0050]), and
wherein the shared source/drain region 260N contacts (“each of the channel layers 215A and 215B (as well as the channel layers 215E and 215F) connects a pair of n-type source/drain features 260N, and the channel layer 215D (as well as the channel layer 215C) connects a pair of p-type source/drain features 260P.” ¶ [0032]) the first channel layers 215A and the second channel layers 215B.
However, Liaw et al. does not disclose, wherein at least portions of the first inner spacers disposed on different height levels have different thicknesses in the first direction,
wherein at least portions of the second inner spacers disposed on different height levels have different thicknesses in the first direction, and
wherein at least one of the first inner spacers and at least one of the second inner spacers are disposed at the same height level and have different thicknesses in the first direction.
wherein the inner spacers have side surfaces that are curved and are convex toward the inner portions of the gate electrode.
In the similar field of endeavor, KIM et al. Fig. 57 discloses, wherein at least portions of the first inner spacers 242 disposed on different height levels have different thicknesses in the first direction (Fig. 57 shows inner spacer 242 in different height level has different widths/thicknesses),
wherein at least portions of the second inner spacers disposed 142 on different height levels have different thicknesses in the first direction (Fig. 57 shows inner spacer 142 in different height level has different widths/thicknesses), and
wherein at least one of the first inner spacers 242 and at least one of the second inner spacers 142 are disposed at the same height level and have different thicknesses (Fig. 57 shows inner spacers 242 and 142 in same height level has different widths/thicknesses) in the first direction.
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify Liaw et al, with the variable width of the spacers depending on the heights of KIM et al. in order to provide a semiconductor device capable of enhancing device performance by variably adjusting threshold voltage of a transistor having gate-all-around structure (KIM et al. ¶ [007]).
However, KIM et al. does not disclose, wherein the inner spacers have side surfaces that are curved and are convex toward the inner portions of the gate electrode.
In the similar field of semiconductor devices, Lee et al. Figs. 5A-5B discloses wherein the inner spacers (“internal spacers IS” ¶ [0057]) have side surfaces that are curved and are convex toward (Figs. 5A-5B shows inner spacers IS have side surfaces that are curved and are convex toward GE) the inner portions of the gate electrode GE (“gate electrode GE” ¶ [0057]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify Liaw et al, with the variable width of the inner spacers of Lee et al. in order to space apart source/drain regions from the gate electrode GE with the internal spacers IS interposed therebetween. (Lee et al. 0043]).
Regarding Claim 3, Liaw et al. as modified by KIM et al. and Lee et al. discloses the limitations of claim 1 as described above. Liaw et al. Fig. 14 further discloses, wherein the shared source/drain region 260 contacts (“inner spacers 255 are disposed laterally between the source/drain features 260N (or 260P)” ¶ [0053]) the first inner spacers and the second inner spacers.
Regarding Claim 4, Liaw et al. as modified by KIM et al. and Lee et al. discloses the limitations of claim 1 as described above. Liaw et al. Fig. 14 further discloses, wherein the gate electrode (350 on PG-1) of the pass- gate transistor PG-1 comprises a first gate electrode having first inner portions (Fig. 14 shows gate electrode 350 has inner portions between the spacers 255 on PG-1),
wherein the gate electrode (350 on PD-1) of the pull-down transistor comprises a second gate electrode having second inner portions (Fig. 14 shows gate electrode 350 has inner portions between the spacers 255 on PD-1).
However, Liaw et al. does not disclose, wherein at least one of the first inner portions and at least one of the second inner portions are disposed on the same height level as each other and have different gate lengths in the first direction.
In the similar field of endeavor, KIM et al. Fig. 57 discloses,
wherein at least one of the first inner portions (inner portions of 224 between the spacers 242) and at least one of the second inner portions (inner portions of 124 between the spacers 142) are disposed on the same height level as each other and have different gate lengths (Fig. 57 shows inner portions of 224 and 124 in same height level has different gate lengths) in the first direction (horizontal direction).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify Liaw et al, with the variable width of the gate lengths depending on the heights of KIM et al. in order to provide a semiconductor device capable of enhancing device performance by variably adjusting threshold voltage of a transistor having gate-all-around structure (KIM et al. ¶ [007]).
Regarding Claim 9, Liaw et al. as modified by KIM et al. and Lee et al. discloses the limitations of claim 1 as described above. Liaw et al. Fig. 14 further discloses, wherein the gate electrode 350 further comprises an upper portion (Fig. 14 shows upper portion of 350 above the uppermost channel layer 215) on an uppermost channel layer among the channel layers 215.
Regarding Claim 10, Liaw et al. as modified by KIM et al. and Lee et al. discloses the limitations of claim 1 as described above. Liaw et al. Fig. 14 further discloses, wherein lower ends of the source/drain regions are located on a level lower than a lowest inner spacer among the inner spacers (Fig. 14 shows lower ends of the source/drain regions 260 are located on a level lower than a lowest inner spacer 255 among the inner spacers 255s).
Regarding Claim 11, Liaw et al. as modified by KIM et al. and Lee et al. discloses the limitations of claim 1 as described above. Liaw et al. Fig. 14 further discloses, wherein the gate dielectric layer 282 of the pass-gate transistor PG-1 comprises a first gate dielectric layer (Gate dielectric 282 on PG-1) having a first thickness (thickness of Gate dielectric 282 on PG-1),
wherein the gate dielectric layer 282 of the pull-down transistor PD-1 comprise a second gate dielectric layer (Gate dielectric 282 on PD-1) having a second thickness (thickness of Gate dielectric 282 on PD-1), and wherein the first thickness and the second thickness are substantially the same (Fig. 14 shows thicknesses of gate dielectric layer 282 are same on PG-1 and PD-1).
Regarding Independent Claim 12, Liaw et al. Figs. 1B and 12-14 discloses a semiconductor device (“6T SP SRAM cell 104” ¶ [0024]) comprising:
a substrate (“substrate 202” ¶ [0051]);
a static random-access memory (SRAM) cell (“SRAM macro 102” ¶ [0050]) comprising a pass-gate transistor PG-1 (“two NMOS transistors as pass-gate (or access) transistors PG-1 and PG-2.” ¶ [0024]), a pull- down transistor PD-1 (“two NMOS transistors as pull-down transistors PD-1 and PD-2” ¶ [0024]), and a pull-up transistor PU-1 (“two PMOS transistors as pull-up transistors PU-1 and PU-2) on the substrate 202,
wherein the SRAM cell comprises an active fin 205 (“the active regions 205 (205A, 205B, 205C, and 205D) in the HD SRAM macro 102 (or in the HD SRAM cell 104) include horizontally oriented vertically stacked transistor channels” ¶ [0050]) extending in a first direction,
wherein the pass-gate transistor PG-1 and the pull-down transistor PD-1 are disposed adjacent to each other on the active fin 205 in the first direction (Fig. 14 shows PG-1 and PD-1 are adjacent to each other in the horizontal direction),
wherein the pass-gate transistor PG-1 comprises first channel layers 215A (“the channels 215A and 215F (for the transistors PG-1 and PG-2 respectively)” ¶ [0050]) disposed on the active fin 205, a first gate electrode (350 on PG-1) (“gate stack 240A (including a gate dielectric layer 282 and a gate electrode 350) wraps around each of the channel layer 215A (FIG. 13), forming an NMOS gate-all-round (GAA) transistor PG-1.” ¶ [0051]) intersecting the active fin 205 and surrounding the first channel layers 215A, first source/drain regions 260N (“a pair of source/drain features 260N” ¶ [0051]) disposed on the active fin 205 on opposite sides of the first gate electrode 350,
wherein the pass-gate transistor PG-1 further comprises first inner spacers (255 on PG-1 in Fig. 14) (“spacers 255” ¶ [0053]) contacting respective lower surfaces of the first channel layers 215A, contacting the first source/drain regions 260N, and wherein the first inner spacers 255 are disposed on opposite sides of the first gate electrode 350,
wherein the pull-down transistor PD-1 comprises second channel layers 215B (“the channels 215B and 215E (for the transistors PD-1 and PD-2 respectively)” ¶ [0050]) disposed on the active fin 205, a second gate electrode (350 on PD-1) (“a gate electrode 350) wraps around each of the channel layer 215A (FIG. 13), forming an NMOS gate-all-round (GAA) transistor PG-1. The other transistors PU-1, PU-2, PD-1, PD-2, and PG-2 are similarly configured as GAA transistors.” ¶ [0051]) intersecting the active fin 205 and surrounding the second channel layers 215B, second source/drain regions 260N disposed on the active fin on opposite sides of the second gate electrode (350 on PD-1),
wherein the pull-down transistor further comprises second inner spacers (255 on PD-1 in Fig. 14) (“spacers 255” ¶ [0053]) contacting respective lower surfaces of the second channel layers 215B, contacting the second source/drain regions (260N on PD-1), and wherein the second inner spacers (255 on PD-1) are disposed on opposite sides of the second gate electrode (350 on PD-1).
wherein at least one of the first source/drain regions (260N on PG-1) of the pass-gate transistor PG-1 and at least one of the second source/drain regions (260N on PD-1) of the pull-down transistor PD-1 is a shared source/drain region (Fig. 14 shows the middle source/drain region 260N is shared between PG-1 and PD-1).
wherein the shared source/drain region 260N contacts (“each of the channel layers 215A and 215B (as well as the channel layers 215E and 215F) connects a pair of n-type source/drain features 260N, and the channel layer 215D (as well as the channel layer 215C) connects a pair of p-type source/drain features 260P.” ¶ [0032]) the first channel layers 215A and the second channel layers 215B.
However, Liaw et al. does not disclose, wherein at least one of the first inner spacers and at least one of the second inner spacers are disposed on the same height level and have different thicknesses in the first direction.
wherein the first inner spacers have side surfaces that are curved and are convex toward first inner portions of the first gate electrode,
wherein the second inner spacers have side surfaces that are curved and are convex toward second inner portions of the second gate electrode,
In the similar field of endeavor, KIM et al. Fig. 57 discloses, wherein at least one of the first inner spacers 142 and at least one of the second inner spacers 242 are disposed at the same height level and have different thicknesses (Fig. 57 shows inner spacers 142 and 242 in same height level has different widths/thicknesses) in the first direction.
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify Lien et al, with the variable width of the spacers depending on the heights of KIM et al. in order to provide a semiconductor device capable of enhancing device performance by variably adjusting threshold voltage of a transistor having gate-all-around structure (KIM et al. ¶ [007]).
However, KIM et al. does not disclose, wherein the first inner spacers have side surfaces that are curved and are convex toward first inner portions of the first gate electrode,
wherein the second inner spacers have side surfaces that are curved and are convex toward second inner portions of the second gate electrode,
In the similar field of semiconductor devices, Lee et al. Figs. 5A-5B discloses wherein the first inner spacers (“internal spacers IS” ¶ [0057]) have side surfaces that are curved and are convex toward (Figs. 5A-5B shows first inner spacers IS have side surfaces that are curved and are convex toward GE) the inner portions of the gate electrode GE (“gate electrode GE” ¶ [0057]).
wherein the second inner spacers (“internal spacers IS” ¶ [0057]) have side surfaces that are curved and are convex toward (Figs. 5A-5B shows second inner spacers IS have side surfaces that are curved and are convex toward GE) the inner portions of the gate electrode GE (“gate electrode GE” ¶ [0057]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify Liaw et al, with the variable width of the inner spacers of Lee et al. in order to space apart source/drain regions from the gate electrode GE with the internal spacers IS interposed therebetween. (Lee et al. 0043]).
Regarding Claim 13, Liaw et al. as modified by KIM et al. and Lee et al. discloses the limitations of claim 12 as described above. Liaw et al. Fig. 14 further discloses, wherein the first inner portions are between the first inner spacers (Fig. 14 shows inner portions between the spacers 255 on PG-1),
wherein the second inner portions are between the second inner spacers (Fig. 14 shows inner portions between the spacers 255 on PD-1).
However, Liaw et al. does not disclose, wherein at least one of the first inner portions and at least one of the second inner portions are disposed on the same height level as each other and have different gate lengths in the first direction.
In the similar field of endeavor, KIM et al. Fig. 57 discloses, wherein at least one of the first inner portions (inner portions of 224 between the spacers 242) and at least one of the second inner portions (inner portions of 124 between the spacers 142) are disposed on the same height level as each other and have different gate lengths (Fig. 57 shows inner portions of 224 and 124 in same height level has different gate lengths) in the first direction (horizontal direction).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify Liaw et al, with the variable width of the gate lengths depending on the heights of KIM et al. in order to provide a semiconductor device capable of enhancing device performance by variably adjusting threshold voltage of a transistor having gate-all-around structure (KIM et al. ¶ [007]).
Regarding Claim 15, Liaw et al. as modified by KIM et al. and Lee et al. discloses the limitations of claim 12 as described above. Liaw et al. Fig. 14 further discloses, wherein the first source/drain regions (260N on PG-1) project into recesses in the active fin to a position lower than a top of the active fin (Fig. 14 shows (260N on PG-1) position lower than the active fin), and
wherein the second source/drain regions (260N on PD-1) project into recesses in the active fin to a position lower than the top of the active fin (Fig. 14 shows (260N on PD-1) position lower than the active fin).
Regarding Claim 16, Liaw et al. as modified by KIM et al. and Lee et al. discloses the limitations of claim 12 as described above. Liaw et al. Fig. 14 further discloses, wherein an uppermost first inner spacer (uppermost inner spacer 255 on PG-1) among the first inner spacers 255 contacts (Fig 14 shows uppermost inner spacer 255 on PG-1 contacts lower surface of uppermost 215A) a lower surface of an uppermost first channel layer (uppermost 215A) among the first channel layers 215A, and
wherein an uppermost second inner spacer (uppermost inner spacer 255 on PD-1) among the second inner spacers 255 contacts (Fig 14 shows uppermost inner spacer 255 on PD-1 contacts lower surface of uppermost 215B) a lower surface of an uppermost second channel layer (uppermost 215B) among the second channel layers 215B.
Regarding Independent Claim 19, Liaw et al. Figs. 1B and 12-14 discloses a semiconductor device (“6T SP SRAM cell 104” ¶ [0024]) comprising:
a substrate (“substrate 202” ¶ [0051]);
a static random-access memory (SRAM) cell (“SRAM macro 102” ¶ [0050]) comprising a pass-gate transistor PG-1 (“two NMOS transistors as pass-gate (or access) transistors PG-1 and PG-2.” ¶ [0024]), a pull- down transistor PD-1 (“two NMOS transistors as pull-down transistors PD-1 and PD-2” ¶ [0024]), and a pull-up transistor PU-1 (“two PMOS transistors as pull-up transistors PU-1 and PU-2) on the substrate 202,
wherein the SRAM cell comprises an active fin 205 (“the active regions 205 (205A, 205B, 205C, and 205D) in the HD SRAM macro 102 (or in the HD SRAM cell 104) include horizontally oriented vertically stacked transistor channels” ¶ [0050]) extending in a first direction,
wherein the pass-gate transistor PG-1 and the pull-down transistor PD-1 are disposed adjacent to each other on the active fin 205 in the first direction (Fig. 14 shows PG-1 and PD-1 are adjacent to each other in the horizontal direction),
wherein the pass-gate transistor PG-1 comprises first channel layers 215A (“the channels 215A and 215F (for the transistors PG-1 and PG-2 respectively)” ¶ [0050]) disposed on the active fin 205, a first gate electrode (350 on PG-1) (“gate stack 240A (including a gate dielectric layer 282 and a gate electrode 350) wraps around each of the channel layer 215A (FIG. 13), forming an NMOS gate-all-round (GAA) transistor PG-1.” ¶ [0051]) intersecting the active fin 205 and surrounding the first channel layers 215A,
a first gate dielectric layer (282 on PG-1) (“a gate dielectric layer 282” ¶ [0051]) between the first channel layers 215A and the first gate electrode (350 on PG-1),
first source/drain regions 260N (“a pair of source/drain features 260N” ¶ [0051]) disposed on the active fin 205 on opposite sides of the first gate electrode 350,
wherein the pull-down transistor PD-1 comprises second channel layers 215B (“the channels 215B and 215E (for the transistors PD-1 and PD-2 respectively)” ¶ [0050]) disposed on the active fin 205, a second gate electrode (350 on PD-1) (“a gate electrode 350) wraps around each of the channel layer 215A (FIG. 13), forming an NMOS gate-all-round (GAA) transistor PG-1. The other transistors PU-1, PU-2, PD-1, PD-2, and PG-2 are similarly configured as GAA transistors.” ¶ [0051]) intersecting the active fin 205 and surrounding the second channel layers 215B,
a second gate dielectric layer (282 on PD-1) (“a gate dielectric layer 282” ¶ [0051]) between the second channel layers 215B and the second gate electrode (350 on PD-1),
second source/drain regions 260N (“source/drain feature 260 (including 260P for PMOSFET and 260N for NMOSFET) in the source/drain regions” ¶ [0050]) disposed on the active fin on opposite sides of the second gate electrode (350 on PD-1),
wherein the first gate electrode (350 on PG-1) comprises first inner portions between first inner spacers (Fig. 14 shows gate electrode 350 has inner portions between the spacers 255 on PG-1),
wherein the second gate electrode (350 on PD-1) comprises second inner portions between second inner spacers (Fig. 14 shows gate electrode 350 has inner portions between the spacers 255 on PD-1), and
wherein at least one of the first source/drain regions (260N on PG-1) of the pass-gate transistor PG-1 and at least one of the second source/drain regions (260N on PD-1) of the pull-down transistor PD-1 is a shared source/drain region (Fig. 14 shows the middle source/drain region 260N is shared between PG-1 and PD-1).
wherein the shared source/drain region 260N contacts (“each of the channel layers 215A and 215B (as well as the channel layers 215E and 215F) connects a pair of n-type source/drain features 260N, and the channel layer 215D (as well as the channel layer 215C) connects a pair of p-type source/drain features 260P.” ¶ [0032]) the first channel layers 215A and the second channel layers 215B.
However, Liaw et al. does not disclose, wherein at least one of the first inner portions and at least one of the second inner portions are disposed on the same height level as each other and have different gate lengths in the first direction.
the first inner portions having opposite side surfaces that are curved and are concave,
the second inner portions having opposite side surfaces that are curved and are concave,
In the similar field of endeavor, KIM et al. Fig. 57 discloses,
wherein at least one of the first inner portions (inner portions of 224 between the spacers 242) and at least one of the second inner portions (inner portions of 124 between the spacers 142) are disposed on the same height level as each other and have different gate lengths (Fig. 57 shows inner portions of 224 and 124 in same height level has different gate lengths) in the first direction (horizontal direction).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify Lien et al, with the variable width of the gate lengths depending on the heights of KIM et al. in order to provide a semiconductor device capable of enhancing device performance by variably adjusting threshold voltage of a transistor having gate-all-around structure (KIM et al. ¶ [007]).
However, KIM et al. does not disclose, wherein the first inner spacers have side surfaces that are curved and are convex toward first inner portions of the first gate electrode,
wherein the second inner spacers have side surfaces that are curved and are convex toward second inner portions of the second gate electrode,
In the similar field of semiconductor devices, Lee et al. Figs. 5A-5B discloses wherein the first inner spacers (“internal spacers IS” ¶ [0057]) have side surfaces that are curved and are convex toward (Figs. 5A-5B shows first inner spacers IS have side surfaces that are curved and are convex toward GE) the inner portions of the gate electrode GE (“gate electrode GE” ¶ [0057]).
wherein the second inner spacers (“internal spacers IS” ¶ [0057]) have side surfaces that are curved and are convex toward (Figs. 5A-5B shows second inner spacers IS have side surfaces that are curved and are convex toward GE) the inner portions of the gate electrode GE (“gate electrode GE” ¶ [0057]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify Liaw et al, with the variable width of the inner spacers of Lee et al. in order to space apart source/drain regions from the gate electrode GE with the internal spacers IS interposed therebetween. (Lee et al. 0043]).
Regarding Claim 20, Liaw et al. as modified by KIM et al. discloses the limitations of claim 16 as described above. Liaw et al. Fig. 14 further discloses, wherein the first source/drain regions (260N on PG-1) project into recesses in the active fin to a position lower than a top of the active fin (Fig. 14 shows (260N on PG-1) position lower than the active fin), and
wherein the second source/drain regions (260N on PD-1) project into recesses in the active fin to a position lower than the top of the active fin (Fig. 14 shows (260N on PD-1) position lower than the active fin).
Claims 5 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw, Jhon Jhy () “Liaw et al.” in view of KIM, Bo Soon (US 20170200738 A1) “KIM et al.” further in view of Huang, Jui-Chien (US 20210066294 A1) “Huang et al.”.
Regarding Claim 5, Liaw et al. as modified by KIM et al. discloses the limitations of claim 1 as described above. Liaw et al. Fig. 14 further discloses, wherein the first inner spacers (255s on PG-1) include a first layer (bottom 255 on PG-1) in the first direction, a second layer (middle 255 on PG-1) in the first direction, and a third layer (top 255 on PG-1) in the first direction, and
wherein the second inner spacers (255s on PD-1) include a fourth layer (bottom 255 on PD-1) in the first direction, a fifth layer (middle 255 on PD-1) in the first direction, and a sixth layer (top 255 on PD-1) in the first direction.
However, Liaw does not disclose, wherein the first inner spacers include a first layer having a first thickness in the first direction, a second layer having a second thickness less than the first thickness in the first direction, and a third layer a third thickness less than the second thickness in the first direction, and
wherein the second inner spacers include a fourth layer having a fourth thickness in the first direction, a fifth layer having a fifth thickness less than the fourth thickness in the first direction, and a sixth layer having a sixth thickness less than the fifth thickness in the first direction.
In the similar field of endeavor of semiconductor devices, Huang et al. Figs. 2C-2F discloses wherein the first inner spacers (214 on the stack 201a) (“sidewall structures 214” ¶ [0037]) include a first layer (214a on the stack 201a) (“inner spacers 214a” ¶ [0037]) having a first thickness in the first direction, a second layer (214b on the stack 201a) (“inner spacers 214b” ¶ [0037]) having a second thickness less than the first thickness in the first direction, and a third layer (214c on the stack 201a) (“inner spacers 214c” ¶ [0037]) a third thickness less than the second thickness in the first direction (“lower layers will have wider inner spacers than upper layers. In the present example, inner spacers 214a are wider than inner spacers 214b. Similarly, inner spacers 214b are wider than inner spacers 214c. Inner spacers 214c are wider than inner spacers 214d.” ¶ [0038]), and
wherein the second inner spacers (214 on the stack 201b) (“sidewall structures 214” ¶ [0037]) include a fourth layer (214a on the stack 201b) (“inner spacers 214a” ¶ [0037]) having a fourth thickness in the first direction, a fifth layer (214b on the stack 201b) (“inner spacers 214b” ¶ [0037]) having a fifth thickness less than the fourth thickness in the first direction, and a sixth layer (214c on the stack 201b) (“inner spacers 214c” ¶ [0037]) having a sixth thickness less than the fifth thickness in the first direction (“lower layers will have wider inner spacers than upper layers. In the present example, inner spacers 214a are wider than inner spacers 214b. Similarly, inner spacers 214b are wider than inner spacers 214c. Inner spacers 214c are wider than inner spacers 214d.” ¶ [0038]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify Liaw et al, with the variable width of the inner spacers of Huang et al. in order to produce a fin stack gate device that has a uniform gate width surrounding each of the nanostructure. Specifically, each layer of the alternating semiconductor material layers may vary in characteristics that affect etch rate. … The etched away portions can then be filled with a dielectric material. After the gate is formed, it will be more uniform in width, and the inner spacers will be wider at lower levels than they are at higher levels (Huang et al. ¶ [0014]) and device performance is improved (Huang et al. 0043]).
Claims 6 is rejected under 35 U.S.C. 103 as being unpatentable over Liaw, Jhon Jhy () “Liaw et al.” in view of KIM, Bo Soon (US 20170200738 A1) “KIM et al.” further in view of Huang, Jui-Chien (US 20210066294 A1) “Huang et al.” further in view of Xie, Ruilong (US 20220399450 A1) “Xie et al.”.
Regarding Claim 6, Liaw et al. as modified by KIM et al. and Huang et al. discloses the limitations of claim 5 as described above. However, Liaw et al. does not disclose wherein the first thickness is greater than the fourth thickness, wherein the second thickness is greater than the fifth thickness, and wherein the third thickness is greater than the sixth thickness.
In the similar field of endeavor of semiconductor devices, Xie et al. Figs. 5A-5C discloses wherein the first thickness (134B on the lowest layer) is greater than the fourth (134A on the lowest layer) thickness, wherein the second thickness (second 134B from the lowest 134B) is greater than the fifth thickness (second 134A from the lowest 134A), and wherein the third thickness (third 134B from the lowest 134B) is greater than the sixth thickness (third 134A from the lowest 134A).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify Liaw et al, with the variable width of the inner spacers of Xie et al. in order to achieve concurrent formation of a thin gate oxide nanosheet device and the formation of a thick gate oxide device on the same substrate (Xie et al. 0043]).
Claims 17 is rejected under 35 U.S.C. 103 as being unpatentable over Liaw, Jhon Jhy () “Liaw et al.” in view of KIM, Bo Soon (US 20170200738 A1) “KIM et al.” further in view of Xie, Ruilong (US 20220399450 A1) “Xie et al.”.
Regarding Claim 17, Liaw et al. as modified by KIM et al. discloses the limitations of claim 16 as described above. However, Liaw et al. does not disclose, wherein the uppermost first inner spacer has a first thickness in the first direction,
wherein the uppermost second inner spacer has a second thickness in the first direction, and wherein the first thickness is greater than the second thickness.
In the similar field of endeavor of semiconductor devices, Xie et al. Figs. 5A-5C discloses wherein the uppermost first inner spacer has a first thickness in the first direction (134B on the uppermost layer)
wherein the uppermost second inner spacer has a second thickness in the first direction (134A on the uppermost layer), and
wherein the first thickness is greater than the second thickness (Figs. 5A-5C show 134B is thicker than 134A)
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify Liaw et al, with the variable width of the inner spacers of Xie et al. in order to achieve concurrent formation of a thin gate oxide nanosheet device and the formation of a thick gate oxide device on the same substrate (Xie et al. 0043]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/AKHEE SARKER-NAG/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893