DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Amendment filed 12/10/2025.
Claims 1, 5-11 and 16-19 are pending. Claims 16-19 are withdrawn. Claims 2-4 and 12-15 are cancelled. Claim 1 is currently amended. Claim 1 is independent.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1/2/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Arguments
Applicants’ arguments and amendments, filed 12/10/2025, with respect 112 Rejections, as indicated in line number 2 of the office action mailed 9/11/2025, have been fully considered and are persuasive. The rejections have been withdrawn.
Applicants' arguments and amendments, filed 12/10/2025, with respect to independent claim 1, although substantive and pertinent to expediting the prosecution of the current application, are considered not persuasive, respectfully, for the reasons that follow.
Regarding independent claim 1, the claim has been amended to recite “wherein the plastic packaging layer covers each of the plurality of chips p and the sheet- like structure on the active surface side, the connection terminal of each of the plurality of chips is exposed from a surface of the plastic packaging layer away from the active surface, and the redistribution layer is disposed on a surface of the plastic packaging layer” which applicants contend is not disclosed or taught by the prior art, including Jeong, since insulating part 150 and insulating layers 131/141 are structurally distinct and functionally different components and conflating the two disparate components is improper. Additionally, Jeong’s terminals 120P are on the bottom (active surface side), and claim 1 requires the terminals to be exposed form the top surface of the packaging layer (the surface away from the active surface). Applicants further contends that Jeong does not teach a one-to-one correspondence of a component in a through-hole. Lastly, applicants contends that the claimed ratio of an area of the first region to an area of the second region is non-obvious due to a synergistic effect tied to the specific ratio. (Remarks 6-9)
Applicants’ contentions are fully considered, however are not found persuasive, since the interpretation of the claimed “plastic packaging layer” as collectively being elements 131 and 150 in Jeong is deemed proper, because as noted in paragraphs [0063] and [0069] both elements 131 and 150 can be comprise of similar plastic compositions. Claim 1, as currently written, does not impose any restriction such that the interpretation of multiple elements collectively as the “plastic packaging layer” would be impermissible. Additionally, Jeong discloses the claim limitation “the connection terminal of each of the plurality of chips is exposed from a surface of the plastic packaging layer away from the active surface”, because as noted below in the rejections of independent claim 1 portions of connection terminals 120P, 122P are directly covered by vias 133 and not by layer 131 and thereby those portions of 120P, 122P are exposed from a surface (i.e., bottom surface of 131) of layer 131/150 and the bottom surface of 131 is away from the active surface as shown in Figures and 5E and 22 of Jeong. Note, the claim language “away from the active surface” in the limitation “the connection terminal of each of the plurality of chips is exposed from a surface of the plastic packaging layer away from the active surface” is being interpreted in association with “a surface of the plastic packaging layer”. Claim 1, as currently written, allows for that specific interpretation of the claim language. Furthermore, paragraphs [0080] and [0083] of Jeong discloses a plurality of chips 120 are disposed in each of through-holes 110X and then sawed to produce each individual package 100A as shown in Figures 4 and 5E of Jeong and thereby Jeong teaches a “one-to-one correspondence” of a component 120 in a through-hole 110X. Lastly, regarding the claimed ratio of an area of the first region to an area of the second region the current rejection of record does not seek to classify the claimed ratio as a result-effective variable for balancing warpage and strength. Rather, as noted below in the rejections of independent claims 1 it is stated that it would have been obvious to form the ratio of an area of the first region to an area of the second region within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Thus, for the aforementioned reasons the rejection is deemed proper.
Claim Objections
Claim 1 is objected to because of the following informalities:
Claim 1 recites the limitation “the plurality of chips p” in line 17 of the claim, which appears to be a typographical error, and thus the Examiner suggests amending the limitation to remove the letter “p”.
Appropriate correction is required.
A. Prior-art rejections based by Jeong
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 and 5-9 are rejected under 35 U.S.C. 103 as being unpatentable and obvious over Jeong et al. (US 2016/0336296 A1, hereinafter “Jeong”).
Regarding independent claim 1, Figures 22-23 of Jeong disclose a wafer-level fan-out structure, comprising:
a plurality of chips 120, 122 (“electronic components”- ¶¶0057, 0129), a sheet-like structure 110 (“frame”- ¶0128) and a plastic packaging layer 131/150 (collectively 131 “insulating layers” and 150 “insulating part”- ¶¶0063, 0069, 0128), wherein each of the plurality of chips 120, 122 comprises an active surface and a connection terminal 120P, 122P (“electrode pads”- ¶0127), the connection terminal 120P, 122P being located on the active surface;
wherein the plastic packaging layer 131/150 covers the plurality of chips 120, 122 and the sheet-like structure 110; the sheet-like structure 110 comprising a first region and a second region, the first region comprising a plurality of spaced apertures 110X1, 110X2 (“holes”- ¶0128), and each aperture 110X1, 110X2 being adjacent to the second region; the plurality of chips 120, 122 and the plurality of apertures 110X1, 110X2 are in one-to-one correspondence, and each of the plurality of chips 120, 122 is located in the corresponding aperture 110X1, 110X2; and
a Young's modulus of the plastic packaging layer 131/150 (Note, 131 and 150 can comprise the same materials- ¶¶0063, 0069) is lower than that of the sheet-like structure 110, since the Young’s modulus is analogous to the elastic modulus of elements 131/150 and 110 (¶0070);
the wafer-level fan-out structure further comprises:
a redistribution layer 140 (“redistribution parts”- ¶0048) disposed on an active surface side and electrically connected to the connection terminal 120P, 122P (¶0127); and
an interconnection structure 165 (“connection terminals”- ¶0061) which is disposed on a side surface of the redistribution layer 140 away from the connection terminal 120P, 122P, and is electrically connected to the redistribution layer 140 (¶0061);
wherein the plastic packaging layer 131/150 covers each of the plurality of the chips 120, 122 p and the sheet-like structure 110 on the active surface side, the connection terminal 120P, 122P of each of the plurality of chips 120, 122 is exposed from a surface of the plastic packaging layer 131/150 away from the active surface, since portions of connection terminals 120P, 122P are directly covered by vias 133 and not by layer 131 and thereby those portions of 120P, 122P are exposed from a surface (i.e., bottom surface of 131) of layer 131/150 and the bottom surface of layer 131 is away from the active surface, and the redistribution layer 140 is disposed on a surface of the plastic packaging layer 131/150.
Jeong does not expressly disclose wherein a ratio of an area of the first region to an area of the second region is (0.5-2):1.
However, it would have been obvious to form the ratio of an area of the first region to an area of the second region within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Regarding claim 5, Figures 22-23 of Jeong (as modified to include elements 113 as shown in Fig. 13- ¶0129) disclose wherein the sheet-like 110 structure further comprises a metal post 113 (“though wirings”- ¶0104), the metal post 113 is embedded into the second region and comprises a connection end surface, the connection end surface and the connection terminal 120P are located on the same side, and the connection end surface and the redistribution layer 140 are electrically connected to each other (¶0104).
Regarding claim 6, Figures 22-23 of Jeong disclose a thickness of the sheet-like structure 110, a film thickness of the plastic packaging layer 150 and a thickness of each of the plurality of chips 120, 122.
Jeong does not expressly disclose wherein a ratio of the thickness of the sheet-like structure, the film thickness of the plastic packaging layer and the thickness of the chip is (0.5-2):(1-2):1.
However, it would have been obvious to form the thickness of the sheet-like structure, the film thickness of the plastic packaging layer and the thickness of the chip such that the ratio of the thickness of the sheet-like structure, the film thickness of the plastic packaging layer and the thickness of the chip is within the claimed ranges, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Regarding claim 7, Figures 22-23 of Jeong disclose wherein the sheet-like structure 110 is made of pure metal, alloy, organic resin or a combination thereof (¶0050).
Regarding claim 8, Figures 22-23 of Jeong disclose wherein the alloy is hard alloy or stainless steel (¶0050).
Regarding claim 9, the limitation “wherein the organic resin is epoxy resin, phenolic resin, amino resin or unsaturated polyester resin” is moot, since Jeong discloses the other suitable compositions for structure 110 as required in intervening claim 7 (¶0050).
B. Prior-art rejections based by Jeong (different embodiment)
Claim Rejections - 35 USC § 103
Claims 1 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable and obvious over Jeong (different embodiment).
Regarding independent claim 1, Figure 5E of Jeong disclose a wafer-level fan-out structure, comprising:
a plurality of chips 120 (“electronic component”- ¶0057, since a plurality of chips 120 are disposed in each of through-holes 110X and then sawed to produce each individual package 100A as shown in Figures 4 and 5E- ¶¶0080, 0083), a sheet-like structure 110 (“frame”- ¶0128) and a plastic packaging layer 131/150 (collectively 131 “insulating layers” and 150 “insulating part”- ¶¶0063, 0069, 0128), wherein each of the plurality of chips 120 comprises an active surface and a connection terminal 120P (“electrode pads”- ¶0127), the connection terminal 120P being located on the active surface;
wherein the plastic packaging layer 131/150 covers the plurality of chips 120 and the sheet-like structure 110; the sheet-like structure 110 comprising a first region and a second region, the first region comprising a plurality of spaced apertures 110X (“through-holes”- ¶0083; see Fig. 5B), and each aperture 110X being adjacent to the second region; the plurality of chips 120 and the plurality of apertures 110X are in one-to-one correspondence, and each of the plurality of chips 120 is located in the corresponding aperture 110X; and
a Young's modulus of the plastic packaging layer 131/150 (Note, 131 and 150 can comprise the same materials- ¶¶0063, 0069) is lower than that of the sheet-like structure 110, since the Young’s modulus is analogous to the elastic modulus of elements 131/150 and 110 (¶0070);
the wafer-level fan-out structure further comprises:
a redistribution layer 140 (“redistribution parts”- ¶0048) disposed on an active surface side and electrically connected to the connection terminal 120P (¶0127); and
an interconnection structure 165 (“connection terminals”- ¶0061) which is disposed on a side surface of the redistribution layer 140 away from the connection terminal 120P, and is electrically connected to the redistribution layer 140 (¶0061);
wherein the plastic packaging layer 131/150 covers each of the plurality of the chips 120 p and the sheet-like structure 110 on the active surface side, the connection terminal 120P of each of the plurality of chips 120 is exposed from a surface of the plastic packaging layer 131/150 away from the active surface, since portions of connection terminals 120P are directly covered by vias 133 and not by layer 131 and thereby those portions of 120P are exposed from a surface (i.e., bottom surface of 131) of layer 131/150 and the bottom surface of layer 131 is away from the active surface, and the redistribution layer 140 is disposed on a surface of the plastic packaging layer 131/150.
Jeong does not expressly disclose wherein a ratio of an area of the first region to an area of the second region is (0.5-2):1.
However, it would have been obvious to form the ratio of an area of the first region to an area of the second region within the claimed range, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Regarding claim 10, Figure 5E of Jeong discloses wherein the sheet-like structure 110 further comprises a plurality of cutting lines (i.e., the areas which are sawed during the “sawing process”- ¶0080), the plurality of cutting lines are located in the second region and surround the plurality of apertures 110X, and a plurality of single packages are obtained by cutting the wafer-level fan-out structure along the plurality of cutting lines (¶0080).
Additionally, regarding the claim limitation “a plurality of single packages are obtained by cutting the wafer-level fan-out structure along the plurality of cutting lines” which is drawn to process steps of a product-by-process claim, such method step(s) are not considered to render an old apparatus patentable where the prior art teaches a product that appears to be the same as, or an obvious variant of, the product set forth in a product-by-process claim although produced by a different process. That is even though product-by-process claims are limited by and defined by the process, the determination of patentability of the claims is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior art product was made by a different process. See MPEP 2113. In this regard, both claimed products and the prior art products would be the same or substantially the same.
Regarding claim 11, Figure 5E of Jeong discloses wherein in each single package, an area of the plastic packaging layer 150 surrounding each of the plurality of chips 120; and an area of the sheet-like structure 110 surrounding each of the plurality of chips 120, wherein the area of the sheet-like structure 110 surrounding each of the plurality of chips 120 is less than or equal to the area of the plastic packaging layer 150, since layer 150 surrounds three sides of chip 120 while structure 110 only surrounds two sides of chip 120 as shown in Figure 5E.
Jeong does not expressly disclose wherein in each single package, a ratio of an area of each of the plurality of chips to the area of the plastic packaging layer surrounding each of the plurality of chips is 1:(1-15); and a ratio of the area of each of the plurality of chips to the area of the sheet-like structure surrounding each chip is 1:(1-15).
However, it would have been obvious to form the ratio of an area of each of the plurality of chips to the area of the plastic packaging layer surrounding each of the plurality of chips and the ratio of the area of each of the plurality of chips to the area of the sheet-like structure surrounding each chip within the claimed ranges, respectively, since it has been held by the Federal circuit that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. (In Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984)).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAY C CHANG whose telephone number is (571)272-6132. The examiner can normally be reached Mon- Fri 12pm-10pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571)-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAY C CHANG/ Primary Examiner, Art Unit 2817
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