Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
RCE, received 12/16/2025, has been entered.
Claims 1-5, 7, 9-13 and 15 are presented for examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bour et al. (US Pub. No. 2018/0374991 A1), hereafter referred to as Bour.
As to claim 1, Bour discloses a micro LED (fig 15, [0082]), comprising:
a first type semiconductor layer (see annotated figure 15 rotated upside down, 106);
a light emitting layer (108) formed on the first type semiconductor layer (106);
a second type semiconductor layer (112/114/110) formed on the light emitting layer (108);
a first electrode formed at a bottom of the first type semiconductor layer (see rotated figure 15, below, first electrode 182 at bottom of 106); and
a second electrode (180) formed at a top of the second type semiconductor layer 112/114/110);
wherein a bottom sidewall of the second type semiconductor layer is aligned with a sidewall of the first type semiconductor layer (bottom sidewall of 110 is shown as aligned with sidewall of 106); and
a sidewall of the second type semiconductor layer does not conform to a straight line (step of 110 creates a non-straight line);
wherein a thickness of the second type semiconductor layer is larger than twice of a thickness of the first type semiconductor layer ([0065]);
wherein a maximum width of the first electrode (182) is less than or equal to a minimum width of the second electrode (180).
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As to claim 2, Bour discloses the micro LED according to claim 1 (paragraphs above),
wherein the sidewall of the second type semiconductor layer comprises at least one step (fig 15, step of layer 110).
As to claim 3, Bour discloses the micro LED according to claim 2 (paragraphs above),
wherein a bottom width of a bottom step structure of the second type semiconductor layer is the same as a top width of the first type semiconductor layer (fig 15, same as applicant considers the emitting layer to be part of the semiconductor layer such that bottom step structure 110 has the same width).
As to claim 4, Bour discloses the micro LED according to claim 2 (paragraphs above),
wherein a sidewall of a bottom step structure of the second type semiconductor layer is aligned with a sidewall of the light emitting layer (fig 15, sidewalls of 110 and 108 are aligned).
As to claim 5, Bour discloses the micro LED according to claim 1 (paragraphs above),
wherein the sidewall of the first type semiconductor layer is aligned with a sidewall of the light emitting layer (fig 15, sidewalls of 106 and 108 are aligned).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bour in view of Cheng et al. (US Pub. No. 2019/0355704 A1), hereafter referred to as Cheng.
As to claim 7, Bour discloses the micro LED according to claim 1 (paragraphs above).
Bour does not disclose wherein a maximum width of the first electrode is less than a minimum width of the first type semiconductor layer.
Nonetheless, Cheng discloses a similar micro LED wherein a maximum width of the first electrode is less than a minimum width of the first type semiconductor layer (fig 2, micro LED with bottom electrode 121 less width than LED 12).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form the relative widths of the semiconductor layer and first electrode such that the first electrode is less since this will optimize the luminesce output with respect to electrical input.
Claim(s) 10-13 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chaji et al. (US 2020/0013662 A1), hereafter referred to as Chaji, in view of Bour.
As to claim 10, Chaji discloses a micro LED panel comprising two or more micro LEDs (fig 1H, [0108]-[0109]),
a first type semiconductor layer (112; [0109]);
a light emitting layer (114) formed on the first type semiconductor layer (112); and
a second type semiconductor layer (116) formed on the light emitting layer (114),
wherein the light emitting layer (114) is continuous between adjacent ones of the two or more micro LEDs (fig 1H, continuous layer 114; [0180]).
Chaji does not disclose wherein a sidewall of the second type semiconductor layer does not conform to a straight line; and a thickness of the second type semiconductor layer is larger than twice of a thickness of the first type semiconductor layer.
Nonetheless, Bour discloses a micro LED (fig 15, [0082]), comprising:
a first type semiconductor layer (see annotated figure 15 rotated upside down, 106);
a light emitting layer (108) formed on the first type semiconductor layer (106);
a second type semiconductor layer (112/114/110) formed on the light emitting layer (108);
a first electrode formed at a bottom of the first type semiconductor layer (see rotated figure 15, below, first electrode 182 at bottom of 106); and
a second electrode (180) formed at a top of the second type semiconductor layer 112/114/110);
wherein a bottom sidewall of the second type semiconductor layer is aligned with a sidewall of the first type semiconductor layer (bottom sidewall of 110 is shown as aligned with sidewall of 106); and
a sidewall of the second type semiconductor layer does not conform to a straight line (step of 110 creates a non-straight line);
wherein a thickness of the second type semiconductor layer is larger than twice of a thickness of the first type semiconductor layer ([0065]);
wherein a maximum width of the first electrode (182) is less than or equal to a minimum width of the second electrode (180).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form the microLEDs of Chaji with the non-straight sidewall and thickness taught in Bour since this will confine current internally within the LED device and away from the external sidewalls where non-radiative recombination may occur.
As to claim 11, Chaji in view of Bour discloses the micro LED panel according to claim 10 (paragraphs above),
Chaji further discloses wherein the light emitting layer is formed by a quantum well layer ([0109]).
As to claim 12, Chaji in view of Bour discloses the micro LED panel according to claim 10 (paragraphs above),
Chaji further discloses an isolation structure (128) between the adjacent ones of the two or more micro LEDs (LED regions 116).
As to claim 13, Chaji in view of Bour discloses the micro LED panel according to claim 10 (paragraphs above),
Chaji further discloses wherein the first type semiconductor layer is continuous between the adjacent ones of the two or more micro LEDs (fig 2E, 212).
As to claim 15, Chaji discloses a micro LED chip comprising one or more micro LED panels, wherein each one of the one or more micro LED panels comprises two or more micro LEDs, and each one of the two or more micro LEDs comprises (fig 1H, [0108]-[0109]):
a first type semiconductor layer (112; [0109]);
a light emitting layer (114) formed on the first type semiconductor layer (112); and
a second type semiconductor layer (116) formed on the light emitting layer (114),
wherein the light emitting layer (114) is continuous between adjacent ones of the two or more micro LEDs (fig 1H, continuous layer 114; [0180]).
Chaji does not disclose wherein a sidewall of the second type semiconductor layer does not conform to a straight line; and a thickness of the second type semiconductor layer is larger than twice of a thickness of the first type semiconductor layer.
Nonetheless, Bour discloses a micro LED (fig 15, [0082]), comprising:
a first type semiconductor layer (see annotated figure 15 rotated upside down, 106);
a light emitting layer (108) formed on the first type semiconductor layer (106);
a second type semiconductor layer (112/114/110) formed on the light emitting layer (108);
a first electrode formed at a bottom of the first type semiconductor layer (see rotated figure 15, below, first electrode 182 at bottom of 106); and
a second electrode (180) formed at a top of the second type semiconductor layer 112/114/110);
wherein a bottom sidewall of the second type semiconductor layer is aligned with a sidewall of the first type semiconductor layer (bottom sidewall of 110 is shown as aligned with sidewall of 106); and
a sidewall of the second type semiconductor layer does not conform to a straight line (step of 110 creates a non-straight line);
wherein a thickness of the second type semiconductor layer is larger than twice of a thickness of the first type semiconductor layer ([0065]);
wherein a maximum width of the first electrode (182) is less than or equal to a minimum width of the second electrode (180).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to form the microLEDs of Chaji with the non-straight sidewall and thickness taught in Bour since this will confine current internally within the LED device and away from the external sidewalls where non-radiative recombination may occur.
Allowable Subject Matter
Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record fails to teach or suggest wherein a maximum width of the second electrode is less than a bottom width of the second type semiconductor, as recited in claim 9 and including the limitations of independent claim 1.
Response to Arguments
Applicant's arguments filed 11/17/2025 have been fully considered but they are not persuasive.
Applicant argued that Bour in view of Cheng does not disclose wherein a maximum width of the first electrode is less than or equal to a minimum width of the second electrode, as recited in the amended independent claims.
Examiner disagrees because even though figure 12A of Bour does not disclose this limitation, new ground of rejection relying of figure 15 of Bour does anticipate this limitation.
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Pub. No. 2023/0006105A1; US Pub. No. 2020/0219438A1; US 2021/0157142A1.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAUN M CAMPBELL whose telephone number is (571)270-3830. The examiner can normally be reached on MWFS: 7:30-6pm Thurs 1-2pm.
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/SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893 2/10/2026