DETAILED ACTION
This communication is a non-final office action on the merits on patent application 18116721, attorney docket AA6116-US-D1-C1 111548 claims Priority from Provisional Application 62593149 , filed 11/30/2017 the application is assigned to Intel Corp. The present application was filed on or after March 16, 2013 and is being examined under the first inventor to file provisions of the AIA . Claims 1-5,7-20 are pending and are considered below. Note that examiner will use numbers in parentheses to indicate numbered elements in prior art figures, and brackets to point to paragraph numbers where quoted material or specific teachings can be found.
A request for continued examination under 37 CFR 1.114 was filed in this application after a decision by the Patent Trial and Appeal Board, but before the filing of a Notice of Appeal to the Court of Appeals for the Federal Circuit or the commencement of a civil action. Since this application is eligible for continued examination under 37 CFR 1.114 and the fee set forth in 37 CFR 1.17(e) has been timely paid, the appeal has been withdrawn pursuant to 37 CFR 1.114 and prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant’s submission filed on 6/18/2026 has been entered.
Response to Arguments
Applicant has amended claims 1 and 8 and correctly argues that removing the limitations of a flat bottom overcomes the §112a for lack of support which is withdrawn except where noted.
Claim Rejections - 35 USC § 112
Claims 13-20 are rejected under 35 U.S.C. 112(a) because the specification, does not reasonably provide enablement for a flat bottom second insulation layer. The specification does not enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make the invention commensurate in scope with these claims.
Claim 13, recites, “the second insulating layer having a flat bottom surface joining rounded corners”, which lacks support in the specification. (See previous office actions for explanation.) Examiner assumes the retention of the limitation was accidental.
Dependent claims include the defect of the parent.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-15 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Sung et al. (U.S. 2016/0351565) in view of Ching et al. (U.S. 2018/0301384).
As for claim 1,
Sung teaches in figure 4d, figure 17, an integrated circuit structure, comprising: a
first discrete three-dimensional body (F1i, left center) comprising silicon ([0067]);
a second discrete three-dimensional body (F1i, right center) comprising silicon [0067];
a trench isolation structure (120) between the first discrete three-dimensional body and the second discrete three-dimensional body, the trench isolation structure comprising:
a first insulating layer (122), wherein the first insulating layer is a non-doped insulating layer comprising silicon and oxygen (thermal oxide of a Si substrate will result in Si and O [0074]);
a second insulating layer (124) directly on the first insulating layer, the second insulating layer comprising silicon and nitrogen (may be SiN [0075]);
and a dielectric fill material (126) directly laterally adjacent to the second insulating layer,
wherein the trench isolation structure has a concave uppermost surface extending from the first discrete three-dimensional body to the second discrete three-dimensional body (shown in figure), the concave uppermost surface and including the first insulating layer, the second insulating layer and the dielectric fill material (the etch shown in figure18I results in a changing slope of the sidewall. [0226,0227]).
(482)a gate electrode (GL) over a channel region of the first discrete three-dimensional body (F1), and over a channel region of the second discrete three-dimensional body (F2);
a first epitaxial source or drain (482) structure at an end of the first discrete three-dimensional body; a second epitaxial source or drain structure (482) at an end of the second discrete three- dimensional body, the second epitaxial source or drain structure laterally spaced apart from the first epitaxial source or drain structure (contacts 720 in figure 17A shows location of each source/drain);
Sung does not teach a dielectric spacer layer continuous from the first epitaxial source or drain structure to the second epitaxial source or drain structure, the dielectric spacer layer on the concave uppermost surface of the trench isolation structure.
However, Ching teaches in figure 19B, dielectric spacer layer (350) continuous from the first epitaxial source or drain structure to the second epitaxial source or drain structure, the dielectric spacer layer on the concave uppermost surface of the trench isolation structure (the STI 190).
It would have been obvious to one skilled in the art at the effective filing date of this application to add the dialectic 350 of Ching to the device of Sung because it allows planarization of the fill 360 to the gate level, Ching [0040]. One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 2,
Sung in view of Ching makes obvious the integrated circuit structure of claim 1, and in the combination, Sung teaches that the first insulating layer comprises the silicon and oxygen and has no other atomic species having an atomic concentration greater than 1E15 atoms per cubic centimeter. (It is grown from undoped silicon Sung [0074], so consists of Si and O. Sung does not teach doping either layer.)
As for claim 3,
Sung in view of Ching makes obvious the integrated circuit structure of claim 1, and in the suggested combination, Sung teaches that the first insulating layer has a thickness in the range of 0.5-2 nanometers. (10-100A, [0074]).
As for claim 4,
Sung in view of Ching makes obvious the integrated circuit structure of claim 1, and in the suggested combination, Sung teaches that the second insulating layer has a thickness in the range of 2-5 nanometers.(10-100A, [0075]).
As for claim 5,
Sung in view of Ching makes obvious the integrated circuit structure of claim 1, and in the suggested combination, Sung teaches that the dielectric fill material comprises silicon and oxygen.(FSG, USG, BPSG are silicon oxides [0075]).
As for claim 7,
Sung in view of Ching makes obvious the integrated circuit structure of claim 1, and in the suggested combination, Sung teaches that the gate electrode is over the dielectric fill material between the first discrete three-dimensional body and the second discrete three-dimensional body.(shown in figure 1B)
As for claim 8,
Sung teaches in figure 4d integrated circuit structure, comprising: a first discrete three-dimensional body(F1i, left center);
a second discrete three-dimensional body(F1i, right center);
a trench isolation structure (220) between the first discrete three-dimensional body and the second discrete three-dimensional body, the trench isolation structure comprising:
a first insulating layer (122) comprising silicon and oxygen and having no other atomic species having an atomic concentration greater than 1E15 atoms per cubic centimeter (thermal oxide of a Si substrate will result in Si and O [0074] It is grown from undoped silicon, so consists of Si and O. Sung does not teach doping either layer.);
a second insulating layer (124) comprising silicon and nitrogen (may be SiN [0075]) , the second insulating layer directly on the first insulating layer; and
a dielectric fill material (126) directly laterally adjacent to the second insulating layer,
wherein the trench isolation structure has a concave uppermost surface extending from the first discrete three-dimensional body to the second discrete three-dimensional body, the concave uppermost surface and including the first insulating layer, the second insulating layer and the dielectric fill material (the etch shown in figure18I results in a changing slope of the sidewall and exposing the ends of both liner layers. [0226,0227]).
a gate electrode (GL) over a channel region of the first discrete three-dimensional body (F1), and over a channel region of the second discrete three-dimensional body (F2);
a first epitaxial source or drain structure (482)at an end of the first discrete three-dimensional body; a second epitaxial source or drain structure at an end of the second discrete three- dimensional body, the second epitaxial source or drain structure laterally spaced apart from the first epitaxial source or drain structure contacts 720 in figure 17A shows location of each source/drain); and
Sung does not teach a dielectric spacer layer continuous from the first epitaxial source or drain structure to the second epitaxial source or drain structure, the dielectric spacer layer on the concave uppermost surface of the trench isolation structure.
However, Ching teaches in figure 19B, dielectric spacer layer (350) continuous from the first epitaxial source or drain structure to the second epitaxial source or drain structure, the dielectric spacer layer on the concave uppermost surface of the trench isolation structure (the STI 190).
It would have been obvious to one skilled in the art at the effective filing date of this application to add the dialectic 350 of Ching to the device of Sung because it allows planarization of the fill 360 to the gate level, Ching [0040]. One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 9,
Sung in view of Ching makes obvious the integrated circuit structure of claim 8, and in the suggested combination, Sung teaches the first insulating layer has a thickness in the range of 0.5-2 nanometers (10-100A, [0074]).
As for claim 10,
Sung in view of Ching makes obvious the integrated circuit structure of claim 8, and in the suggested combination, Sung teaches the second insulating layer has a thickness in the range of 2-5 nanometers .(10-100A, [0075])
As for claim 11,
Sung in view of Ching makes obvious the integrated circuit structure of claim 8, and in the suggested combination, Sung teaches that the dielectric fill material comprises silicon and oxygen.(FSG, USG, BPSG are silicon oxides [0075])
As for claim 12,
Sung in view of Ching makes obvious the integrated circuit structure of claim 8, and in the combination, Sung teaches that the gate electrode is over the dielectric fill material between the first discrete three-dimensional body and the second discrete three-dimensional body. (shown in figure 1B)
As for claim 13,
Sung teaches a computing device, comprising:
a board (motherboard [0299]);
and a component (memory module 1400) coupled to the board [0299], the component including ([0298]) an integrated circuit structure, comprising:
a first discrete three-dimensional body (F1i, left center) comprising silicon ([0067]);
a second discrete three-dimensional body (F1i, right center) comprising silicon ([0067]);
a trench isolation structure (120 between the first discrete three-dimensional body and the second discrete three-dimensional body, the trench isolation structure comprising:
a first insulating layer (122), wherein the first insulating layer is a non- doped insulating layer comprising silicon and oxygen (thermal oxide of a Si substrate will result in Si and O [0074] It is grown from undoped silicon, so consists of only Si and O. Sung does not teach doping either layer.);
a second insulating layer (124) directly on the first insulating layer, the second insulating layer comprising silicon and nitrogen may be SiN [0075]);
and a dielectric fill material (126) directly laterally adjacent to the second insulating layer, wherein the trench isolation structure has a concave uppermost surface extending from the first discrete three-dimensional body to the second discrete three-dimensional body, the concave uppermost surface and including the first insulating layer, the second insulating layer and the dielectric fill material (the etch shown in figure18I results in a changing slope of the sidewall and exposes the ends of the first and second dielectric liners. [0226,0227]).
a gate electrode (GL) over a channel region of the first discrete three-dimensional body (F1), and over a channel region of the second discrete three-dimensional body (F2);
a first epitaxial source or drain structure (482) at an end of the first discrete three- dimensional body;
a second epitaxial source or drain structure (482) at an end of the second discrete three- dimensional body, the second epitaxial source or drain structure laterally spaced apart from the first epitaxial source or drain structure (contacts 720 in figure 17A shows location of each source/drain);
Sung does not teach a dielectric spacer layer continuous from the first epitaxial source or drain structure to the second epitaxial source or drain structure, the dielectric spacer layer on the concave uppermost surface of the trench isolation structure.
However, Ching teaches in figure 19B, dielectric spacer layer (350) continuous from the first epitaxial source or drain structure to the second epitaxial source or drain structure, the dielectric spacer layer on the concave uppermost surface of the trench isolation structure (the STI 190).
It would have been obvious to one skilled in the art at the effective filing date of this application to add the dialectic 350 of Ching to the device of Sung because it allows planarization of the fill 360 to the gate level, Ching [0040]. One skilled in the art would have combined these elements with a reasonable expectation of success.
As for claim 14,
Sung in view of Ching makes obvious the computing device of claim 13, and in the combination, Sung teaches a memory coupled to the board ([0297]).
As for claim 15,
Sung in view of Ching makes obvious the computing device of claim 13, and in the suggested combination, Sung teaches: a communication chip coupled to the board. (controller 1502 [0301])
As for claim 18,
Sung teaches the computing device of claim 13, and in the suggested combination, Sung teaches a display coupled to the board. (figure 22).
As for claim 19,
Sung in view of Ching makes obvious the computing device of claim 13, and in the combination, Sung teaches the component is a packaged integrated circuit die. [0295]
As for claim 20,
Sung in view of Ching makes obvious the e computing device of claim 13, and in the suggested combination, Sung teaches the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor. (may be a DDI [0300] or a controller [0301]).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Sung in view of Ching and in further view of Feshali et al. (U.S. 2014/0008750).
As for claim 16,
Sung in view of Ching makes obvious the computing device of claim 13, but does not teach a battery coupled to the board.
However, Feshali teaches a batter on a motherboard. [0049].
It would have been obvious to one skilled in the art at the effective filing date of this application to add the battery of Feshali to the device of Sung so that power can be maintained to components on the board when not external power is available to maintain data or clock functionality. One skilled in the art would have combined these elements with a reasonable expectation of success.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Sung in view of Ching in further view of Okabe (U.S. 2006/02276158).
As for claim 17,
Sung in view of Ching makes obvious the computing device of claim 13, but does not teach a camera coupled to the board.
However, Okabe teaches adding a camera to the device ([0005], figure 15).
It would have been obvious to one skilled in the art at the effective filing date of this application to add a camera to the device of Sung to allow the device to capture images. One skilled in the art would have combined these elements with a reasonable expectation of success.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN A BODNAR whose telephone number is (571)272-4660. The examiner can normally be reached M-Th and every other Friday 7:30-5:30 Central time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached on 571-270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JOHN A BODNAR/ Primary Examiner, Art Unit 2893
Prosecution Insights