DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election, without traverse, of Group I: claims 1-8, in the “Response to Election / Restrict. ion Filed - 08/06/2025”, is acknowledged. Applicant amended Claims 1, 6-7 and 9 in “Claims - 07/29/2025”.
This office action considers claims 1-14 are thus pending for prosecution, of which, non-elected claims 9-14 are withdrawn, and elected claims 1-8 are examined on their merits.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (1; Fig 1; [0025]) = (element 1; Figure No. 1; Paragraph No. [0025]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 1-8 are rejected under 35 U.S.C. 102(a) (2) as being anticipated by KIM; Changhun et al. (US 20230387053 A1) hereinafter Kim.
1. Kim teaches a semiconductor memory device (1; Fig 1; [0025]) comprising (See the entire document Figs 1-22, specifically Figs 10-12 [0086+], and as cited below):
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Kim Figure 11 and Figure 12
a first peripheral area (PE5) and a second peripheral area (394);
a lower substrate (210) located in the first peripheral area (PED) and the second peripheral area (393);
a peripheral circuit component (220a,220c) located on the lower substrate (201);
a lower bonding layer (LMP1, 271C), located on the peripheral circuit component, the lower bonding layer including a lower capacitor structure (VC1-VC4; Fig 11) in the second peripheral area;
an upper bonding layer (UMP1, 372C,392), bonded to the lower bonding layer, the upper bonding laver including an upper capacitor structure (VC5-VC8);
a plurality of cells (CELL; [0040]) and a dummy insulating layer (352; [0069]) that are located on the upper bonding layer (UMP1);
a cell area (330) and a dummy area (PE5); and
an upper substrate (310) located in the cell area (330) and the dummy area, the upper substrate being located on the plurality of cells and the dummy insulating layer,
wherein the upper capacitor structure (VC4-VC8; Figs 10-12) is located in the dummy area and is coupled to the lower capacitor structure (VC1-VC3).
2. The semiconductor memory device according to claim 1, Kim further teaches, wherein ([0142]) the plurality of cells (330) comprise a plurality of insulating layers (315) and a plurality of gate layers (331-338) that are alternately stacked (Figs 5,12).
3. (Original) The semiconductor memory device according to claim 2, Kim further teaches, wherein ([0064,0067,0142]) the plurality of gate layers include a source selection line (320), a word line (330), and a drain selection line (338), wherein the source selection line (320) is located in an uppermost portion (Fig 12), among the plurality of gate layers (330), and wherein the drain selection line (338) is located in a lowermost portion, among the plurality of gate layers (330).
4. (Original) The semiconductor memory device according to claim 1, Kim further teaches, wherein the lower capacitor structure (VC1-VC4) comprises:
lower conductive patterns (MC1-MC3; Fig 7,11-12; [0072]) arranged to be parallel to each other; and
lower insulating patterns (215; [0046. 0139]) located between the lower conductive patterns (MC1-MC3).
5. The semiconductor memory device according to claim 1, Kim further teaches, wherein the upper capacitor structure (V5-V8) comprises:
upper conductive patterns (DCP1-DCP6: figs 11-12,5) arranged to be parallel to each other; and
upper insulating patterns (315) located between the upper conductive patterns.
6. The semiconductor memory device according to claim 4, Kim further teaches, wherein the lower conductive patterns (MC1-MC3; Fig 7,11-12; [0072]) vertically penetrate the lower bonding layer (LMP).
7. The semiconductor memory device according to claim-claim 5, Kim further teaches, wherein the upper conductive patterns (DCP1-DCP3)vertically penetrate the upper bonding layer (UMP1-UMP3).
8. The semiconductor memory device according to claim 1, Kim further teaches,
wherein the lower bonding layer (LMP1-LMP3) includes a lower bonding structure ([0074]) in the first peripheral area (PERI),
wherein the upper bonding layer (UMP1-UMP3) includes an upper bonding structure in the cell area (CELL; Fig 11), and
wherein the lower bonding structure and the upper bonding structure are coupled to each other (Fig 11).
Conclusion
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/MOAZZAM HOSSAIN/Primary Examiner, Art Unit 2898
August 14, 2025