DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 02/10/2026 have been fully considered but are moot in view of the new grounds of rejection in light of Applicant’s claim amendments or indication of allowable subject matter as detailed below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 15 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 15 depends on claim 14 but claim 14 has been cancelled. For purposes of examination, claim 15 is interpreted as depending on claim 13.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1,6,11,26 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2023/0144304 A1 to Chang et al., “Chang”, in view of U.S. Patent Number 5,864,159 to Takahashi, “Takahashi”.
Regarding claim 1, Chang discloses a semiconductor device (e.g. FIG. 1) comprising a transistor, the transistor comprising a plurality of macro cells, the plurality of macro cells comprising a first macro cell (e.g. one of TRG1) and a second macro cell (e.g. one of TRG2), each of the first and the second macro cells comprising:
a plurality of trenches (102) formed in a first main surface of a semiconductor substrate (100, ¶ [0032]), the trenches patterning the semiconductor substrate into mesas (as pictured, ¶ [0034]), wherein the plurality of trenches comprises a conductive trench (i.e. gate structure, ¶ [0037],[0038]), a conductive material (“conductive layer”) arranged in the conductive trench being electrically connected to a terminal (e.g. gate through gate pad 130, ¶ [0039]), wherein a majority of all the trenches of the first macro cell (TRG1) exclusively run in a first direction (D2), wherein a majority of all the trenches of the second macro cell (TRG2) exclusively run in a second direction (D1) different from the first direction, wherein at least one first macro cell is arranged adjacent to at least one second macro cell.
Chang fails to clearly teach wherein the trenches in the first macro cell and the trenches in the second macro cell comprise a source trench, wherein a conductive material in the source trench is electrically connected to a source terminal and insulated from adjacent semiconductor material of the semiconductor substrate.
Takahashi teaches modifying a conventional semiconductor device (FIG. 2,3) with a plurality of gate trenches (45) by adding (FIG. 22,23) a source trench (55, referred to as a “dummy trench”, column 19 line 62 to column 20 line 31), wherein the conductive material (polysilicon 47) in the source trench is electrically connected to a source terminal (source electrode 49) and insulated (by dielectric 46, column 20 lines 15-19,41-42) from adjacent semiconductor material of the semiconductor substrate.
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Chang by adding source trenches in parallel with the gate trenches as taught by Takahashi in order to increase the breakdown voltage (Takahashi column 20 line 31 to column 21 line 38).
Regarding claim 6, Chang in view of Takahashi yields the semiconductor device of claim 1, and Chang further discloses wherein the terminal (130) is a gate terminal (¶ [0039]).
Regarding claim 11, Chang in view of Takahashi yields the semiconductor device of claim 1, and Chang further discloses wherein the first (TRG1) and the second macro cells (TRG2) are arranged to form a checkerboard pattern (alternating as pictured).
Regarding claim 26, Chang in view of Takahashi yields the semiconductor device of claim 1, and Takahashi further teaches (FIG. 23) wherein a source region (N+ regions 44) is absent from the mesa directly adjacent to the source trench (55).
Claims 1-6,8-9,25 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2018/0005959 A1 to Wang et al., “Wang”, in view of U.S. Patent Application Publication Number 2023/0197786 A1 to Mori et al., “Mori”.
Regarding claim 1, Wang discloses a semiconductor device (e.g. FIG. 3C,4B) comprising a transistor, the transistor comprising a plurality of macro cells (regions B and A, from FIG. 3A,3B ¶ [0021]-[0025]), the plurality of macro cells comprising a first macro cell (B) and a second macro cell (A), each of the first and the second macro cells comprising:
a plurality of trenches (112a and 112b, ¶ [0021], alternately FIG. 8 trenches filled with 161a, ¶ [0031]) formed in a first main surface of a semiconductor substrate, the trenches patterning the semiconductor substrate into mesas (as pictured), wherein the plurality of trenches comprises a conductive trench (“gate”), a conductive material (FIG. 4B material 132, ¶ [0025],[0026]) arranged in the conductive trench being electrically connected to a terminal (“gate”), wherein a majority of all the trenches of the first macro cell (B) exclusively run in a first direction (up-down axis), wherein a majority of all the trenches of the second macro cell (A) exclusively run in a second direction (left-right axis) different from the first direction, wherein at least one first macro cell (B) is arranged adjacent to at least one second macro cell (A).
Wang fails to clearly teach wherein the trenches in the first macro cell and the trenches in the second macro cell comprise a source trench, wherein a conductive material in the source trench is electrically connected to a source terminal and insulated from adjacent semiconductor material of the semiconductor substrate.
Mori teaches (e.g. FIGs. 7-8) wherein trenches in a macro cell comprise a source trench (41, ¶ [0119]-[0133], between trench gate structures 31 ¶ [0104]-[0112]), wherein (e.g. FIG. 9) a conductive material (44, ¶ [0132]) in the source trench (41) is electrically connected to a source terminal (“source potential is given to the first trench source structures 41” ¶ [0119]) and insulated (by 43, ¶ [0132]) from adjacent semiconductor material of the semiconductor substrate.
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Wang by adding source trenches between the gate trenches as taught by Mori in order to achieve improved reliability (Mori ¶ [0004],[0463],[0618]). Alternately, it would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Mori with the macro cells running in different directions as taught by Wang in order to reduce wafer warpage (Wang ¶ [0001]-[0002],[0020]).
Regarding claim 2, Wang in view of Mori yields the semiconductor device of claim 1, and Wang further discloses wherein the first macro cell (B) further comprises a first connection trench (112b-1, ¶ [0024],[0026]) running in the first direction (up-down axis), a conductive material (also material 132) being arranged in the first connection trench, and wherein the conductive material (1032) of the first connection trench is electrically connected to a plurality of conductive trenches of the second macro cell (gate, formed from same material).
Regarding claim 3, Wang in view of Mori yields the semiconductor device of claim 1, and Wang further discloses (FIG. 7A,7B,8B) an insulating layer (160, ¶ [0035],[0036]) over the semiconductor substrate (105); and
a first contact groove (FIG. 7A contacts 162 to FIG. 8B contacts 161a on left, ¶ [0032],[0033]) formed in the insulating layer (160) and contacting a mesa of the first macro cell, a lateral extension of the first contact groove in the first direction (Y axis) being larger than a lateral extension of the first contact groove (filled with 132) in the second direction (X axis).
Regarding claim 4, Wang in view of Mori yields the semiconductor device of claim 3, and Wang further discloses a second contact groove (FIG. 7A contacts 162 to FIG. 8B contacts 161a on right) formed in the insulating layer (160) and contacting a mesa of the second macro cell, a lateral extension of the second contact groove in the second direction (X axis) being larger than a lateral extension of the second contact groove in the first direction (Y axis).
Regarding claim 5, Wang in view of Mori yields the semiconductor device of claim 3, and Wang further discloses wherein the mesa contacted by the first contact groove comprises a doped semiconductor portion (body region 115, ¶ [0034] or alternately source region 16, ¶ [0036]) in contact with the first contact groove.
Regarding claim 6, Wang in view of Mori yields the semiconductor device of claim 1, and Wang further discloses wherein the terminal is a gate terminal (132 is a gate ¶ [0025]).
Regarding claim 8, Wang in view of Mori yields the semiconductor device of claim 1, and Wang in further teaches wherein the trenches in the first macro cell and the trenches in the second macro cell further comprise a gate trench (conductive material 132 is connected to “gate”), and wherein a conductive material (132) in the gate trench is electrically connected to a gate terminal (“gate”) and insulated (by 131, ¶ [0025]) from adjacent semiconductor material of the semiconductor substrate.
Regarding claim 9, Wang in view of Mori yields the semiconductor device of claim 1, and Wang further discloses wherein the plurality of mesas comprise a dummy mesa (region between active mesas and terminal trench 120, ¶ [0035],[0036]) that is disconnected from a terminal (“dummy gate”).
Regarding claim 25, Wang in view of Mori yields the semiconductor device of claim 1, and Mori further teaches wherein a source region (24, ¶ [0102]) is present in the mesa directly adjacent to the source trench (41).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2023/0144304 A1 to Chang et al., “Chang”, in view of U.S. Patent Number 5,864,159 to Takahashi, “Takahashi”, further in view of U.S. Patent Application Publication Number 2024/0014275 A1 to Sanda, “Sanda”.
Regarding claim 10, although Chang in view of Takahashi yields the semiconductor device of claim 1, Chang fails to clearly anticipate wherein a number of trenches of the first macro cell is identical with a same number of trenches of the second macro cell.
Sanda exemplifies (e.g. Fig. 6) wherein a number of trenches (S1_1, S1_2, S1_3, S1_4) of a first macro cell (S1, ¶ [0014]) is identical with a same number of trenches (S2_1, S2_2, S2_3, S2_4) of a second macro cell (S2).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Chang in view of Takahashi with an equal number of trenches for the first and second macro cells as taught by Sanda in the process of selecting a number of gate trenches in order to allow for mounting the semiconductor device (Sanda ¶ [0019]) and since it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969), wherein in the instant case the number of trenches determines and is determined by the dimensions and operating characteristics of the specific macro cell making it a result effective variable, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), and MPEP 2144.05 Obviousness of Ranges II. OPTIMIZATION OF RANGES A. Optimization Within Prior Art Conditions or Through Routine Experimentation B. Only Result-Effective Variables Can Be Optimized.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication Number 2023/0144304 A1 to Chang et al., “Chang”, in view of U.S. Patent Number 5,864,159 to Takahashi, “Takahashi”, further in view of U.S. Patent Application Publication Number 2014/0175541 A1 to Matri` et al, “Matri`”.
Regarding claim 12, Chang in view of Takahashi yields the semiconductor device of claim 11, and Chang further discloses wherein the first (TRG1) and the second (TRG2) macro cells are arranged in columns (three as pictured) and rows (two as pictured), an array of macro cells comprising an odd number of columns (3 is odd) of macro cells and an odd number of rows of macro cells.
Chang fails to include in the picture an odd number of rows.
Matri` teaches (e.g. FIG. 2A) forming macro cells (210ah, 210ac, 212ah, 121av) in any number of rows and columns (as pictured, ¶ [0040],[0041],[0043]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Chang in view of Takahashi with an odd number of rows and columns as generally taught by Matri` in order to achieve a uniform distribution (Matri` ¶ [0043]) for example in order to evenly distribute warping of the wafer (Matri` ¶ [0030],[0033],[0036]).
Allowable Subject Matter
Claims 13,17-19 are allowed.
Claim 15 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Although prior art e.g. Wang teaches a device with macro cells having gate trenches and source trenches in different directions with a connection trench for the gate trenches as discussed above, prior art fails to reasonably teach wherein the trenches including the connection trench are connected to a source terminal as claimed in amended claim 13. Claim 17 is allowable insofar as it depends upon and includes all of the limitations of amended claim 13. Claim 15 if corrected for the pending indefiniteness issue would also be allowable insofar as it depends upon and includes all of the limitations of amended claim 13.
Additionally, although alignment marks are known in the art, prior art fails to reasonably teach or suggest a passivation layer at least partly above a metallization layer at a frontside of the semiconductor device, the passivation layer comprising marker portions indicating the orientation of at last/least one of the macro cells together with all of the limitations of claim 18 as claimed. Claim 19 is allowable insofar as it depends upon and includes all of the limitations of allowable claim 18.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC A WARD whose telephone number is (571)270-3406. The examiner can normally be reached M-F 10-6 ET.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571)272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Eric A. Ward/ Primary Examiner, Art Unit 2891