DETAILED ACTION
This Office action is in response to a Request for Continued Examination filed on 05/07/2026. Claims 1-7, 9-20, and 22 are presented for examination consideration.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 05/07/2026 has been entered.
Drawings
Applicant’s Drawing Amendments (filed on 03/18/2026) are persuasive in the cited drawing objections from the last office action (mailed on 02/12/2026) due to the following:
Providing Amended Drawings to properly designate “item 165d” in amended Fig. 1.
Providing Amended Drawings to properly designate “item 153e” in amended Fig. 1.
The drawing objections cited in the last office action are withdrawn.
Response to RCE Amendments
Applicant's AF/RCE Claim Amendments (filed on 03/18/2026) with respect to the 112(b) rejection of independent claim 15 that was cited in the office action (mailed on 02/12/2026) is persuasive due to amending the claim to resolve the indefinite claim that is failing to particularly point out and distinctly claim the subject matter. The claim amended the following structural limitations:
“FROM “and the plane is devoid of conductive features except for the second subject of the conductive features” TO “and the plane is devoid of metal except for the at least one loading pad”.
The 112(b) rejection of independent claim 15 and the claims depended on claim 15 are withdrawn.
Applicant's AF/RCE Claim Amendments (filed on 03/18/2026) with respect to the 112(a) rejection of independent claim 15 that was cited in the office action (mailed on 02/12/2026) is persuasive due to comply with the written description requirement. The claim amended the following structural limitations:
“FROM “and the plane is devoid of conductive features except for the second subject of the conductive features” TO “and the plane is devoid of metal except for the at least one loading pad”.
The 112(a) rejection of independent claim 15 and the claims depended on claim 15 are withdrawn.
Applicant's AF/RCE Claim Amendments (filed on 03/18/2026) with respect to the 112(d) rejection of claim 21 that was cited in the office action (mailed on 02/12/2026) is persuasive due to cancelling the claim.
The 112(d) rejection of claim 21 is withdrawn.
Applicant’s AF/RCE Claim Amendments (filed 03/18/2026) with respect to amended method independent claim 20 has been fully considered and is persuasive due to amending the claim to further define the following structural limitations in the method:
“Removing a portion of the first conductive layer to form a loading pad such that the surface of the first dielectric layer is devoid of metal except for loading pad”.
The 35 U.S.C. 103/102 rejection of claim 20 that was cited in the last office action (mailed 02/12/2026) has been withdrawn.
Nevertheless, Applicant's RCE Amendments are moot in view of the new ground(s) of rejection in the RCE.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-7, 9-19, and 22 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 1 recites the limitation phrase “devoid of metal” in the limitation “wherein the first plane is devoid of metal except for the at least one first loading pad”, is confusing. Specifically, the cited limitation is CONTRADICTING the STRUCTURES of Fig. 1, where in Fig. 1, the “via 157” may include “conductive materials 160”, where suitable conductive materials may be copper, solder, aluminum, or gold (indicated in ¶[0024]). Given the structure of the conductive “via 157”, then HOW can the “first plane” (of “planes 164, 166, 168, 170, 172”) in the cited limitation be “devoid of metal” EXCEPT “first loading pad” when the “via 157” is formed part of the “planes 164, 166, 168, 170, 172”. Accordingly, the cited limitation will be examined that may include ANY “via structure(s)” as part of the plane in prior arts reference to conform with Fig. 1.
Claims 2-7, 9-14, and 22 are rejected since the base independent claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph.
Claim 15 recites the limitation phrase “devoid of metal” in the limitation “and the plane is devoid of metal except for the at least one loading pad”, is confusing. Specifically, the cited limitation is CONTRADICTING the STRUCTURES of Fig. 1, where in Fig. 1, the “via 157” may include “conductive materials 160”, where suitable conductive materials may be copper, solder, aluminum, or gold (indicated in ¶[0024]). Given the structure of the conductive “via 157”, then HOW can the “plane” (of “planes 164, 166, 168, 170, 172”) in the cited limitation be “devoid of metal” EXCEPT “loading pad” when the “via 157” is formed part of the “planes 164, 166, 168, 170, 172”. Accordingly, the cited limitation will be examined that may include ANY “via structure(s)” as part of the plane in prior arts reference to conform with Fig. 1.
Claims 16-19 are rejected since the base independent claim 15 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph.
Examiner’s Note Concerning Using Foreign Priority Date in a US PgPub Reference used in 102(a)(2) Rejection
Under (AIA ), a foreign priority date can be used as the effective prior art date for a US Patent or US Patent Application reference under 35 U.S.C. § 102(a)(2), which is a significant change from pre-AIA law under the Hilmer doctrine. See MPEP § 2154.01(b).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 9, 10, 11, 12, 13, and 14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chen et al. (US20230290723A1 and Chen hereinafter).
Regarding claim 1, Chen discloses a printed circuit board (PCB) (item 100 of Fig. 1B and ¶[0041] shows and indicates PCB 100 {semiconductor structure 100}), comprising: a first dielectric layer (item D2 of Fig. 1B and ¶[0041] shows and indicates first dielectric layer D2 {plurality of insulating layers D2, D3 and D4}); a second dielectric layer formed adjacent to the first dielectric layer (item D3 of Fig. 1B and ¶[0041] shows and indicates second dielectric layer D3 {plurality of insulating layers D2, D3 and D4} formed adjacent to first dielectric layer D2); a first plane defined by an interface between the first and the second dielectric layers (Fig. 1B and ¶[0041] shows and indicates first plane D2-facing-D3 {plane defined as the surface of insulating layer D2 facing insulating layer D3} defined by interface between first dielectric layer D2 and second dielectric layer D3); and at least one first loading pad formed on the first plane, wherein the first plane is devoid of metal except for the at least one first loading pad (item 115 of Fig. 1B and ¶[0042] shows and indicates first loading pad 115 formed on first plane D2-facing-D3; where first plane D2-facing-D3 is devoid of metal except for first loading pad 115).
Regarding claim 9, Chen discloses a PCB, further comprising: a third dielectric layer vertically adjacent the second dielectric layer; and a conductive layer extending between the second and third dielectric layers (items D4, M4 of Fig. 1B and ¶[0041] shows and indicates PCB 100 is further comprised of third dielectric layer D4 {plurality of insulating layers D2, D3 and D4} vertically adjacent second dielectric layer D3; where conductive layer M4 is extending between second dielectric layer D3 and third dielectric layer D4).
Regarding claim 10, Chen discloses a PCB, further comprising at least one second loading pad formed on the conductive layer (item 116 of Fig. 1B and ¶[0042] shows and indicates PCB 100 is further comprised of second loading pad 116 formed on conductive layer M4 by being embedded within conductive layer M4).
Regarding claim 11, Chen discloses a PCB, wherein the at least one second loading pad is vertically aligned with the at least one first loading pad (Fig. 1B and ¶[0042] shows where second loading pad 116 is vertically aligned with first loading pad 115).
Regarding claim 12, Chen discloses a PCB, wherein the at least one second loading pad is formed from aluminum foil or copper foil (Fig. 1B and ¶[0041-0042] is interpreted to indicate where second loading pad 116 is formed from copper/aluminum foil, since conductive layer M4 can be made of conductive materials, such as copper/aluminum).
Regarding claim 13, Chen discloses a PCB, further comprising a via extending through the at least one first loading pad, the at least one second loading pad, the first dielectric layer, the second dielectric layer, and the third dielectric layer (items 110, 120 of Fig. 1B and ¶[0038-0039 & 0078-0079] shows where PCB 100 is further comprised of vias 110 & 120 {conductive via structures 110 and 120} extending through first loading pad 115, second loading pad 116, first dielectric layer D2, second dielectric layer D3, and third dielectric layer D4).
Regarding claim 14, Chen discloses a PCB, wherein the via is a signal via or a ground via (Fig. 1B and ¶[0041-0042 & 0078-0079] shows and indicates where vias 110 & 120 are signal vias).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2, 3, 4, and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Chen, as detailed in the rejection of claim 10 above, in view of Lizalde Moreno et al. (US20190116668A1 and Moreno hereinafter).
Regarding claim 2, Chen discloses a PCB, wherein at least one second loading pad and conductive layer (item 116 of Fig. 1B and ¶[0042] shows and indicates where second loading pad 116 and conductive layer M4).
However, Chen does not disclose wherein an antipad separates the at least one second loading pad from the conductive layer.
Moreno discloses wherein an antipad separates the at least one second loading pad from the conductive layer (items 420b, 410b, 416 of Fig. 4A and ¶[0040 & 0054] shows and indicates where an antipad 420b {second barrel void/anti-pad 420b} separates second loading pad 410b {via pad 410b} from the conductive layer 416-top-layer {top metal layer 416}).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein an antipad separates the at least one second loading pad from the conductive layer into the structure of Chen. One would have been motivated in the PBC of Chen and have the antipad separates the at least one second loading pad from the conductive layer, in order to design a board where void/anti-pad can optimized potential or/and designated impedance targets, as implied by Moreno in ¶[0040], in the PBC of Chen.
Regarding claim 3, modified Chen discloses a PCB, wherein at least one second loading pad and conductive layer (Moreno: Fig. 4A and ¶[0040 & 0054] shows and indicates where an antipad 420b is a void in conductive layer 416-top-layer surrounding second loading pad 410b).
Regarding claim 4, modified Chen discloses a PCB, wherein the antipad is a non-conductive material laterally separating the at least one second loading pad from the conductive layer (Moreno: Fig. 4A and ¶[0040 & 0054] shows and indicates where an antipad 420b is a non-conductive material laterally separating second loading pad 410b from conductive layer 416-top-layer).
Regarding claim 6, modified Chen discloses a PCB, wherein the conductive layer is a signal plane (Moreno: items 402a, 402b of Fig. 4A and ¶[0053] shows and indicates where conductive layer 416-top-layer is a signal plane, since stacked vias 402a and 402b can be differential pair signaling).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Moreno, as detailed in the rejection of claim 2 above, and in further view of Dellis et al. (US20100270644A1 and Dellis hereinafter).
Regarding claim 5, modified Chen discloses a PCB, wherein the conductive layer (Moreno: Fig. 4A and ¶[0040 & 0054] shows and indicates where conductive layer 416-top-layer).
However, Chen and Moreno do not disclose wherein the conductive layer comprises a layer of patterned metal.
Dellis discloses wherein the conductive layer comprises a layer of patterned metal (item 211 of Fig. 3A and ¶[0058-0059] shows and indicates where conductive layer 211 {patterned metal layer 211} comprises a layer of patterned metal).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the conductive layer comprises a layer of patterned metal into the structure of modified Chen. One would have been motivated in the PBC of modified Chen and have the conductive layer be comprised of a layer of patterned metal, in order to design a board where a conductive layer can be pattern to segregate signaling paths from grounding paths, as infer by Dellis in ¶[0058], in the PBC of modified Chen.
Claims 15, 16, 17, and 18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chen et al. (US20230290723A1 and Chen hereinafter).
Regarding claim 15, Chen discloses a PCB (item 100 of Fig. 1B and ¶[0041] shows and indicates PCB 100 {semiconductor structure 100}), comprising: a stack of multiple dielectric layers (items D2, D3, D4 of Fig. 1B and ¶[0041] shows and indicates the stack of multiple dielectric layers D2-D4 {plurality of insulating layers D2, D3 and D4}); conductive features formed at an interface between each of the dielectric layers, wherein at least a first subset of the conductive features are formed on a conductive plane extending between adjacent dielectric layers (items M3, M4, M5, 125, 126, 128 of Fig. 1B and ¶[0041-0042] shows and indicates conductive features M3-M5 {conductive layers M3, M4 and M5} formed at the interface between each of the respective dielectric layers D2-D4; where first subset 125_126_128 {conductive pads 125, 126 and 128} of conductive features M3-M5 are formed on the respective conductive planes D2-facing-D3 & D3-facing-D4 & D4-top-surface {planes defined by the following: plane D2-facing-D3 defined as the surface of insulating layer D2 facing insulating layer D3; plane D3-facing-D4 defined as the surface of insulating layer D3 facing insulating layer D4;and plane D4-top-surface defined as the top surface of insulating layer D4} between adjacent respective dielectric layers D2-D4), least a second subset of the conductive features comprising at least one loading pad are formed on a plane defined by an interface between adjacent dielectric layers in direct contact, and the plane is devoid of metal except for the at least one loading pad (items 115, 116, 118 of Fig. 1B and ¶[0041-0042] shows and indicates second subset 115_116_118 {conductive pads 115, 116 and 118} of the respective conductive features M3-M5 comprising of the respective loading pads 115 OR 116 OR 118 are formed on the respective conductive planes D2-facing-D3 & D3-facing-D4 & D4-top-surface defined by the interface between adjacent respective dielectric layers D2-D4 in direct contact; where the respective conductive planes D2-facing-D3 & D3-facing-D4 & D4-top-surface is devoid of metal except for of the respective loading pads 115 OR 116 OR 118); and a via formed through the conductive features and the stack of multiple dielectric layers (items 110, 120 of Fig. 1B and ¶[0038-0042] shows and indicates vias 110 & 120 {conductive via structures 110 and 120} formed through conductive features M3-M5 and the stack of multiple dielectric layers D2-D4).
Regarding claim 16, Chen discloses a PCB, wherein the via is a signal via or a ground via (Fig. 1B and ¶[0041-0042 & 0078-0079] shows and indicates where vias 110 & 120 are signal vias).
Regarding claim 17, Chen discloses a PCB, wherein the conductive features include one or more loading pads (Fig. 1B and ¶[0041-0042] shows and indicates where conductive features M3-M5 includes loading pads 115 & 116 & 118).
Regarding claim 18, Chen discloses a PCB, wherein the conductive plane is a signal plane (Fig. 1B and ¶[0041-0042 & 0078-0079] shows and indicates that since vias 110 & 120 are signal vias, then conductive planes D2-facing-D3 & D3-facing-D4 & D4-top-surface are signal planes formed within the respective conductive features M3-M5, enclosed within the conductive via structures).
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Chen, as detailed in the rejection of claim 15 above, in view of Moreno.
Regarding claim 19, Chen discloses a PCB, wherein first subset of conductive features (item 116 of Fig. 1B and ¶[0041-0042] shows and indicates where first subset 125_126_128 of conductive features M3-M5).
However, Chen does not disclose further comprising an anti-pad circumscribed around the first subset of conductive feature.
Moreno discloses further comprising an anti-pad circumscribed around the first subset of conductive feature (items 420b, 410b, 416 of Fig. 4A and ¶[0040 & 0054] shows and indicates where an antipad 420b {second barrel void/anti-pad 420b} circumscribed around the first subset 410b {via pad 410b} of conductive feature 416-top-layer {top metal layer 416}; therefore the PCB of Chen will have an anti-pad that is circumscribed around each of the first subset of conductive features by incorporating the anti-pad structure of Moreno).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate further comprising an anti-pad circumscribed around the first subset of conductive feature into the structure of Chen. One would have been motivated in the PBC of Chen and have the anti-pad be circumscribed around the first subset of conductive feature, in order to design a board where void/anti-pad can optimized potential or/and designated impedance targets, as implied by Moreno in ¶[0040], in the PBC of Chen.
Allowable Subject Matter
Claim 20 is allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding independent claim 1, the prior art taken either singularity or in combination fails to anticipate or fairly suggest the limitations of the independent claim, in such a manner that a rejection under 35 U.S.C. 102 or 103 would be improper. The prior art fails to teach a combination of limitations of a method for forming a PCB, comprising: …removing at least a portion of the first conductive layer to form at least one loading pad such that the surface of the first dielectric layer is devoid of metal except for the at least one loading pad…, as recited in combination in independent claim 20. After careful review of the specification and the claim in the application and a search of the prior art, considering the claim as a whole, the aforementioned recited limitations in combination in independent claim 20, it is believed to render the claim individually patentable over the prior art of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUILLERMO J EGOAVIL whose telephone number is (571)270-1325. The examiner can normally be reached Mon-Fri 8:00-5:00.
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/GUILLERMO J EGOAVIL/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
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