DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1/5/2026 was filed after the mailing date of the non-final rejection on 12/11/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Status
Previous action: claims 1 through 7, 9 through 16, 18, 19, 21, 32, and 33 are rejected
Present action: claims 1 through 7, 9 through 12, 14, 15, 16, 18, 19, 21, 32, and 33 are rejected
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “a plurality if test structures on the device region” as stated in claim 33 line 2 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 33 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 33 recites “the test structure is comprised in a plurality of test structures on the device region” in lines 1 and 2. However, the specification does not teach this element. Rather, as is illustrated in figures 1 and 4, a plurality of test structures are located in the edge region. It is unclear whether the applicant is referring to test structures or some other component. For the purpose of examination, the examiner will assume that the plurality of test structures are located in the edge region in order to accord with the figures and the elements of claim 31.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and struck through claim limitations indicate limitations that are not explicitly disclosed in the primary reference, but disclosed in the secondary reference(s), case law, or interpretation.
Claim(s) 1, 2, 7, and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2021/0175133) in view of Naruta (US 2009/0001368)
Regarding claim 1.
Choi teaches:
A semiconductor device comprising: a semiconductor substrate (fig 11:21; [para 0068]) including comprising a device region (fig 11:CH; [para 0033]) and an edge region (fig 11:SL11,SL12; [para 0034]);
a semiconductor component (fig 11:MC; [para 0038])on the device region (fig 11:CH; [para 0033]);
a structure (fig 11:41; [para 0042]) on the edge region (fig 11:SL12; [para 0034]), the structure (fig 11:41; [para 0042]) comprising a top surface and a side surface (fig 11);
an insulating layer (fig 11:31; [para 0036]) surrounding the semiconductor component (fig 11:MC; [para 0038]) and the structure (fig 11:41; [para 0042]);
and a pad (fig 11:64; [para 0048]) on the semiconductor component (fig 11:MC; [para 0038]), wherein the top surface and the side surface of the structure (fig 11:41; [para 0042]) are is surrounded by the insulating layer (fig 11:31; [para 0036]) and are not exposed at a top surface and a side surface of the insulating layer (fig 11:31; [para 0036]) , and wherein the structure (fig 11:41; [para 0042]) is electrically insulated from the semiconductor component (fig 11:MC; [para 0038]).
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Choi does not teach that the structure is metal and floating.
Naruta teaches:
a metal structure (fig 2a:28,29; [para 0025]), comprising a top surface and a side surface;
the metal structure (fig 2a:28,29; [para 0025]) is electrically floating ([para 0025])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the structure of metal because it is highly conductive enabling conduction of voltage, further by forming a floating structure it can be used to evaluate the current of properties of a formed device (paragraph 12,29).
Regarding claim 2.
Choi in view of Naruta teaches the semiconductor device of claim 1, further
Naruta teaches:
the metal structure (fig 2a:28,29; [para 0025]) comprises a test pattern (fig 2a; [para 0025]).
Regarding claim 7.
Choi in view of Naruta teaches the semiconductor device of claim 1, further
Choi teaches:
the structure (fig 11:41; [para 0042]) is on a top surface of the semiconductor substrate (fig 11:21; [para 0068]).
Naruta teaches:
the metal structure (fig 2a:28,29; [para 0025]).
Regarding claim 9.
Choi in view of Naruta teaches the semiconductor device of claim 1, further
Choi teaches:
a plurality of structures (fig 7,11:49a,41; [para 0062]) comprising the structure (fig 7,11:49a,41; [para 0062]), and wherein the plurality of metal structures (fig 7,11:49a,41; [para 0062]) are arranged on the edge region (fig 11:SL11,SL12; [para 0034]) in a direction parallel to the side surface of the insulating layer (fig 11:31; [para 0036]).
Naruta teaches:
the metal structure (fig 2a:28,29; [para 0025])
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2021/0175133) in view of Naruta (US 2009/0001368) as applied to claim 2 and further in view of Chakihara (US 2019/0326311)
Regarding claim 3
Choi in view of Naruta teaches the semiconductor device of claim 2, above.
Choi in view of Naruta does not teach the structure comprises a capacitor.
Chakihara teaches:
the test pattern comprises a capacitor (fig 13:CP; [para 0113]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the test element to comprise a capacitor so that the TEG can be used to measure capacitance (paragraph 4).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2021/0175133) in view of Naruta (US 2009/0001368) as applied to claim 1 and further in view of Shin (US 2019/0221535)
Regarding claim 4.
Choi in view of Naruta teaches the semiconductor device of claim 1, above
Choi in view of Naruta does not teach a side surface of the semiconductor substrate is coplanar with the side surface of the insulating layer.
Shin teaches:
a side surface of the semiconductor substrate (fig 6e:100; [para 0068]) is coplanar with the side surface of the insulating layer (fig 6e:110; [para 0043]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form a coplanar sidewall because this will result from a sawing process that divides chip regions
Claim(s) 5 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2021/0175133) in view of Naruta (US 2009/0001368) as applied to claim 1 and further in view of Shin (US 2019/0221535)
Regarding claim 5.
Choi in view of Naruta teaches the semiconductor device of claim 1, above
Choi in view of Naruta does not teach an interconnect connected to the pad.
Shin teaches:
an interconnection layer (fig 6e:CLa; [para 0044]) on the insulating layer (fig 6e:110; [para 0043]), wherein the pad (fig 6e:141; [para 0060]) is on the interconnection layer (fig 6e:CLa; [para 0044]) and is electrically connected to the interconnection layer (fig 6e:CLa; [para 0044]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the pad on interconnect so that voltage applied to the pad can be conveyed to the devices within the structure.
Regarding claim 6.
Choi in view of Naruta in view of Shin teaches the semiconductor device of claim 5,
Choi teaches
a protective layer (fig 11:35a,35b; [para 0036]) , wherein a distance between a top surface of the device region (fig 11:CH; [para 0033]) of the semiconductor substrate (fig 11:21; [para 0033]) and a top surface of the protective layer (fig 11:35b; [para 0036]) is greater than a distance between a top surface of the edge region (fig 11:SL1,SL2; [para 0033]) of the semiconductor substrate (fig 11:21; [para 0033]) and the top surface of the protective layer (fig 11:35b; [para 0036]).
Shin teaches:
an interconnection layer (fig 6e:CLa; [para 0044])
Claim(s) 10, 11, 12, 14, 15, 16, 18, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2021/0175133) in view of Naruta (US 2009/0001368) in view of Shin (US 2019/0221535)
Regarding claim 10.
Choi teaches:
A semiconductor device comprising:
a semiconductor substrate (fig 11:21; [para 0068]) including comprising a device region (fig 11:CH; [para 0033]) and an edge region (fig 11:SL11,SL12; [para 0034]) which surrounds the device region (fig 11:CH; [para 0033]);
a semiconductor component (fig 11:MC; [para 0038]) on a top surface of the device region (fig 11:CH; [para 0033]);
a structure (fig 11:41; [para 0042]) on a top surface of the edge region (fig 11:SL11,SL12; [para 0034]), the structure (fig 11:41; [para 0042]) comprising a top surface and a side surface;
;
an insulating layer (fig 11:31; [para 0036]) surrounding the semiconductor component (fig 11:MC; [para 0038]) and the structure (fig 11:41; [para 0042]);
and a pad (fig 11:64; [para 0048]) on the device region (fig 11:CH; [para 0033]), , and wherein the structure (fig 11:41; [para 0042])is spaced apart from a side surfacein a direction toward an inside of the semiconductor substrate (fig 11:21; [para 0068]), and wherein the top surface and the side surface of the structure (fig 11:41; [para 0042]) are surrounded by the insulating layer (fig 11:31; [para 0036]) and are not exposed at a top surface and a side surface of the insulating layer (fig 11:31; [para 0036]) .
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Choi does not teach that the structure is metal and floating.
Naruta teaches:
a metal structure (fig 2a:28,29; [para 0025]), comprising a top surface and a side surface;
the metal structure (fig 2a:28,29; [para 0025]) is electrically floating ([para 0025])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the structure of metal because it is highly conductive enabling conduction of voltage, further by forming a floating structure it can be used to evaluate the current of properties of a formed device (paragraph 12,29).
Choi does not teach interconnect on the device region
Shin teaches:
an interconnection layer (fig 6e:CLa,CLb; [para 0044]) on the semiconductor component (fig 6e:101; [para 0044]) and the structure (fig 6d,6e:103; [para 0066]);
an insulating layer (fig 6e:110; [para 0043]);
and a pad (fig 6e:141; [para 0060]) on the interconnection layer (fig 6e:CLa,CLb; [para 0044]) on the device region (fig 6e:10b; [para 0040]), wherein the pad (fig 6e:141; [para 0060]) is electrically connected to the interconnection layer (fig 6e:CLa,CLb; [para 0044]), and a side surface of the semiconductor substrate (fig 6e:100; [para 0040]) in a direction toward an inside of the semiconductor substrate (fig 6e:100; [para 0040]),
It would have been obvious to one of ordinary skill in the art before the effective filing date of the clamed invention to provide interconnection in the chip area in order to convey voltage from the pad to devices, further it would be obvious to provide the semiconductor substrate with a side surface as a consequence of sawing and dividing the structure.
Regarding claim 11.
Choi in view of Naruta in view of Shin teaches the semiconductor device of claim 10, further
Shin teaches:
the interconnection layer (fig 6e:CLa,CLb; [para 0044]) is on the insulating layer (fig 6e:110; [para 0043]).
Regarding claim 12.
Choi in view of Naruta in view of Shin teaches the semiconductor device of claim 11, further
a side surface of the structure (fig 11:41; [para 0042])is spaced apart from a side surface of the insulating layer (fig 11:31; [para 0036])in the direction toward the inside of the semiconductor substrate (fig 11:MC; [para 0038]).
Naruta teaches:
a metal structure (fig 2a:28,29; [para 0025]),
Regarding claim 14.
Choi in view of Naruta in view of Shin teaches the semiconductor device of claim 11, further
Shin teaches
the side surface of the semiconductor substrate (fig 6e:100; [para 0040])is coplanar with a side surface of the insulating layer (fig 6e:110; [para 0043]).
Regarding claim 15.
Choi in view of Naruta in view of Shin teaches the semiconductor device of claim 10, further
Choi teaches:
the structure (fig 11:41; [para 0042]) is electrically insulated (fig 11:31; [para 0036]) from the semiconductor component (fig 11:MC; [para 0038]).
Naruta teaches:
a metal structure (fig 2a:28,29; [para 0025]),
Regarding claim 16.
Choi in view of Naruta in view of Shin teaches the semiconductor device of claim 10, further
Choi teaches:
the structure (fig 11:41; [para 0042]) comprises a test pattern ([para 0037])
Naruta teaches:
a metal structure (fig 2a:28,29; [para 0025]),
Regarding claim 18.
Choi in view of Naruta in view of Shin teaches the semiconductor device of claim 10, further
Choi teaches:
a protective layer (fig 11:35a,35b; [para 0036]) , wherein a distance between the top surface of the device region (fig 11:CH; [para 0033]) of the semiconductor substrate (fig 11:21; [para 0033]) and a top surface of the protective layer (fig 11:35b; [para 0036]) is greater than a distance between the top surface of the edge region of the semiconductor substrate (fig 11:21; [para 0033]) and the top surface of the protective layer (fig 11:35a; [para 0036]).
Shin teaches:
An interconnection layer (fig 6e:CLa; [para 0044])
Regarding claim 19.
Choi in view of Naruta in view of Shin teaches the semiconductor device of claim 10, further
Choi teaches:
the structure (fig 11:41; [para 0042]) is on the top surface of the semiconductor substrate (fig 11:21; [para 0033]).
Naruta teaches:
a metal structure (fig 2a:28,29; [para 0025]),
Claim(s) 31, 32, and 33 is/are rejected under 35 U.S.C. 103 as being unpatentable over Choi (US 2021/0175133) in view of Naruta (US 2009/0001368)
Regarding claim 31.
Choi teaches
A semiconductor device comprising: a semiconductor substrate (fig 11:21; [para 0068]) comprising a device region (fig 11:CH; [para 0033]) and an edge region (fig 11:SL11,SL12; [para 0034]);
a semiconductor component (fig 11:MC; [para 0038])on the device region (fig 11:CH; [para 0033]);
a test structure (fig 11:41; [para 0042]) on the edge region (fig 11:SL11,SL12; [para 0034]), wherein the test structure (fig 11:41; [para 0042]) is electrically insulated (fig 11:31; [para 0036]) from the semiconductor component (fig 11:MC; [para 0038]) and comprises a top surface and a side surface;
and an insulating layer (fig 11:MC; [para 0038]) on the semiconductor substrate (fig 11:MC; [para 0038]), the semiconductor component (fig 11:MC; [para 0038]), and the test structure (fig 11:41; [para 0042]);
and wherein the test structure (fig 11:41; [para 0042]) is between the semiconductor component (fig 11:MC; [para 0038]) and a side surface of the insulating layer (fig 11:31; [para 0036]), wherein the top surface and the side surface of the test structure (fig 11:41; [para 0042]) are surrounded by the insulating layer (fig 11:31; [para 0036]) and are not exposed at a top surface and the side surface of the insulating layer (fig 11:31; [para 0036]) .
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Choi does not teach that the structure is floating.
Naruta teaches:
a test structure (fig 2a:28,29; [para 0025]), is electrically floating ([para 0025])
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the structure of metal because by forming a floating structure it can be used to evaluate the current of properties of a formed device (paragraph 12,29).
Regarding claim 32.
Choi in view of Naruta teaches the semiconductor device of claim 31,
Choi teaches:
the semiconductor component (fig 11:MC; [para 0038]) is comprised in a plurality of semiconductor components (fig 11:MC; [para 0038]) on the device region (fig 11:CH; [para 0033]).
Regarding claim 33.
Choi in view of Naruta teaches the semiconductor device of claim 31,
Choi teaches:
the test structure (fig 11:41; [para 0042]) is comprised in a plurality of test structures (fig 7:49a; [para 0037])
on the [edge] region (fig 11:SL11,SL12; [para 0034]),wherein the plurality of test structures (fig 7:49a; [para 0037]) are between the semiconductor component (fig 11:MC; [para 0038]) and the side surface of the insulating layer (fig 11:MC; [para 0038]).
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Response to Arguments
Applicant’s arguments with respect to claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference combination applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The applicant argues that previously applied art does not anticipate all elements of the claim. However, the current rejection relied upon a different embodiment from Choi in combination new reference Naruta (see above).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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