DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 3/6/2023 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “a protective layer on the interconnection layer, wherein a distance between a top surface of the device region and a top surface of the protective layer is greater than a distance between a top surface of the edge region and the top surface of the protective layer” of claim 6 and 18 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
The drawings as filed do not show the above element, rather the drawings as filed show:
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Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4, 5, 6, 7, and 9 is/are rejected under 35 U.S.C. 102a1as being anticipated by Shin (US 2019/0221535)
Regarding claim 1.
Shin teaches semiconductor device comprising: a semiconductor substrate (100) including a device region (10b) and an edge region (23b) (paragraph 40) (fig 6e); a semiconductor component (101) on the device region (10b) (fig 6e) (paragraph 41); a metal structure (113b) on the edge region (23b) (paragraph 45,46); an insulating layer (110) surrounding the semiconductor component (101) and the metal structure (113b) (fig 6e) (paragraph 44); and a pad (141) on the semiconductor component (101) (fig 6e) (paragraph 60), wherein the metal structure (113b) is surrounded by the insulating layer (110) and is not exposed at a side surface of the insulating layer (110), and wherein the metal structure (113b) is electrically insulated from the semiconductor component (101) (fig 6e).
Regarding claim 4.
Shin teaches the structure of claim 1.
Shin teaches a side surface of the semiconductor substrate (100) is coplanar with the side surface of the insulating layer (110) (fig 6e) (paragraph 68).
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Regarding claim 5
Shin teaches the structure of claim 1.
Shin teaches an interconnection layer (121) on the insulating layer (110), wherein the pad (141) is on the interconnection layer (121) and is electrically connected to the interconnection layer (121) (fig 6e) (paragraph 49,50).
Regarding claim 6.
Shin teaches the structure of claim 5.
Shin teaches a protective layer (133) on the interconnection layer (121), wherein a distance between a top surface of the device region (10b) and a top surface of the protective layer (133) is greater than a distance between a top surface of the edge region (23b) and the top surface of the protective layer (133).
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Regarding claim 7.
Shin teaches the structure of claim 1.
Shin teaches the metal structure (113b) is on a top surface of the semiconductor substrate (100) (fig 6e) (paragraph 68,69).
Regarding claim 9.
Shin teaches the structure of claim 1.
Shin teaches a plurality of metal structures (113b) including the metal structure (113b), and wherein the plurality of metal structures (113b) are arranged on the edge region (23b) in a direction (D2) parallel to the side surface of the insulating layer (fig 5) (paragraph 44,45).
Claim(s) 10, 11, 12, 13, 14, 15, 18, and 19 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Shin (US 2019/0221535)
Regarding claim 10.
Shin teaches a semiconductor device comprising: a semiconductor substrate (100) including a device region (10b) and an edge region (23b) which surrounds the device region (10b) (paragraph 40); a semiconductor component (101) on a top surface of the device region (10b) (paragraph 41); a metal structure (113b) on a top surface of the edge region (23b) (paragraph 45,46) (fig 6e); an interconnection layer (121) on the semiconductor component (101) and the metal structure (123b) (paragraph 49); and a pad (141) on the interconnection layer (121) on the device region (10b) (paragraph 60), wherein the pad (141) is electrically connected to the interconnection layer (121), and wherein the metal structure (113b) is spaced apart from a side surface of the semiconductor substrate (100) in a direction (d1) toward an inside of the semiconductor substrate (fig 6e,5).
Regarding claim 11.
Shin teaches the structure of claim 10.
Shin teaches an insulating layer (110) surrounding the semiconductor component (101) and the metal structure (13b) (fig 6e) (paragraph 43), wherein the interconnection layer (123b) is on the insulating layer (110) (fig 6e) (paragraph 51,52).
Regarding claim 12
Shin teaches the structure of claim 11.
Shin teaches a side surface of the metal structure (113b) is spaced apart from a side surface of the insulating layer (110) in the direction (d1) toward the inside of the semiconductor substrate (100) (fig 5,6e).
Regarding claim 13.
Shin teaches the structure of claim 11.
Shin teaches the metal structure (113b) is surrounded by the insulating layer (110) and is not exposed at a side surface of the insulating layer (110) (fig 6e).
Regarding claim 14.
Shin teaches the structure of claim 11.
Shin teaches the side surface of the semiconductor substrate (100) is coplanar with a side surface of the insulating layer (110) (fig 6e).
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Regarding claim 15.
Shin teaches the structure of claim 10.
Shin teaches the metal structure (113b) is electrically insulated from the semiconductor component (101) (fig 6e) (paragraph 43).
Regarding claim 18.
Shin teaches the structure of claim 10.
Shin teaches a protective layer (133) on the interconnection layer (123b) (paragraph 54), wherein a distance between the top surface of the device region (10b) and a top surface of the protective layer (133) is greater than a distance between the top surface of the edge region (23b) and the top surface of the protective layer (133) (fig 6e).
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Regarding claim 19.
Shin teaches the structure of claim 10.
Shin teaches the metal structure (123b) is on the top surface of the semiconductor substrate (100) (fig 6e) (paragraph 51,52).
Claim(s) 31, 32, and 33 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Choi (US 2021/0175133)
Regarding claim 31.
Shin teaches a semiconductor device comprising: a semiconductor substrate (21) including a device region (CH) and an edge region (SL11) (fig 11) (paragraph 33); a semiconductor component (MC) on the device region (CH) (fig 11) (paragraph 33); a test structure (41) on the edge region (SL11) (paragraph 41), wherein the test structure (41) is electrically insulated (31) from the semiconductor component (CH) (paragraph 33); and an insulating layer (33) on the semiconductor substrate (21), the semiconductor component (MC), and the test structure (41); and wherein the test structure (41) is between the semiconductor component (CH) and a side surface of the insulating layer (33), and wherein the test structure (41) is not exposed at the side surface of the insulating layer (33) (fig 11) (paragraph 41).
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Regarding claim 32.
Choi teaches the structure of claim 31.
Choi teaches the semiconductor component (MC) is included in a plurality of semiconductor components on the device region (CH) (fig 5) (paragraph 57).
Regarding claim 33.
Choi teaches the structure of claim 31
Choi teaches the test structure (41) is included in a plurality of test structures on the device region (fig 7) (paragraph 62), wherein the plurality of test structures are between the semiconductor component (MC) and the side surface of the insulating layer (33), and wherein the plurality of test structures are not exposed at the side surface of the insulating layer (fig 11).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over
Shin (US 2019/0221535) as applied to claim 1 in view of Choi (US 2021/0175133)
Regarding claim 2.
Shin teaches the structure of claim 1.
Shin does not teach a test pattern.
Choi teaches the metal structure (49a) comprises a test pattern (41) (fig 10)(paragraph 37,105).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a test pattern in order to for determining whether elements are suitably formed in the semiconductor device formed on the semiconductor wafer (Choi paragraph 4).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over
Shin (US 2019/0221535) in view of Choi (US 2021/0175133) as applied to claim 2 and further in view of Otsuki (US 2008/0308800)
Regarding claim 3.
Shin teaches the structure of claim 1.
Shin does not teach a test pattern comprises a capacitor.
Otsuki teaches the test pattern comprises a capacitor (paragraph 32).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a test pattern in order to provide a test pattern comprising a capacitor in order for the test pattern to evaluate the alignment of features by measuring changes in impedance and resistance across the capacitive feature
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over
Shin (US 2019/0221535) as applied to claim 10 in view of Choi (US 2021/0175133)
Regarding claim 16.
Shin teaches the structure of claim 10.
Shin does not teach a test pattern.
Choi teaches the metal structure (49a) comprises a test pattern (41) (fig 10) (paragraph 37,105).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide a test pattern in order to for determining whether elements are suitably formed in the semiconductor device formed on the semiconductor wafer (Choi paragraph 4).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J GOODWIN whose telephone number is (571)272-8451. The examiner can normally be reached Monday - Friday, 11:00 - 19:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571)272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D.J.G/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817 December 9, 2025
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