DETAILED ACTION
This application, 17/559490, attorney docket 00158.0803.00US, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This application is assigned to Semiconductor Manufacturing International (Shanghai) Corporation foreign priority to 202210468722.4, filed 04/29/2022.
Claims 1-8 and 21-31 are pending and are considered below. Note that examiner will use numbers in parentheses to indicate numbered elements in prior art figures, and brackets to point to paragraph numbers where quoted material or specific teachings can be found.
Response to Arguments
Applicant has amended claim 1 to remove the disputed language (the base is now only referred to as the substrate, in harmony with the drawing), but argues that the 112b was improper because the base and the substrate are the same element. Applicant further argues that the first a second conductive layers are supported in figures f4and 18 The examiner need not address the arguments because they are moot in light of the amendments. Applicant correctly argues that the amendment overcomes both the §112a of claim 2 and the §112b of claim 1, as well as the drawing objections which are withdrawn.
Applicant argues that amended claim is distinguished from prior art Lee because the amended claim 1 is not anticipated by Lee. Examiner disagrees. The amended rejection, and remapping is presented below which shows that each element of the claim is taught by Lee.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the plugs with different depth recited in claim 8 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. In addition, figures 7 and 8 show 207 and 208 as groove, but the structures are shown to have a top surface that is above the surface of the dielectric 206, into which they grooves are formed. It is not clear how the structure can represent groove.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
Claim 8 is rejected under 35 U.S.C. 112(a) as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claim 8 recites, “…and depths of the plurality of first plug structures are 30% to 70% of the depths of the plurality of second plug structures.” The specification refers to grooves 207 and 208 of figures 7 and 8 having different sizes, but it does not teach how the plugs can be different depth when they must reach from bottom metal surfaces that are coplanar to top meta surfaces that are coplanar. Figure 2 clearly shows plugs 108 and 109 are the same depth.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 2 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 2 recites, “the plurality of first metal layers and the plurality of second metal layers are located in the first region (of the substrate)” but claim 1 requires, “a bottom metal structure located on the device layer, which is require to be “on the substrate, so the metal cannot be in the region defined.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7, 21-26, 28-29 and claim 31 are rejected under 35 U.S.C. 102 a1/a2 as being anticipated by Lee et al. (U.S. 2019/0157198).
As for claim 1,
Lee teaches in figure 1, 2, 7, and 8 a semiconductor structure, comprising:
a substrate (30) including a base, a device structure located on the base, and conductive layers (V1) located on the device structure; (not shown)
a bottom metal structure (v1) located on the substrate; the bottom metal structure (200/300) being electrically connected to the conductive layers;
a first dielectric layer (110) located on the bottom metal structure, wherein the first dielectric layer contains:
a first opening structure (110, figure 8) including first grooves (214) and second grooves (212) on top of the first grooves, an extension direction (into the page) of the first opening structure being parallel to an extension direction of the bottom metal structure, a projection of one of the first grooves on the substrate being located within a projection of one of the second grooves on the substrate (shown in figure 2), and bottoms of the first grooves exposing surface of the first dielectric layer;
a second opening structure (320) including third grooves (340) and fourth grooves (320) on top of the third grooves, projections of a number of the third grooves on the substrate being located within a projection of one of the fourth grooves on the substrate Shown in figure 2), the third grooves exposing top surface of the bottom metal structure (they act as vias [0092-93], and depths of the first grooves being smaller than depths of the third grooves (d12 shown beside 340 in figure 8);
first plug structures located in the first grooves; second plug structures located in the third grooves; and first metal structures located in the second grooves and the fourth grooves (all grooves are filled with metal [0047]).
As for Claim 1,
Lee teaches in figures 1, 2, and 8, a semiconductor structure, comprising:
a substrate (30), a device layer (layer below M1, which would contain devices built on the substrate. located on the substrate, and conductive layers (212/312) located on the device layer;
a bottom metal structure (220/230) located on the device layer, the bottom metal structure being electrically connected to the conductive layers (they are continuous), the bottom metal structure including a plurality of first metal layers (320) and a plurality of second metal layers (220) alternately arranged in parallel along a first direction parallel to a surface of the substrate (arranged in the x-direction, shown parallel);
and a first dielectric layer (400 above M1 level 1) located on the bottom metal structure, wherein the first dielectric layer contains:
a plurality of first plug (240 [0093]) structures arranged in parallel along the first direction (shown along x );
and a first metal structure (M2) including a plurality of third metal layers (320) and a plurality fourth metal layers (220) alternately arranged in parallel along the first direction and respectively located on the plurality of first plug structures, wherein:
the plurality of third metal layers is located over the plurality of first metal layers;
and the plurality of fourth metal layers is located over the plurality of second metal layers. (Metal lines are aligned vertically, shown in figure 1).
As for Claim 2,
Lee teaches the semiconductor structure according to claim 1, and teaches that
the substrate includes a first region and second regions located at two sides of the first region along a second direction parallel to the surface of the substrate, the second direction perpendicular to the first direction;
and the plurality of first metal layers and the plurality of second metal layers are located in the first region (the metal lines are all entered between the conducive lines 212/312);
As for Claim 3,
Lee teaches the semiconductor structure according to claim 1, and Lee teaches that the conductive layers include a first conductive layer (214) and a second conductive layer (314) in the second regions respectively;
the first dielectric layer further contains a plurality of second plug structures;
and the plurality of second plug structures includes a plurality of first plugs located on the first conductive layer and a plurality of second plugs located on the second conductive layer. (V2 represent the second layer of plugs in the next layer of dielectric).
As for Claim 4,
Lee teaches the semiconductor structure according to claim 3, wherein:
the conductive layers further include a third conductive layer and a fourth conductive layer (212/312 at M3);
and the third conducive layer is located on the plurality of first plugs (connected to V2 at 214), and the fourth conducive layer is located on the plurality of second plugs (connected to V2 at the opposite end [0093])).
As for Claim 5,
Lee teaches the semiconductor structure according to claim 4, further comprising:
a second metal structure ( 200/300 atM3) located on the first metal structures, the second metal structure including a plurality of fifth metal layers and a plurality of sixth metal layers alternately arranged in parallel along the first direction. (Shown in figure 1).
As for Claim 6,
Lee teaches the semiconductor structure according to claim 5, further comprising:
third plugs located on the third conductive layer; and
fourth plugs located on the fourth conductive layer layers.(V4, at 212 and 312)
As for Claim 7,
Lee teaches the semiconductor structure according to claim 3, wherein:
projected images of the plurality of second plug structures on the substrate are rectangles (214 in figure 2 represents the via as a triangular trench);
and sizes of the plurality of first plug structures in the first direction are smaller than side lengths of the projected images of the plurality of second plug structures. (shown in figure 2)
As for Claim 21,
Lee teaches the semiconductor structure according to claim 2, wherein:
the conductive layers include a first conductive layer and a second conductive layer respectively located in the second regions; and
the first conductive layer and the second conductive layer are parallel to the first direction. (shown in figure 2).
As for Claim 22,
Lee teaches the semiconductor structure according to claim 21, and Lee teaches
the plurality of first metal layers is connected to the first conductive layer; and
the plurality of second metal layers is connected to the second conductive layer. (Shown in figure 2).
As for Claim 23,
Lee teaches the semiconductor structure according to claim 21, and lee teaches
first spacings are located between the plurality of first metal layers and the second conductive layer; and
second spacings are located between the plurality of second metal layers and the first conductive layer. (gaps shown in figure 2)
As for Claim 24,
Lee teaches the semiconductor structure according to claim 4, and teaches in figure 2,
the plurality of fourth metal layers is connected to the third conductive layer;
the plurality of third metal layers is connected to the fourth conductive layers;
third spacings are located between the plurality of third metal layers and the third conductive layer; and
fourth spacings are located between the plurality of fourth metal layers and the fourth conductive layer. (each metal level is the same with conductive layer extending in the x direction and fingers of metal extending in the y direction).
As for Claim 25,
Lee teaches the semiconductor structure according to claim 4, and teaches
the plurality of third metal layer is electrically connected to the plurality of second metal layers through the fourth conductive layer, the plurality of second plugs, and the second conductive layer; and the plurality of fourth metal layers is electrically connected to the plurality of first metal layers through the third conductive layer, the plurality of first plugs, and the first conductive layer. The vias connect the left and right-side layers vertically together in figure 1)
As for Claim 26,
Lee teaches the semiconductor structure according to claim 6, and teaches in figures 1 and 2,
the conductive layers further include a fifth conductive layer located on the third conductive layer, and a sixth conductive layer located on the fourth conductive layer; and
the fifth conductive layers and the sixth conductive layers are parallel to the first direction. (The m4 level is the same as the m3 level of Lee).
As for Claim 28,
Lee teaches the semiconductor structure according to claim 26, and teaches
the plurality of fifth metal layers is connected to the fifth conductive layer;
the plurality of sixth metal layers is connected to the sixth conductive layers;
fifth spacings are located between the plurality of fifth metal layers and the sixth conductive layer; and
sixth spacings are located between the plurality of sixth metal layers and the fifth conductive layer. (the geometry of each layer is identical so will mirror the arrangement of M1).
As for Claim 29,
Lee teaches the semiconductor structure according to claim 26, and teaches that
the plurality of fifth metal layers is electrically connected to the plurality of fourth metal layers through the fifth conductive layer, the third plugs, and the third conductive layer; and
the plurality of sixth metal layers is electrically connected to the plurality of third metal layers through the sixth conductive layer, the fourth plugs, and the fourth conductive layer. (the geometry of each layer is identical so will mirror the arrangement of M1).
As for Claim 31,
Lee teaches the semiconductor structure according to claim 5, and Lee teaches that
projections of the plurality of fifth metal layers on the substrate partially coincide with projections of the plurality of third metal layers on the substrate; and
projections of the plurality of sixth metal layers on the substrate partially coincide with projections of the plurality of fourth metal layers on the substrate. (the geometry of each layer is identical so will mirror the arrangement of M1 and substantially coincide, so at least partially coincide).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 27 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Huang et al.( U.S. 2014/0001597).
As for Claim 27,
Lee teaches the semiconductor structure according to claim 6, and teaches a plurality of first metal structures (220) and a plurality of second metal structures (320) alternately arranged vertically in a direction perpendicular to the surface of the substrate (M1 figure 1); and
the plurality of fifth metal layers is located on the plurality of third metal layers, and the plurality of sixth metal layers is located on the plurality of fourth metal layers.(layers are stacked shown in figure 1)
but does not teach that the structure includes a plurality of second adhesion layers located at bottoms of the plurality of fifth metal layers and the plurality of sixth metal layers,
However, Huang teaches a plurality of second adhesion layers (seed layers, [0013]) located at bottoms of the plurality of fifth metal layers and the plurality of sixth metal layers.
It would have been obvious to one skilled in the art at the effective filing date of this application add the seed layer of Huang to Lee to improve uniformity of metal deposition into the dielectric trenches. One skilled in the art would have combined these elements with a reasonable expectation of success.
As for Claim 30,
Lee in view of Huang makes obvious the semiconductor structure according to claim 27, and in the combination, the depths of the second adhesion layers are smaller than depths of the third plugs and the fourth plugs because the seed layer is a molecular deposition, and the plugs extend a thickness near the thickness of the metal layer.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN A BODNAR whose telephone number is (571)272-4660. The examiner can normally be reached M-Th and every other Friday 7:30-5:30 Central time.
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/JOHN A BODNAR/Primary Examiner, Art Unit 2893