DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 2, 8-10 is/are rejected under 35 U.S.C. 102(a)(1)/ 102(a)(2) as being anticipated by LEE (US 20220367486), (hereinafter, LEE).
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RE Claim 1, LEE discloses in FIGS. 3-5 a semiconductor memory device. LEE discloses a semiconductor device comprising:
a substrate “SUB”, referring to FIG. 4;
a source structure “SL” disposed on the substrate “SUB”;
cell stack structures “NMC_R normal cell region” disposed on the source structure “SL”;
a dummy stack structure “DMC_R” disposed between the cell stack structures “NMC_R” on the source structure “SL”;
vertical barriers “CO core insulating layer” [0054] disposed between the dummy stack structure “DMC_R” and the cell stack structures “DMC_R”; and
at least one lower protective pattern 117 disposed at a lower portion of the dummy stack structure “DMC_R” between the vertical barriers “135”.
RE Claim 2, LEE discloses a semiconductor device, wherein the dummy stack structure “DMC_R” includes a first stack structure ST1 and a second stack structure ST2 on the first stack structure ST1, and wherein the at least one lower protective pattern 117 is disposed at the same level as the first stack structure ST1, referring to FIG. 5D.
RE Claim 8, LEE discloses semiconductor device, wherein the dummy stack structure “DMC_R” includes dummy interlayer insulating layers “ILD 123 silicon oxide” and sacrificial insulating layers 121 “silicon nitride” which are alternately stacked, referring to FIGS. 4 and 5D [0070-0071],
wherein the cell stack structures “NMC_R” include interlayer insulating layers “ILD3” and conductive patterns “GP2”, which are alternately stacked, and wherein the dummy stack structure “DMC_R” is isolated from the cell stack structures “NMC_R” by the vertical barriers “CO core insulating layer”, referring to FIG. 4.
RE Claim 9, LEE discloses semiconductor device, wherein the dummy stack structure “DMC_R” includes a first stack structure ST1 and a second stack structure ST2 on the first stack structure ST1,
wherein the first stack structure ST1 includes a lowermost sacrificial insulating layer 111 of the dummy stack structure “DMC_R”, referring to FIG. 5B, and
wherein the at least one lower protective pattern 117 penetrates the lowermost sacrificial insulating layer 111 of the dummy stack structure “DMC_R”.
RE Claim 10, LEE discloses semiconductor device, further comprising a support sl1 penetrating through a cell stack structure of the cell stack structures to contact a top of the source structure “SL”, referring to FIG. 4.
Allowable Subject Matter
Claims 3-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 03/12/2026 have been fully considered but they are not persuasive. In the instant case, LEE (US 20220367486) was published Nov. 17, 2022 prior to the US filing date of the instant application, hence qualifies under U.S.C. 102(a)(1)/102(a)(2). The foreign priority application KR-10-2022-0109232 is published in the Korean language and cannot be considered as the effective filing date unless it has an official English translation. Accordingly, the aforementioned rejection above is proper under USC. 102(a)(1), and the finality is proper.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. In the instant case, KIM et al. (US 2022/0302157) disclose a semiconductor memory device, wherein a through via structure includes a through via and a capping pattern. The through via includes a metal pattern extending in a vertical direction, and a barrier pattern on a sidewall and a lower surface of the metal pattern. The capping pattern contacts an upper surface of the through via. A lowermost surface of an edge portion of the capping pattern is not higher than a lowermost surface of a central portion of the capping pattern.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YASSER ABDELAZIEZ whose telephone number is (571)270-5783. The examiner can normally be reached Monday - Friday 9 am - 6 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Leonard Chang can be reached at (571)270-3691. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YASSER A ABDELAZIEZ, PhD/Primary Examiner, Art Unit 2898