DETAILED ACTION
This Notice is responsive to communication filed on 03/09/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed 04/29/2026 fails to comply with the provisions of 37 CFR 1.97, 1.98 and MPEP § 609 because it does not include a concise explanation of the relevance, as it is presently understood by the individual designated in 37 CFR 1.56(c) most knowledgeable about the content of the information, of each reference listed that is not in the English language. It has been placed in the application file, but the information referred to therein has not been considered as to the merits. Applicant is advised that the date of any re-submission of any item of information contained in this information disclosure statement or the submission of any missing element(s) will be the date of submission for purposes of determining compliance with the requirements based on the time of filing the statement, including all certification requirements for statements under 37 CFR 1.97(e). See MPEP § 609.05(a).
Response to Amendment
The amendment filed on 06/25/2026 under 37 CFR 1.111 has been entered. Claims 1-15 remain pending in the application.
The amendment filed 06/25/2026 is objected to under 35 U.S.C. 132(a) because it introduces new matter into the disclosure. 35 U.S.C. 132(a) states that no amendment shall introduce new matter into the disclosure of the invention. The added material which is not supported by the original disclosure is as follows:
Claim limitation of claim 1: "the field oxide layer is located between a gate and a drain."
Applicant is required to cancel the new matter in the reply to this Office Action.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the claimed limitation "the field oxide layer is located between a gate and a drain" must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-15 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 1, the limitation “the field oxide layer is located between a gate and a drain” in lines 11 and 12, neither the Specification nor the Drawings disclose or depicts the field oxide layer 108 being located between a drain and a gate.
Claims 2-15 are also rejected as being dependent on claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Rejection Note: Italicized and underlined claim limitations indicate limitations that are not explicitly disclosed in the primary reference(s).
Claims 1-8, 10, 13, and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Ko et al. (US 7238564 B2) and further in view of Li et al. (CN 110718479 A) and Lee (KR 200550067474).
Regarding claim 1, Ko teaches a method of making a semiconductor device, the method comprising:
a) etching a substrate Fig. 2A: 318 to form a trench Fig. 2A: 310 in the substrate Fig. 2A: 318;
b) filling the trench Fig. 2A: 310 with an insulating material layer Fig. 2A: STI (col. 4, lines 19-20, filler material 312), wherein a top surface of the insulating material layer is higher than a top surface of the trench (shown in Fig. 1D);
c) etching the insulating material layer Fig. 2B: STI to form a side groove Fig. 2B: 372 between the insulating material layer Fig. 2B: STI and a top side wall of the trench Fig. 2B: 310 to expose a corner at a top of only one side of the trench Fig. 2B: 372 (col. 4, lines 33-37), wherein the corner is formed on the substrate; and
d) forming a field oxide layer Fig. 2D: 330 on a top surface of the substrate Fig. 2D: 318 by an oxidation process, wherein the field oxide layer covers a portion of the insulating material layer, the corner, and a portion of the top surface of the substrate, wherein the corner at the top of the trench Fig. 2D: 310 is correspondingly oxidized to form into a round corner by the oxidation process (col. 3, lines 47-59), wherein an upper surface and sidewall of the corner are simultaneously oxidized during the oxidation process to form the round corner,
e) wherein the insulating material layer and the field oxide layer comprise a same material. Ko teaches (col. 4, lines 19-20) the STI filler material/insulating material layer 312 is an oxide or polysilicon, and (col. 5, lines 6-10) the gate dielectric/field oxide layer 330 is a silicon/oxide material.
Although Ko’s present invention as shown in Fig. 2A – 3 does not explicitly mention the rounded corner formed by the oxidation process, Ko teaches that it is known in the art that the conventional fabrication process, thermal oxidation used to form oxide films may be used to form rounded corners (see col. 3, lines 47- 59). It would be obvious to one of ordinary skill in the art to include this in Ko’s present invention as shown in Fig. 2A – 3 in order to stabilize and improve the electrical characteristics and performance of the semiconductor device (col. 3, lines 54-57).
Li discloses the following claim limitations not explicitly disclosed by Ko:
etching the insulating material layer Fig. 5: 03 to form a side groove Fig. 5: 05 between the insulating material layer Fig. 5: 03 and a top side wall of the trench to expose a corner at a top of only one side of the trench, wherein the corner is formed on the substrate Fig. 5: 01 (shown in Fig. 5).
It would be obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Ko’s teachings with Li in order to improve the asymmetric bird’s beak defect of a high threshold voltage device (see para. 8, 39).
Lee discloses the following claim limitations not explicitly disclosed by Ko:
wherein an upper surface and sidewall of the corner Fig. 3d: 35a are simultaneously oxidized during the oxidation process to form the round corner Fig. 3e: 35a (para. 28).
It would be obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Lee with Ko’s teachings for the purpose of improving transistor performance and improving reliability of the gate oxide film (para. 16-17).
Regarding claim 2, Ko teaches the method of claim 1, wherein etching the insulating material layer Fig. 2B: STI comprises using a wet etching process (col. 4, line 45).
Regarding claim 3, Ko teaches the method of claim 2, wherein an etching solution used for the wet etching of the insulating material layer Fig. 2B: STI comprises a hydrofluoric acid solution (col. 4, lines 37-39).
Regarding claim 5, Ko teaches the method of claim 1, wherein during the etching of the insulating material layer Fig. 2B: STI, a depth of the side groove Fig. 2B: 372 is controlled by controlling a concentrate ion of an etching solution and a duration of a wet etching process.
It is well known in the art that in wet etching, the depth of a groove is indeed controlled by manipulating the concentration of the etchant solution and the duration of the etching process. A higher concentration or longer etching time will generally result in a deeper groove. And as the etchant used in Ko’s invention will not be left on the substrate and insulating material layer indefinitely, it will be obvious of one of ordinary skill in the art to control a concentration and duration of the etching process.
Regarding claim 6, Ko teaches the method of claim 5, wherein a depth of the side groove Fig. 2B: 372 is from 200A to 400A (col. 4, lines 60-61 “10-2000 angstroms”).
Ko teaches a range that includes the depth of the side groove of claim 6.
Regarding claim 7, Ko teaches the method of claim 1, further comprising forming an anti-oxidation mask Fig. 2A: 314, 316 on the substrate Fig. 2A: 318, wherein a field oxide preparation area is exposed by the anti-oxidation mask Fig. 2A: 314, 316, and a field oxide preparation area comprises a part of the substrate Fig. 2A: 318 that is connected with the trench Fig. 2A: 310 (annotated figure below shows field oxide preparation area).
Regarding claim 10, Ko teaches the method of claim 1, wherein after the forming of the field oxide layer Fig. 2D: 330, the side groove Fig. 2B: 372 is fully filled due to an increase of a volume of the field oxide layer Fig. 2D: 330 (Fig. 3 shows the field oxide layer 330 is expanded to full the side groove as circled), and the substrate Fig. 2D: 318 at the corner of the top of the trench is oxidized to form a round corner (col. 4, lines 33-37).
Although Ko’s present invention as shown in Fig. 2A – 3 does not explicitly mention the rounded corner formed by the oxidation process, Ko teaches that it is known in the art that the conventional fabrication process, thermal oxidation used to form oxide films may be used to form rounded corners (see col. 3, lines 47-59). It would be obvious to one of ordinary skill in the art to include this in Ko’s present invention as shown in Fig. 2A – 3 in order to stabilize and improve the electrical characteristics and performance of the semiconductor device (col. 3, lines 54-57).
Also, Lee teaches wherein an upper surface and sidewall of the corner Fig. 3d: 35a are simultaneously oxidized during the oxidation process to form the round corner Fig. 3e: 35a (para. 28).
It would be obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Lee with Ko’s teachings for the purpose of improving transistor performance and improving reliability of the gate oxide film (para. 16-17).
Regarding claim 13, Ko teaches the method of claim 1, wherein the substrate Fig. 2D: 318 comprises silicon (col. 4, lines 58-60 “silicon substrate”), and the field oxide layer Fig. 2D: 330 comprises silicon dioxide (col. 5, lines 7-10), but does not explicitly teach the insulating material layer Fig. 2B: STI comprises silicon dioxide (mentions “oxide” col. 4, lines 19-20).
However, it is well known in the art that silicon dioxide is used as the material for the insulating material layer (see Shallow Trench Isolation, ScienceDirect, 2001). Therefore, it would have been obvious to one of ordinary skill in the art to include an insulating material layer comprising silicon dioxide for the purpose of isolating electrically active regions.
Regarding claim 14, Ko teaches a semiconductor structure Fig. 2D formed by the method of claim 1.
Claims 4 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Ko et al. (US 7238564 B2), Li et al. (CN 110718479 A) and Lee (KR 200550067474) and further in view of Moon et al. (US 5719085).
Regarding claim 4, Moon disclosed the following claim limitations not disclosed by Ko:
The method of claim 3, wherein a volume ratio of hydrofluoric acid to water in the hydrofluoric acid solution is from 1:5 to 1:100 (col. 5, lines 24-27 “a wet etchant comprising 50:1 water to HF”).
It would be obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the teachings of Ko, Li, and Lee with Moon for the purpose of removing just enough pad oxide to allow subsequent 2D oxidation of the trench corner to help reduce leakage current (col. 5, lines 13-27).
Regarding claim 8, Ko, in Figs. 1A-1D, discloses wherein the forming the anti-oxidation mask on the substrate comprises:
a) forming a photoresist material layer Fig. 1A: 320 on the substrate Fig. 1A: 318; and
b) forming a window Fig. 1B: 322 (exposure section) in the photoresist material layer Fig. 1B: 320 through an exposure and development process to form the anti-oxidation mask, wherein the field oxide preparation area is exposed by the window Fig. 1B: 322 (col. 3, lines 11-18), and the anti-oxidation mask is used to isolate oxygen on the substrate surface to avoid oxidation thereof.
Moon discloses the following claim limitations not explicitly disclosed by Ko:
the anti-oxidation mask is used to isolate oxygen on the substrate surface to avoid oxidation thereof (col. 1, lines 19-26 “a silicon nitride mask and pad oxide layer are used to grow field isolation regions…the silicon nitride mask prevents oxidation of the silicon substrate”.
It would be obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Ko with Moon’s teachings to create a semiconductor device with the above limitations for the purpose of growing field isolation regions and preventing the substrate from being oxidized (col. 1, lines 21-25).
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Claims 9, 11, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Ko et al. (US 7238564 B2), Li et al. (CN 110718479 A) and Lee (KR 200550067474) as applied to claim 1 above, and further in view of Wang et al. (US 11024722 B1) and Davies (US 6197640 B1).
Regarding claim 9, Davies teaches the following claim limitations not explicitly disclosed by Ko:
The method of claim 1, wherein the oxidation process comprises using a high-pressure field oxide furnace tube (col. 2, lines 38-60), and
Wang teaches the following claim limitations not explicitly disclosed by Ko:
a thickness of the field oxide layer Fig. 1: 520 is from 300A to 1000A (col. 5, lines 20-23).
In col. 5 lines 36-42, Wang teaches that one end portion of the oxide layer 520 may be of a thickness of the first oxide layer 510. Hence teaching a range of 100A to greater than 1000A for the field oxide layer 520.
It would be obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Ko with these teachings for the purpose of having an oxide layer used to reduce the gate-to-drain capacitance and increase frequency response of a MOSFET (Davies, col. 4, lines 24-26; col. 8, lines 19-20), and forming a thick field oxide layer that can facilitate electric field modulation in the substrate and thus improve the device’s voltage resistance (Wang, col. 5, lines10-17).
Regarding claim 11, Wang discloses the following claim limitations not explicitly disclosed by Ko:
The method of claim 7, further comprising forming a polysilicon layer Fig. 1: 800 (electrode conductive layer) on the field oxide layer Fig. 1: 520, wherein the polysilicon layer Fig. 1: 800 extends to a part of the surface of the substrate Fig. 1: 100 connected with the field oxide layer Fig. 1: 520 (connection is shown in Fig. 1).
It is well known in the art that polysilicon layers are commonly used to create conductive electrode layers.
It would be obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Ko with these teachings in order to create a semiconductor device with a polysilicon layer for the purpose of modulating and homogenizing an electric field distribution in the substrate and improving the breakdown voltage (col. 6, lines 11-16).
Regarding claim 12, Wang discloses the following claim limitations not explicitly disclosed by Ko:
the method of claim 11, further comprising removing the anti-oxidation mask Fig. 3f: 200 before the forming of the polysilicon layer Fig. 3i: 800 (col. 9, lines 60-64, S500).
It would be obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Ko with these teachings and remove the anti-oxidation mask before the forming of the polysilicon layer in order to implant phosphorous, arsenic or boron ions into the substrate to form a P-type well region or an N-type drift region (col. 10, lines 4-10, 47-50).
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Ko et al. (US 7238564 B2), Li et al. (CN 110718479 A) and Lee (KR 200850067474) as applied to claim 1 above, and further in view of Choi (KR 100917106).
Regarding claim 15, Choi discloses the following claim limitations not disclosed by Ko:
The method of claim 1, wherein the top surface of the insulating material layer Fig. 6: 114 remains higher than the top surface of the trench Fig. 2: 108 after etching the insulating material layer (shown in Fig. 6).
Choi teaches the reduced etching of high-density plasma oxide film 112 which is then implanted with ion to form the device isolation layer 114.
It would be obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Ko with Choi’s teachings for the purpose of suppressing the generation of motes in the corner portion of the upper portion of the trench and prevent a gate oxide film thinning phenomenon at the corner of the trench (para.0028).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NKECHINYERE ESIABA whose telephone number is (571)272-0720. The examiner can normally be reached Monday - Friday 10am-5pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nkechinyere Esiaba/Examiner, Art Unit 2817
/NICHOLAS J TOBERGTE/Primary Examiner, Art Unit 2817
