Technology area: Semiconductors, Circuits & Optics
12 pending office actions • 8 art units • 10 examiners • 0 of 12 (0%) have an AI response strategy ready • 24 patents granted in the last 365 days
Silergy Semiconductor Technology (Hangzhou) Ltd. has 12 pending office actions in Semiconductors, Circuits & Optics. The matters are distributed among 10 examiners across 8 art units, indicating concentration at both examiner and art-unit levels.
GRAHAM, KRETELIA is the busiest examiner, with 2 pending matters. Counsel can coordinate the applications before that examiner while using art-unit groupings to identify recurring examination issues across the broader semiconductor portfolio.
Based on the USPTO statutory response window for each pending office action. 6 of the docket's apps have a known mailing date; the rest are excluded from the tile counts.
Every pending office action with a known statutory deadline, placed on a days-until-due axis. Dots left of Today are overdue; the further right, the more runway. Cases that share a deadline window stack vertically. 6 of the docket's apps have a known mailing date.
Difficulty is derived from the rejection statutes on the most recent pending office action. §101-driven and multi-statute cases are graded Hard; §112-only and obviousness-type double-patenting cases are graded Easy; everything else is Medium. "Unknown" means we have not yet parsed a statute for that office action.
| Bucket | Cases |
|---|---|
| §103 only | 4 (33%) |
| Multi-statute (no §101) | 8 (67%) |
How the docket's pending cases split across USPTO tech-center bands.
Manual office-action response work runs about 10 hours per case. The time-saved bands below show what IP Author's prosecution pipeline typically delivers — a conservative 20% on the low end, 35% in the middle, 50% on the high end.
| Examiner | Apps on this docket | Allow rate | Interview lift |
|---|---|---|---|
| GRAHAM, KRETELIA | 2 | 80.1% | +10.0% |
| BARNES, MALCOLM | 2 | 81.4% | +4.7% |
| PEREZ, BRYAN REYNALDO | 1 | 83.9% | +13.8% |
| HOQUE, MOHAMMAD M | 1 | 85.3% | +9.3% |
| BLACKWELL, ASHLEY NICOLE | 1 | 97.3% | -1.2% |
| BARTELS, CHRISTOPHER A. | 1 | 68.1% | +11.7% |
| RAMASWAMY, ARUN | 1 | 84.8% | +12.3% |
| BAIG, ANEESA RIAZ | 1 | 91.8% | +10.3% |
| MALEK, MALIHEH | 1 | 79.8% | +3.4% |
| TRAN, NGUYEN | 1 | 83.6% | +7.6% |
Cases in front of an examiner with an allow rate of 80%+ where the difficulty is Easy or Medium. The top 3 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 17743646 | POWER CONVERTER | TRAN, NGUYEN | 132d overdue |
| 18141510 | STACKED PACKAGING STRUCTURE AND POWER CONVERTER | BAIG, ANEESA RIAZ | 20d |
| 18773979 | METHOD FOR FORMING ISOLATION TRENCH, AND ISOLATION TRENCH | BLACKWELL, ASHLEY NICOLE | — |
Multi-statute / §101-driven matters, or cases in front of an examiner with an allow rate under 30%. The top 8 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18131952 | SEMICONDUCTOR DEVICE WITH FIELD OXIDE LAYER AND METHOD FOR MANUFACTURING THE SAME | MALEK, MALIHEH | 7d |
| 18760314 | CAPACITOR | RAMASWAMY, ARUN | 33d |
| 18118243 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME | GRAHAM, KRETELIA | 33d |
| 18985337 | CONTROL CIRCUIT AND SWITCHING POWER SUPPLY | PEREZ, BRYAN REYNALDO | — |
| 18892513 | CURVED-GATE TRANSISTOR STRUCTURE | HOQUE, MOHAMMAD M | — |
| 18747608 | ETCHING METHOD FOR SEMICONDUCTOR STRUCTURE COMPRISING SUBSTRATE, FIRST STRUCTURE LOCATED ON PART OF TOP SURFACE OF THE SUBSTRATE, SIDEWALLS STRUCTURE AND FIELD EFFECT TRANSISTOR | GRAHAM, KRETELIA | — |
| 18387153 | MAGNETIC ELEMENT, MANUFACTURING METHOD AND POWER SUPPLY CIRCUIT THEREOF | BARNES, MALCOLM | — |
| 18386302 | INDUCTOR, MANUFACTURING METHOD FOR INDUCTOR, ENCAPSULATION MODULE, AND MANUFACTURING METHOD FOR ENCAPSULATION MODULE | BARNES, MALCOLM | — |
Cases in front of an examiner whose interview lift is 10 percentage points or more — i.e. interviewed cases historically resolve more favorably than non-interviewed ones. The top 6 ordered by deadline are shown.
| App # | Title | Examiner | Due in |
|---|---|---|---|
| 18141510 | STACKED PACKAGING STRUCTURE AND POWER CONVERTER | BAIG, ANEESA RIAZ | 20d |
| 18764890 | SYNCHRONIZATION SIGNAL TRANSMISSION METHOD AND SERIAL COMMUNICATION SYSTEM | BARTELS, CHRISTOPHER A. | 22d |
| 18760314 | CAPACITOR | RAMASWAMY, ARUN | 33d |
| 18118243 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME | GRAHAM, KRETELIA | 33d |
| 18985337 | CONTROL CIRCUIT AND SWITCHING POWER SUPPLY | PEREZ, BRYAN REYNALDO | — |
| 18747608 | ETCHING METHOD FOR SEMICONDUCTOR STRUCTURE COMPRISING SUBSTRATE, FIRST STRUCTURE LOCATED ON PART OF TOP SURFACE OF THE SUBSTRATE, SIDEWALLS STRUCTURE AND FIELD EFFECT TRANSISTOR | GRAHAM, KRETELIA | — |
| Art Unit | Apps |
|---|---|
| 2817 | 3 |
| 2838 | 2 |
| 2897 | 1 |
| 2184 | 1 |
| 2847 | 1 |
| 2837 | 1 |
| 2814 | 1 |
| 2813 | 1 |
| App # | Title | Examiner | Art Unit | Statutes | Status | Due in | AI | Filed |
|---|---|---|---|---|---|---|---|---|
| 18985337 | CONTROL CIRCUIT AND SWITCHING POWER SUPPLY | PEREZ, BRYAN REYNALDO | 2838 | §102§103 | Non-Final OA | — | Pending | Dec 18, 2024 |
| 18892513 | CURVED-GATE TRANSISTOR STRUCTURE | HOQUE, MOHAMMAD M | 2817 | §102§103 | Non-Final OA | — | Pending | Sep 22, 2024 |
| 18773979 | METHOD FOR FORMING ISOLATION TRENCH, AND ISOLATION TRENCH | BLACKWELL, ASHLEY NICOLE | 2897 | §103 | Non-Final OA | — | Pending | Jul 16, 2024 |
| 18764890 | SYNCHRONIZATION SIGNAL TRANSMISSION METHOD AND SERIAL COMMUNICATION SYSTEM | BARTELS, CHRISTOPHER A. | 2184 | §103 | Non-Final OA | 22d | Pending | Jul 05, 2024 |
| 18760314 | CAPACITOR | RAMASWAMY, ARUN | 2847 | §102§103 | Final Rejection | 33d | Pending | Jul 01, 2024 |
| 18747608 | ETCHING METHOD FOR SEMICONDUCTOR STRUCTURE COMPRISING SUBSTRATE, FIRST STRUCTURE LOCATED ON PART OF TOP SURFACE OF THE SUBSTRATE, SIDEWALLS STRUCTURE AND FIELD EFFECT TRANSISTOR | GRAHAM, KRETELIA | 2817 | §102§103§112 | Non-Final OA | — | Pending | Jun 19, 2024 |
| 18387153 | MAGNETIC ELEMENT, MANUFACTURING METHOD AND POWER SUPPLY CIRCUIT THEREOF | BARNES, MALCOLM | 2837 | §102§103§112 | Non-Final OA | — | Pending | Nov 06, 2023 |
| 18386302 | INDUCTOR, MANUFACTURING METHOD FOR INDUCTOR, ENCAPSULATION MODULE, AND MANUFACTURING METHOD FOR ENCAPSULATION MODULE | BARNES, MALCOLM | — | §102§103§112 | Non-Final OA | — | Pending | Nov 02, 2023 |
| 18141510 | STACKED PACKAGING STRUCTURE AND POWER CONVERTER | BAIG, ANEESA RIAZ | 2814 | §103 | Non-Final OA | 20d | Pending | May 01, 2023 |
| 18131952 | SEMICONDUCTOR DEVICE WITH FIELD OXIDE LAYER AND METHOD FOR MANUFACTURING THE SAME | MALEK, MALIHEH | 2813 | §103§112Other | Final Rejection | 7d | Pending | Apr 07, 2023 |
| 18118243 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME | GRAHAM, KRETELIA | 2817 | §103§112 | Final Rejection | 33d | Pending | Mar 07, 2023 |
| 17743646 | POWER CONVERTER | TRAN, NGUYEN | 2838 | §103 | Final Rejection | 132d overdue | Pending | May 13, 2022 |
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Start Free TrialSilergy Semiconductor Technology (Hangzhou) Ltd. has 12 pending office actions as of October 2026, spread across 8 art units and 10 examiners.
Kretelia Graham has the most, with 2 of Silergy Semiconductor Technology (Hangzhou) Ltd.'s pending office actions.
Mostly Semiconductors, Circuits & Optics (USPTO Tech Center 2800), based on where its pending office actions are examined.
