Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species I, Claims 1-18 in the reply filed on 11/25/2025 is acknowledged.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 4-6, 16, 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mao et al.(US 20090200590 A1, hereafter Mao).
Regarding Claim 1, Mao discloses:
An image sensor(Fig. 5, 6) comprising:
A charge accumulation region(Fig. 5 [518]) having a first conductivity type(N-type, See paragraph 0033) disposed in a substrate(Fig. 5 [504]);
A charge storage region(Fig. 5 [526]) having the first conductivity type(N-type, See paragraph 0033) and disposed in the substrate(Fig. 5 [504]) to be laterally spaced apart from the charge accumulation region(Fig. 5 [518]);
A transfer gate electrode(Fig. 5 [520]) disposed on a channel region(Fig. 5 See figure below) between the charge accumulation region(Fig. 5 [518]) and the charge storage region(Fig. 5 [526]) to transfer a charge from the charge accumulation region(Fig. 5 [518]) to the charge storage region(Fig. 5 [526], See paragraph 0033);
A first well region(Fig. 5 [512]) having a second conductivity type(P-type, See paragraph 0032) and disposed below the charge storage region(Fig. 5 [526]) to inhibit a charge generated below the charge storage region(Fig. 5 [526]) from being moved to the charge storage region(Fig. 5 [526]); and
A second well region(Fig. 5 [508]) having the second conductivity type(See paragraph 0032) and disposed below a portion of one side of the first well region(Fig. 5 [512]) adjacent to a neighboring image cell(See plurality of image cells Fig. 6 [610/620/630]).
Regarding Claim 4, Mao further discloses:
A third well region(Fig. 5 [524]) having the first conductivity type(N-type) and disposed below the first well region(fig. 5 [512]).
Regarding Claim 5, Mao further discloses:
The third well region(Fig. 5 [524]) is electrically connected to the charge accumulation region(Fig. 5 [518]).
Regarding Claim 6, Mao further discloses:
The third well region(Fig. 5 [524]) has an impurity concentration lower than that of the charge accumulation region(Fig. 5 [518], See paragraph 0027).
Regarding Claim 16, Mao discloses:
An image sensor(Fig. 5, 6) comprising:
A charge accumulation region(Fig. 5 [518]) having a first conductivity type(N-type, See paragraph 0033) and disposed in a substrate(Fig. 5 [504]);
A charge storage region(Fig. 5 [526]) having the first conductivity type(N-type, See paragraph 0033) and disposed in the substrate(Fig. 5 [504]) to be laterally spaced apart from the charge accumulation region(Fig. 5 [518]);
A transfer gate electrode(Fig. 5 [520]) disposed on a channel region(Fig. 5 See figure below) between the charge accumulation region(Fig. 5 [518]) and the charge storage region(Fig. 5 [526]) to transfer a charge from the charge accumulation region(Fig. 5 [518]) to the charge storage region(Fig. 5 [526], See paragraph 0033);
A first well region(Fig. 5 [512]) having a second conductivity type(P-type, See paragraph 0032) and disposed below the charge storage region(Fig. 5 [526]) to inhibit a charge generated below the charge storage region(Fig. 5 [526]) from being moved to the charge storage region(Fig. 5 [526]); and
A second well region(Fig. 5 [508]) having the second conductivity type(See paragraph 0032) and disposed below a portion of one side of the first well region(Fig. 5 [512]) adjacent to the charge accumulation region(Fig. 5 [518]).
Regarding Claim 18, Mao further discloses:
A third well region(Fig. 5 [524]) having the first conductivity type(N-type) and disposed below the first well region(fig. 5 [512]).
PNG
media_image1.png
708
805
media_image1.png
Greyscale
Above: Fig. 5 of Mao with the channel region denoted by examiner.
Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jangjian et al.(US 20150041851 A1, hereafter Jangjian).
Regarding Claim 1, Jangjian discloses:
An image sensor(Fig. 7) comprising:
A charge accumulation region(Fig. 7 [28]) having a first conductivity type(N-type, See paragraph 0009) disposed in a substrate(Fig. 7 [22]);
A charge storage region(Fig. 7 [62]) having the first conductivity type(See paragraph 0021) and disposed in the substrate(Fig. 7 [22]) to be laterally spaced apart from the charge accumulation region(Fig. 7 [28]);
A transfer gate electrode(Fig. 7 [50]) disposed on a channel region(Fig. 7 [37], See paragraph 0023) between the charge accumulation region(Fig. 7 [28]) and the charge storage region(Fig. 7 [62]) to transfer a charge from the charge accumulation region(Fig. 7 [28]) to the charge storage region(Fig. 7 [62], See paragraph 0023);
A first well region(Fig. 7 [38]) having a second conductivity type(P-type, See paragraph 0015) and disposed below the charge storage region(Fig. 7 [62]) to inhibit a charge generated below the charge storage region(Fig. 7 [62]) from being moved to the charge storage region(Fig. 7 [62]); and
A second well region(Fig. 7 [40]) having the second conductivity type(P-type) and disposed below a portion of one side of the first well region(Fig. 7 [38]) adjacent to a neighboring image cell(See paragraph 0024, “plurality of image sensor chips”).
Claim(s) 1-3, 16-17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Baek et al.(US 20220013552 A1, hereafter Baek).
Regarding Claim 1, Baek discloses:
An image sensor(Fig. 11) comprising:
A charge accumulation region(Fig. 11 [124a]) having a first conductivity type(N-type, See Fig. 11) disposed in a substrate(Fig. 11 [100])
A charge storage region(Fig. 11 [FD1]) having the first conductivity type(N-type) and disposed in the substrate(Fig. 11 [100]) to be laterally spaced apart from the charge accumulation region(Fig. 11 [124a]);
A transfer gate electrode(Fig. 11 [TG1R]) disposed on a channel region(Fig. 11 [CH2]) between the charge accumulation region(Fig. 11 [124a]) and the charge storage region(Fig. 11 [FD1]) to transfer a charge from the charge accumulation region(Fig. 11 [124a]) to the charge storage region(Fig. 11 [FD1]);
A first well region(Fig. 11 [134]) having a second conductivity type(P-type) and disposed below the charge storage region(Fig. 11 [FD1]) to inhibit a charge generated below the charge storage region(Fig. 11 [FD1]) from being moved to the charge storage region(Fig. 11 [FD1]); and
A second well region(Fig. 11 [136]) having the second conductivity type(P-type) and disposed below a portion of one side of the first well region(Fig. 11 134]) adjacent to a neighboring image cell(See Fig. 11 below).
Regarding Claim 2, Baek further discloses:
The second well region(Fig. 11 [136]) has an impurity concentration lower than that of the first well region(Fig. 11 [134]).
Regarding Claim 3, Baek further discloses:
The substrate(Fig. 11 [100]) has the second conductivity type(P-type, See paragraph 0053) and has an impurity concentration lower than that of the second well region(“lightly doped with P-type impurities”).
Regarding Claim 16, Baek discloses:
An image sensor(Fig. 11) comprising:
A charge accumulation region(Fig. 11 [124a]) having a first conductivity type(N-type, See Fig. 11) disposed in a substrate(Fig. 11 [100])
A charge storage region(Fig. 11 [FD1]) having the first conductivity type(N-type) and disposed in the substrate(Fig. 11 [100]) to be laterally spaced apart from the charge accumulation region(Fig. 11 [124a]);
A transfer gate electrode(Fig. 11 [TG1R]) disposed on a channel region(Fig. 11 [CH2]) between the charge accumulation region(Fig. 11 [124a]) and the charge storage region(Fig. 11 [FD1]) to transfer a charge from the charge accumulation region(Fig. 11 [124a]) to the charge storage region(Fig. 11 [FD1]);
A first well region(Fig. 11 [134]) having a second conductivity type(P-type) and disposed below the charge storage region(Fig. 11 [FD1]) to inhibit a charge generated below the charge storage region(Fig. 11 [FD1]) from being moved to the charge storage region(Fig. 11 [FD1]); and
A second well region(Fig. 11 [136]) having the second conductivity type(P-type) and disposed below a portion of one side of the first well region(Fig. 11 134]) adjacent to the charge accumulation region(Fig. 11 [124a]).
Regarding Claim 17, Baek further discloses:
The second well region(Fig. 11 [136]) has an impurity concentration lower than that of the first well region(Fig. 11 [134]), and
The substrate(Fig. 11 [100]) has the second conductivity type(P-type, See paragraph 0053) and has an impurity concentration lower than that of the second well region(“lightly doped with P-type impurities”).
PNG
media_image2.png
845
855
media_image2.png
Greyscale
Above: Fig. 11 of Baek with neighboring image cell denoted by examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7-12, 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jangjian in view of Kim(US 20070145365 A1, hereafter Kim).
Regarding Claim 7, Jangjian discloses an alternative embodiment of Fig. 7 that involves the creation of a front side illumination image sensor wafer, which includes metal layers, color filters, and micro lenses formed on the front side(See paragraph 0025 of Baek).
Jangjian does not teach or disclose a first dummy pattern disposed on a surface portion of the substrate between the charge storage region and a charge accumulation region of the neighboring image cell and configured to inhibit light from entering the charge storage region from the neighboring image cell.
In the same field of endeavor, Kim discloses a dummy pattern(Fig. 2c [241]) disposed on a surface portion of the substrate(Fig. 2c [200]) between the charge storage region(Fig. 2c see figure below) and a charge accumulation region(Fig. 2c [251/252]) of the neighboring image cell(Fig. 2c see figure below) and configured to inhibit light(Fig. 2c See figure below) from entering the charge storage region(Fig. 2c see figure below) from the neighboring image cell(Fig. 2c see figure below).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to modify the device disclosed by Jangjian along the lines of Kim. One might have been motivated to add a dummy gate to the device disclosed by Jangjian in order to increase the light collection efficiency of the cell by redirecting light from a lens towards the photodiode(See Fig. 2c of Kim, Paragraph 0033). Performing this modification would have generated a predictable result in the creation of Jangjian’s device with a dummy gate atop a shallow isolation(See Fig. 7 [36] of Jangjian) structure.
Regarding Claim 8,
Jangjian discloses a transfer gate(Fig. 7 [50]).
Jangjian does not teach or disclose a dummy gate pattern made of a same material as the transfer gate electrode.
In the same field of endeavor, Kim discloses a transfer gate electrode(Fig. 2c [242]) and dummy pattern(Fig. 2c [241]) formed both of polysilicon(See paragraph 0017).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to produce Jangjian’s device along the lines of Kim such that Jangjians’ device included a dummy gate comprising a same material as a transfer gate. With consideration of including a dummy pattern, which is discussed in the rejection of claim 7, one of ordinary skill in the art would then look to Kim or the other prior art to determine the steps by which to form this dummy gate and the material to use. The most natural choice would be to continue following Kim’s teaching, which discloses the patterning of a single polysilicon to form both the transfer and dummy gate electrodes(See paragraph 0017). Performing this modification would have generated a predictable result in the creation of Jangjian’s device with a dummy gate atop a shallow isolation(See Fig. 7 [36] of Jangjian) structure.
Regarding Claim 9,
Jangjian discloses an insulating layer(Fig. 7 [72]) disposed on the substrate(Fig. 7 [22]) and the transfer gate electrode(Fig. 7 [50]).
Jangjian does not teach or disclose the insulating layer disposed on the dummy pattern and a light shield layer disposed on the insulating layer and configured to inhibit light from entering the charge storage region.
In the same field of endeavor, Kim discloses an insulating layer(Fig. 2c [261]) disposed on a dummy pattern(Fig. 2c [241]) and a light shield layer(Fig. 2c [262]) on the insulating layer(Fig. 2c [261]) and configured to inhibit light from entering the charge storage region(See paragraph 0007, “the photodiode may be exposed by forming an opening in the interlayer dielectric”).
It would have been further obvious to one of ordinary skill in the art at the time the application at hand to produce the device disclosed by Jangjian along the lines of Kim. One might have been motivated to produce Kim’s light shield layer on Jangjian’s device in order to shield their drain region from unwanted light, which could potentially create unwanted charge flow when the transfer gate is not turned on. Performing this modification would have generated a predictable result in an embodiment of Jangjian’s device with a light shielding layer as disclosed by Kim.
Regarding Claim 10,
Claim 9 is rejected under 35 U.S.C. 103(See above rejection).
Jangjian does not teach or disclose a first light shield pattern disposed between the first dummy pattern and the light shield layer and configured to pass through the insulating layer.
In the same field of endeavor, Kim discloses a first light shield pattern(Fig. 2c [261], See figure below) disposed between the first dummy pattern(Fig. 2c [241]) and the light shield layer(Fig. 2c [262]) and configured to pass through the insulating layer(Fig. 2c [263]).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to further modify the device disclosed by Jangjian along the lines of Kim. One might have been motivated to include the light shielding pattern as shown by Kim in order to focus light towards the photodiode specifically, in order to improve the sensitivity of the area of the diode. Performing this modification would have generated a predictable result in the creation of an embodiment of Jangjian’s device with a light shielding layer as disclosed by Kim.
Regarding Claim 11,
Claim 10 is rejected under 35 U.S.C. 103(See above rejection).
Jangjian does not teach or disclose a second light shield pattern extending from a first edge portion of the light shield layer adjacent to the neighboring image cell toward the substrate.
In the same field of endeavor, Kim discloses a second light shield pattern(Fig. 2c [261], See figure below) extending from a first edge portion of the light shield layer adjacent to the neighboring image cell(See Fig. 2c below) toward the substrate(Fig. 2c [200]).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to further modify the device disclosed by Jangjian along the lines of Kim. One might have been motivated to include the second light shielding pattern as shown by Kim in order to focus light towards the photodiode specifically, in order to improve the sensitivity of the area of the diode. Performing this modification would have generated a predictable result in the creation of an embodiment of Jangjian’s device with a second light shielding pattern as disclosed by Kim.
Regarding Claim 12,
Claim 10 is rejected under 35 U.S.C. 103(See above rejection).
Jangjian does not teach or disclose a third light shield pattern extending from a second edge portion of the light shield layer adjacent to the charge accumulation region toward the substrate.
In the same field of endeavor, Kim discloses a third light shield pattern(Fig. 2c [261], See figure below) extending from a second edge portion of the light shield layer adjacent to the charge accumulation region(Fig. 2c [251]) toward the substrate(Fig. 2c [200])
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to further modify the device disclosed by Jangjian along the lines of Kim. One might have been motivated to include the third light shielding pattern as shown by Kim in order to focus light towards the photodiode specifically, in order to improve the sensitivity of the area of the diode. Performing this modification would have generated a predictable result in the creation of an embodiment of Jangjian’s device with a third light shielding pattern as disclosed by Kim.
Regarding Claim 14, Jangjian discloses a cell isolation region(Fig. 7 [36]) disposed in the surface portion of the substrate(Fig. 7 [22]) between the charge storage region(Fig. 7 [62]) and the charge accumulation region(See Fig. 7 below) of the neighboring image cell.
Jangjian does not teach or disclose a first dummy pattern disposed on the cell isolation region.
In the same field of endeavor, Kim discloses a dummy pattern(Fig. 2c [241]) disposed on a surface portion of the substrate(Fig. 2c [200]) between the charge storage region(Fig. 2c see figure below) and a charge accumulation region(Fig. 2c [251/252]) of the neighboring image cell(Fig. 2c see figure below) and disposed on a cell isolation region(Fig. 2c [220]).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to modify the device disclosed by Jangjian along the lines of Kim. One might have been motivated to add a dummy gate to the device disclosed by Jangjian in order to increase the light collection efficiency of the cell by redirecting light from a lens towards the photodiode(See Fig. 2c of Kim, Paragraph 0033). A most natural place to position the dummy gate would be in the manner Kim positioned it, that is atop the shallow isolation region 36 of Fig. 7 of Jangjian. Performing this modification would have generated a predictable result in the creation of Jangjian’s device with a dummy gate atop a shallow isolation(See Fig. 7 [36] of Jangjian) structure.
PNG
media_image3.png
815
1001
media_image3.png
Greyscale
Above: Fig. 2c of Kim with the light shield patterns, neighboring image cell, and charge storage region denoted by examiner.
PNG
media_image4.png
609
662
media_image4.png
Greyscale
Above: Fig. 7 of Jangjian with the neighboring image cell denoted by examiner.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jangjian and Kim, further in view of Ahn et al.(US 20120009719 A1, hereafter Ahn).
Regarding Claim 13,
Claim 9 is rejected under 35 U.S.C. 103(See above rejection).
Neither Jangjian nor Kim teach or disclose a second insulating layer disposed on the insulating layer and the light shield layer;
Interlayer insulating layers disposed on the second insulating layer;
Metal wiring layers disposed among the interlayer insulating layers; and
A light guide pattern configured to pass through the interlayer insulating layers and to correspond to the charge accumulation region.
In the same field of endeavor, Ahn discloses:
a second insulating layer(Fig. 4F [141]) disposed on the insulating layer(Fig. 4F [140]) and the light shield layer(Fig. 4F [150]);
Interlayer insulating layers(Fig. 4F [142/143/144]) disposed on the second insulating layer(Fig. 4 [141]);
Metal wiring layers(Fig. 4F [161/163]) disposed among the interlayer insulating layers(Fig. 4F [142/143/144]); and
A light guide pattern(Fig. 4F [C1/C2]) configured to pass through the interlayer insulating layers(Fig. 4F [142/143/144]) and to correspond to the charge accumulation region(Fig. 4F [130]).
It would have been further obvious to modify the device disclosed by Jangjian and Kim along the lines of Ahn. One might have been motivated to include the structure disclosed by Ahn in order to operate the sensor, as a front side illuminated device would require such a structure positioned above its transfer transistor and photodiode in order to operate. Performing this modification would have generated a predictable result in the device disclosed by Jangjian and Kim, with the further structural features disclosed by Ahn resulting in an operable image sensor device.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jangjian and Kim, further in view of Park et al.(US 20190165018 A1, hereafter Park).
Regarding Claim 15,
Claim 7 is rejected under 35 U.S.C. 103(See above rejection).
Neither Jangjian nor Kim teach or disclose a second dummy pattern disposed on the charge storage region and configured to inhibit light from entering the charge storage region; and
An insulating layer disposed between the charge storage region and the second dummy pattern and configured to electrically insulate the charge storage region from the second dummy pattern.
In the same field of endeavor, Park discloses a second dummy pattern(Fig. 12 [D1]) disposed on the charge storage region(Fig. 12 [206]) and configured to inhibit light from entering the charge storage region(Fig. 12 [206], the dummy pattern and spacers physically block light); and
An insulating layer(Fig. 12 [222]) disposed between the charge storage region(Fig. 12 [206]) and the second dummy pattern(Fig. 12 [D1]) and configured to electrically insulate the charge storage region(Fig. 12 [206]) from the second dummy pattern(Fig. 12 [D1]).
It would have been further obvious to modify the device disclosed by Jangjian and Kim further along the lines of Park. One might have been motivated to add Park’s second dummy pattern in order to use a process for forming a doped region(See paragraph 0120 of Park) of the resulting device. Performing this modification would have generated a predictable result in the creation of a second dummy structure over the charge storage region of the device disclosed by Jangjian and Kim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Mcgrath(US 20230154947 A1) discloses a multi-well floating diffusion region. Huang(US 20210193712 A1) discloses a backside illuminated image sensor with multiple wells. Uya et al.(US 20080283726 A1) discloses a plurality of wells below a charge storage region.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARSHALL MU-NUO HATFIELD whose telephone number is (703)756-1506. The examiner can normally be reached Mon-Thus 11:00 AM-9:00PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached at 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/MARSHALL MU-NUO HATFIELD/Examiner, Art Unit 2897