Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 04/15/2026, See page 9, Paragraph 1, of applicant’s remarks, in regards to the rejection(s) of Claim 7(Now amended claim 1) under 35 U.S.C. 103 over Jangjian(US 20150041851 A1, hereafter Jangjian) in view of Kim(US 20070145365 A1, hereafter Kim) have been fully considered but do not place the application in the conditions for allowance. This is on grounds that the dummy pattern of the present application differs from Kim’s dummy gate in terms of purpose, effect, and structure. Firstly, see Page 10, final paragraph, wherein applicant argues that Kim’s dummy gate is not a component for preventing light from entering a charge storage region from an adjacent image cell. This may be true in the sense that Kim’s dummy gate is not intended by Kim to prevent light from entering a charge storage region from an adjacent image cell. This may be true; however, a determination on patentability must be based on the structure implied by a functional limitation, and not that function itself, or else multiple of a same structure, but used in different ways, would find their way towards patentability. Therefore, the examiner’s contention on the applicant’s arguments is based on the fact that Kim’s dummy gate structure would necessarily result in a structure which prevents light from entering a charge storage region from an adjacent image cell.
For clarity, the term “from an adjacent image cell” is interpreted as “from a space vertically above an adjacent image cell” as one would not expect light to literally pass from an adjacent image cell towards the present image cell. Furthermore, with the understanding that an adjacent image cell is not literally producing light, it can be understood that “a structure which prevents light from entering a charge storage region from an adjacent image cell” is a structure which prevents light from entering a charge storage region from a direction lateral to said region. Therefore, the effect and structure of this dummy gate from Kim is the same. A polysilicon dummy gate in the configuration given by Kim is not transparent, thus it prevents light from entering from a lateral direction relative to the charge storage region, whether or not Kim intends it to.
Finally, the contention that there is no adjacent image cell in Kim is true in that there is no explicit mention of an adjacent image cell by Kim. However, there are two issues with using this as a grounds against the present rejection. Firstly, the prior art of sensors involving photodiodes use arrays of many image cells in a grid, as this is a way in the art of creating an image sensor. In the light of the prior art, it would be unusual to interpret Kim’s device as a single image cell. It would be far more reasonable to assume that Kim’s image cell is involved in an array of photodiode image cells, as is the general way by which these sensors are constructed. Secondly, the limitation is that this dummy gate is “configured to” block light from an adjacent image cell, but that does not require this neighboring image cell to exist. A component can be configured to perform a function involving another component, even if that second component is not present. For these reasons the contention that there is no neighboring image cell disclosed by Kim is unconvincing. Updated rejections are below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 8-12, 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jangjian in view of Kim.
Regarding Claim 1, Jangjian discloses: An image sensor(Fig. 7) comprising:
A charge accumulation region(Fig. 7 [28]) having a first conductivity type(N-type, See paragraph 0009) disposed in a substrate(Fig. 7 [22]);
A charge storage region(Fig. 7 [62]) having the first conductivity type(See paragraph 0021) and disposed in the substrate(Fig. 7 [22]) to be laterally spaced apart from the charge accumulation region(Fig. 7 [28]);
A transfer gate electrode(Fig. 7 [50]) disposed on a channel region(Fig. 7 [37], See paragraph 0023) between the charge accumulation region(Fig. 7 [28]) and the charge storage region(Fig. 7 [62]) to transfer a charge from the charge accumulation region(Fig. 7 [28]) to the charge storage region(Fig. 7 [62], See paragraph 0023);
A first well region(Fig. 7 [38]) having a second conductivity type(P-type, See paragraph 0015) and disposed below the charge storage region(Fig. 7 [62]) to inhibit a charge generated below the charge storage region(Fig. 7 [62]) from being moved to the charge storage region(Fig. 7 [62]); and
A second well region(Fig. 7 [40]) having the second conductivity type(P-type) and disposed below a portion of one side of the first well region(Fig. 7 [38]) adjacent to a neighboring image cell(See paragraph 0024, “plurality of image sensor chips”).
Jangjian also discloses an alternative embodiment of Fig. 7 that involves the creation of a front side illumination image sensor wafer, which includes metal layers, color filters, and micro lenses formed on the front side(See paragraph 0025 of Jangjian).
Jangjian does not teach or disclose a first dummy pattern disposed on a surface portion of the substrate between the charge storage region and a charge accumulation region of the neighboring image cell and configured to inhibit light from entering the charge storage region from the neighboring image cell.
In the same field of endeavor, Kim discloses a dummy pattern(Fig. 2c [241]) disposed on a surface portion of the substrate(Fig. 2c [200]) between the charge storage region(Fig. 2c see figure below) and a charge accumulation region(Fig. 2c [251/252]) of the neighboring image cell(Fig. 2c see figure below) and configured to inhibit light(Fig. 2c See figure below) from entering the charge storage region(Fig. 2c see figure below) from the neighboring image cell(Fig. 2c see figure below).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to modify the device disclosed by Jangjian along the lines of Kim. One might have been motivated to add a dummy gate to the device disclosed by Jangjian in order to increase the light collection efficiency of the cell by redirecting light from a lens towards the photodiode(See Fig. 2c of Kim, Paragraph 0033). Performing this modification would have generated a predictable result in the creation of Jangjian’s device with a dummy gate atop a shallow isolation(See Fig. 7 [36] of Jangjian) structure. For further explanation, as discussed above, the configuration of Kim’s dummy gate to inhibit light from entering the charge storage region from a neighboring image cell does not depend on Kim’s intention of doing so, nor does it necessarily depend on Kim’s disclosure of an actual neighboring image cell. Whether or not Kim’s dummy gate is configured to inhibit light from entering from a neighboring image cell is entirely dependent on the structural features of Kim’s dummy gate, of which Kim’s dummy gate as disclosed by Kim would inhibit light from entering from a neighboring image cell.
Regarding Claim 2, Jangjian further discloses:
A second well region(Fig. 7 [40]) with an impurity concentration(See paragraph 0011) and a first well region(Fig. 7 [38], See paragraph 0015).
Jangjian discloses the second well region having an impurity concentration between 1014 and 1018/cm3, as well as the first well region having an impurity concentration between 1014 and 1018/cm3. This means that in some embodiments, the concentration of the impurities of the first well will be higher than that of the second well. Thus, one of ordinary skill in the art would have arrived at the claimed limitation as a matter of routine device optimization or experimentation with embodiments of Jangjian’s device.
Regarding Claim 3, Jangjian discloses:
A substrate(Fig. 7 [22]).
Jangjian does not explicitly disclose the substrate has an impurity concentration lower than that of the second well region.
However, one of ordinary skill in the art would understand the substrate of Fig. 7 22 as having a lower impurity concentration than the regions created in that substrate as those regions are create by the implantation of impurities(See paragraphs 0015-0016).
Thus, the only property not disclosed by Jangjian is the the second type(p-type in the context of Jangjian) conductivity of the substrate.
In the same field of endeavor, Mao discloses a substrate(Fig. 2c [200/210], See paragraph 0006) with a P- epi layer(Fig. 2c [210]).
It would have been further obvious to one of ordinary skill in the art at the time the application at hand was filed to modify the device disclosed by Jangjian along the lines of Kim. One might have been motivated to include a P- type substrate in order to further isolate the existing photodiode from charges forming below the photoactive area of the sensor. Performing this modification would have generated a predictable result in Jangjian’s device with a p- type substrate.
Regarding Claim 4, Jangjian further discloses:
A third well region(Fig. 7 [26]) having the first conductivity type(n-type, See paragraph 0009) and disposed below the first well region(Fig. 7 [38]).
Regarding Claim 5, Jangjian further discloses:
The third well region(Fig. 7 [26]) is electrically connected to the charge accumulation region(Fig. 7 [28]).
Regarding Claim 6, Jangjian further discloses:
The third well region(Fig. 7 [26]) has an impurity concentration lower than that of the charge accumulation region(Fig. 7 [28], See paragraph 0012).
The rejections for claims 8-12, 14 are substantially the same for those laid out in the Non-final office action, dated 01/15/2026.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jangjian and Kim, further in view of Ahn et al.(US 20120009719 A1, hereafter Ahn).
Regarding Claim 13,
Claim 9 is rejected under 35 U.S.C. 103(See above rejection).
Neither Jangjian nor Kim teach or disclose a second insulating layer disposed on the insulating layer and the light shield layer;
Interlayer insulating layers disposed on the second insulating layer;
Metal wiring layers disposed among the interlayer insulating layers; and
A light guide pattern configured to pass through the interlayer insulating layers and to correspond to the charge accumulation region.
In the same field of endeavor, Ahn discloses:
a second insulating layer(Fig. 4F [141]) disposed on the insulating layer(Fig. 4F [140]) and the light shield layer(Fig. 4F [150]);
Interlayer insulating layers(Fig. 4F [142/143/144]) disposed on the second insulating layer(Fig. 4 [141]);
Metal wiring layers(Fig. 4F [161/163]) disposed among the interlayer insulating layers(Fig. 4F [142/143/144]); and
A light guide pattern(Fig. 4F [C1/C2]) configured to pass through the interlayer insulating layers(Fig. 4F [142/143/144]) and to correspond to the charge accumulation region(Fig. 4F [130]).
It would have been further obvious to modify the device disclosed by Jangjian and Kim along the lines of Ahn. One might have been motivated to include the structure disclosed by Ahn in order to operate the sensor, as a front side illuminated device would require such a structure positioned above its transfer transistor and photodiode in order to operate. Performing this modification would have generated a predictable result in the device disclosed by Jangjian and Kim, with the further structural features disclosed by Ahn resulting in an operable image sensor device.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jangjian and Kim, further in view of Park et al.(US 20190165018 A1, hereafter Park).
Regarding Claim 15,
Claim 1 is rejected under 35 U.S.C. 103(See above rejection).
Neither Jangjian nor Kim teach or disclose a second dummy pattern disposed on the charge storage region and configured to inhibit light from entering the charge storage region; and
An insulating layer disposed between the charge storage region and the second dummy pattern and configured to electrically insulate the charge storage region from the second dummy pattern.
In the same field of endeavor, Park discloses a second dummy pattern(Fig. 12 [D1]) disposed on the charge storage region(Fig. 12 [206]) and configured to inhibit light from entering the charge storage region(Fig. 12 [206], the dummy pattern and spacers physically block light); and
An insulating layer(Fig. 12 [222]) disposed between the charge storage region(Fig. 12 [206]) and the second dummy pattern(Fig. 12 [D1]) and configured to electrically insulate the charge storage region(Fig. 12 [206]) from the second dummy pattern(Fig. 12 [D1]).
It would have been further obvious to modify the device disclosed by Jangjian and Kim further along the lines of Park. One might have been motivated to add Park’s second dummy pattern in order to use a process for forming a doped region(See paragraph 0120 of Park) of the resulting device. Performing this modification would have generated a predictable result in the creation of a second dummy structure over the charge storage region of the device disclosed by Jangjian and Kim.
Claim(s) 16, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mao et al.(US 20090200590 A1, hereafter Mao) in view of Kim.
An image sensor(Fig. 1) comprising:
A charge accumulation region(Fig. 1 [118]) having a first conductivity type(N-type, See paragraph 0019) and disposed in a substrate(Fig. 1 [104]);
A charge storage region(Fig. 1 [126]) having the first conductivity type(N-type, See paragraph 0019) and disposed in the substrate(Fig. 1 [104]) to be laterally spaced apart from the charge accumulation region(Fig. 3 [318]);
A transfer gate electrode(Fig. 1 [120]) disposed on a channel region(Fig. 1 See figure below) between the charge accumulation region(Fig. 1 [118]) and the charge storage region(Fig. 1 [126]) to transfer a charge from the charge accumulation region(Fig. 1 [118]) to the charge storage region(Fig. 1 [126], See paragraph 0019);
A first well region(Fig. 1 [112]) having a second conductivity type(P-type, See paragraph 0019) and disposed below the charge storage region(Fig. 1 [126]) to inhibit a charge generated below the charge storage region(Fig. 1 [126]) from being moved to the charge storage region(Fig. 1 [126]); and
A second well region(Fig. 1 [108]) having the second conductivity type(See paragraph 0019) and disposed below a portion of one side of the first well region(Fig. 1 [112]) adjacent to the charge accumulation region(Fig. 1 [118]).
Mao does not teach or disclose a first dummy pattern disposed on a surface portion of the substrate between the charge storage region and a charge accumulation region of the neighboring image cell and configured to inhibit light from entering the charge storage region from the neighboring image cell.
In the same field of endeavor, Kim discloses a dummy pattern(Fig. 2c [241]) disposed on a surface portion of the substrate(Fig. 2c [200]) between the charge storage region(Fig. 2c see figure below) and a charge accumulation region(Fig. 2c [251/252]) of the neighboring image cell(Fig. 2c see figure below) and configured to inhibit light(Fig. 2c See figure below) from entering the charge storage region(Fig. 2c see figure below) from the neighboring image cell(Fig. 2c see figure below).
It would have been obvious to one of ordinary skill in the art at the time the application at hand was filed to modify the device disclosed by Mao along the lines of Kim. One might have been motivated to add a dummy gate to the device disclosed by Mao in order to increase the light collection efficiency of the cell by redirecting light from a lens towards the photodiode(See Fig. 2c of Kim, Paragraph 0033). Performing this modification would have generated a predictable result in the creation of Mao’s device with a dummy gate atop a shallow isolation(See Fig. 1 [116] of Mao) structure. For further explanation, as discussed above, the configuration of Kim’s dummy gate to inhibit light from entering the charge storage region from a neighboring image cell does not depend on Kim’s intention of doing so, nor does it necessarily depend on Kim’s disclosure of an actual neighboring image cell. Whether or not Kim’s dummy gate is configured to inhibit light from entering from a neighboring image cell is entirely dependent on the structural features of Kim’s dummy gate, of which Kim’s dummy gate as disclosed by Kim would inhibit light from entering from a neighboring image cell.
Regarding Claim 18,
Mao discloses a third well region(Fig. 3 [324]) having the first conductivity(p-type) disposed below a first well region(Fig. 3 [312]).
It would have been obvious to combine the embodiment disclosed by Mao with the embodiment disclosed by Mao as being of the prior art. One might have been motivated to include Mao’s diffusion region in order to improve the retention of the photo-generated electrons(See paragraph 0028). Performing this modification would have generated a predictable result in Fig. 1 of Mao with a diffusion region and/or Fig. 3 of Mao with the deep-P well presented by Mao as prior art.
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mao and Kim, further in view of Jangjian.
Regarding Claim 17, Mao discloses:
The substrate(Fig. 1 [104]) has the second conductivity type(p-type) and an impurity concentration lower than that of the second well region(Fig. 1 [108]).
While not explicitly stated, as the wells are formed in the epitaxial layer 104 via ion implantation, one of ordinary skill in the art would expect the p-type epitaxial layer to have a lower p-type impurity concentration than that of the wells.
Mao does not teach or disclose the second well region has an impurity concentration lower than that of the first well region.
In the same field of endeavor, Jangjian discloses the second well region having an impurity concentration between 1014 and 1018/cm3, as well as the first well region having an impurity concentration between 1014 and 1018/cm3(See paragraphs 0011, 0015 of Jangjian). This means that in some embodiments, the concentration of the impurities of the first well will be higher than that of the second well. Thus, one of ordinary skill in the art would have arrived at the claimed limitation as a matter of routine device optimization or experimentation with embodiments of Mao’s device, provided with the guidance of Jangjian.
PNG
media_image1.png
815
1001
media_image1.png
Greyscale
Above: Fig. 2c of Kim with the light shield patterns, neighboring image cell, and charge storage region denoted by examiner.
PNG
media_image2.png
747
793
media_image2.png
Greyscale
Above: Fig. 1 of Mao with the channel region denoted by examiner.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Mcgrath(US 20230154947 A1) discloses a multi-well floating diffusion region. Huang(US 20210193712 A1) discloses a backside illuminated image sensor with multiple wells. Uya et al.(US 20080283726 A1) discloses a plurality of wells below a charge storage region.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
For clarification, the addition of the limitations of old claim 7 into claims 1 and 16 means that all claims dependent on 1 or 16 now have a scope in line with the limitations of the old claim 7, which was not the case before.
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARSHALL MU-NUO HATFIELD whose telephone number is (703)756-1506. The examiner can normally be reached Mon-Thus 11:00 AM-9:00PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached at 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897
/MARSHALL MU-NUO HATFIELD/Examiner, Art Unit 2897
Prosecution Insights