DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
An amendment filed on 12/30/2025 in response to the Office Action mailed on 10/01/2025 is
being acknowledged and entered into the record. The present Final rejection is made by taking into
fully consideration all the amendments.
Response to Arguments
Applicant’s arguments, see page 7 of the remarks, filed on 12/30/2025, with respect to the objection of the drawings have been fully considered and are persuasive. The objection of the drawings has been withdrawn.
Applicant’s arguments, see page 7 of the remarks, filed on 12/30/2025, with respect to the 112(b) rejections of Claims 1-19 have been fully considered and are persuasive. The rejections of Claims 1-19 have been withdrawn.
Applicant’s arguments, see pages 7-9 of the remarks, filed on 12/30/2025, with respect to the rejections of claims 1-5, 7 and 8 under 35 USC § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of 103 rejections are made in view of previously applied prior art reference of Ryu et al. and Melikyan in combination with the newly found reference of Sun et al. The combination of Ryu/Melikyan/Sun teach the newly added limitations of Claim 1 as outlined in the rejection below. New rejections are also made for all claims dependent on Claim 1.
On page 10 of the remarks filed on 12/20/2025, Applicant argues that while Lee teaches a cutting along the scribe lane region, it is silent as to a method to measure the thickness and therefore, the combination of reference would be silent as to the sequence of a process to measure the thickness of the die in the stack and a process to cut the stack. This argument is fully considered but is moot as Lee is no longer relied upon for the rejection of Claim 1. However, owever, the above argument is relevant for the new rejection in view of Sun et al. and hence is addressed for future references. One cannot show non-obviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). As such, the combination of Ryu, Melikyan and newly found reference of Sun teach the sequence of processes to measure the thickness of the die in the stack and a process to cut the stack as recited in Claim 1 (see rejection below).
On page 10 of the remarks filed on 12/20/2025, Applicant further argues that the modified method of Melikyan in view of Ryu based on Lee would be different from the claimed invention, because the prior art references are silent that the measurement is performed at the scribe lane region where the cutting is performed and therefore would not be an obvious modification. This argument is fully considered but is not persuasive. While Lee is no longer relied upon for the rejection of Claim 1, owever, the above argument is relevant for the new rejection in view of Sun et al. and hence is addressed for future references. Defining a scribe lane region and cutting along the scribe lane region is a routine step performed in semiconductor packages to sperate packages, expose package sidewalls or form package outlines and thus can be easily incorporated into the manufacturing process of Ryu according to the teachings of newly found reference of Sun. Further, it would have obvious to a person of ordinary skill in the art to perform the measurements within the scribe lane region.
On page 10 of the remarks filed on 12/20/2025, Applicant further argues that a cutting process of Lee, if performed to the structure of Melikyan, would inevitably damage the structure of Melikyan and thus there would be no reasonable expectation of success to make the final structure of Melikyan to be measured according to Ryu and then cut according to Lee. These arguments are fully considered but are moot as the new rejection is no longer based on a modification of Melikyan in view of Ryu and Lee but a modification of Ryu in view of Melikyan and Sun. The modification of Ryu in view Sun and Melikyan would not inevitably damage the structure of Ryu or the operation of the device of Ryu. In order words, cutting through scribed lanes defined in the structure of Ryu according to the teachings of Sun and disposing active layers, encapsulant and light-transmitting regions in the structure of Ryu according to the teachings of Melikyan would not damage the structure of Ryu.
Applicant’s arguments, see page 10 of the remarks, filed on 12/30/2025, with respect to the rejection of claim 11 under 35 USC § 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground of 103 rejection is made in view of previously applied prior art reference of Ryu et al. in combination with the newly found reference of Sun et al. The combination of Ryu/ Sun teaches the newly added limitations of Claim 11 as outlined in the rejection below. New rejections are also made for all claims dependent on Claim 11.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7, and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Ryu et al. (US 20170363418 A1), in view of Melikyan (US 11664318 B2) and Sun et al. (US 20230420330 A1).
Regarding Claim 1, Ryu et al. teaches a method of manufacturing a semiconductor package, comprising:
disposing a buffer die 12a on a support carrier 100 (see annotated Fig. 2: 12a, 100, T, paragraph 0019);
forming a plurality of memory dies 12b, 12c, 12d (see annotated Fig. 2: T, 12a, 12b, 12c, 12d, paragraph 0019);
Note that while Ryu et al. does not explicitly teach a memory die, it does teach the plurality of die 12a-12d can be any semiconductor chip (see paragraph 0003), which includes memory die. Therefore, it would have been obvious to a person of ordinary skill in the art to include a memory die in the semiconductor package of Ryu et al, as it is well known in the art to integrate memory die in semiconductor packages for improved performance.
each of the plurality of memory dies including a light-transmitting region and having a body layer and an active layer on a surface of the body layer;
stacking the plurality of memory dies 12b, 12c, 12d on the buffer die 12a in a vertical direction to form a semiconductor device T (see annotated Fig. 2: T, 12a, 12b, 12c, 12d, paragraph 0019);
measuring respective distances between the buffer die 12a and the plurality of memory dies 12b, 12c, 12d by irradiating light I1 on the semiconductor device T in the vertical direction (see annotated Fig. 2: I1, 12a, 12b, 12c, 12d, T, Fig 4A: I1, paragraph 0019, 0030);
forming a molding member encapsulating the semiconductor device,
and after measuring the respective distances, cutting through the molding member, the plurality of memory dies, the buffer die, and the support carrier such that outer side surfaces of the molding member, the buffer die, and the plurality of memory dies are coplanar with each other to form the semiconductor package,
wherein measuring the respective distances between the buffer die 12a and the plurality of memory dies 12b, 12c, 12d includes: irradiating first light I1 on a first memory die 12d positioned at an uppermost position among the plurality of memory dies 12b, 12c, 12d (see Fig. 4A: I1, annotated Fig. 2, paragraph 0030),
the first memory die having a first body layer and a first active layer, and including a first light transmitting region;
and measuring a distance d between the first memory die 12d and a second memory die 12c through first detected light I3’ (See annotated Fig. 2: I3’, paragraph 0032),
Note that in paragraph 0032 and in Fig. 4C, the measurement method is described in a sequence, where only the initial steps are explicitly stated and demonstrated. A person of ordinary skill in the art could have inferred the remaining steps by identifying the discernible pattern. For example, the light reflected from the top surface of the second memory die 12c will be the first detected light I3’, the light reflected from the top surface of the third memory die 12b will be the second detected light I5’, and so on, as shown in annotated Fig. 2 below.
wherein the second memory die 12c is positioned immediately below the first memory die 12d among the plurality of memory dies 12b, 12c, 12d (see annotated Fig. 2: 12a, 12b, 12c, 12d, paragraph 0019),
and wherein the first detected light I3’ is formed by the first light I1 sequentially passing through the first light transmitting region in a thickness direction of the first active layer, being incident on the second memory die 12c, and reflected from the second memory die 12c (See annotated Fig. 2, paragraph 0032).
and the first memory die further includes a die region and a scribe lane region surrounding the die region in a plan view, the first light transmitting region is disposed in the scribed lane region, and the cutting is along the scribe lane region, through which, the respective distances are measured before the cutting.
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Annotated Fig. 2 of Ryu et al. (US 20170363418 A1)
Melikyan teaches a method of manufacturing a semiconductor package, comprising the following limitations not disclosed in Ryu et al.:
each of the plurality of memory dies 102 including a light-transmitting region and having a body layer and an active layer 114 on a surface of the body layer (see annotated Fig. 4: 102, 114, body layer, column 6, 21-23, column 6, lines 57-64);
Note that each active layer 114 includes a supporting material layer that is light-transmitting (see column 6, lines 57-64), a portion of this layer is interpreted as the light-transmitting region.
forming a molding member 130 encapsulating the semiconductor device 100 (see annotated Fig. 4: 130, column 11, lines 24-35),
the first memory die 105a having a first body layer and a first active layer 114, and including a first light transmitting region (see annotated Fig. 4: 105a, 114, column 6, lines 15-21);
Therefore, it would have been obvious to a person of ordinary skill in the art at the time of the claimed invention to have combined the teachings of Ryu et al. and Melikyan in order to have each of the plurality of memory dies including a light-transmitting region and having a body layer and an active layer on a surface of the body layer, a step of forming a molding member encapsulating the semiconductor device, and the first memory die having a first body layer and a first active layer, and including a first light transmitting region. Doing so would protect the semiconductor device as well as enable optical access through each die for accurate measurement of inter-die distance while preserving active circuitry functionality.
Sun et al. teaches a method of manufacturing a semiconductor package, comprising:
cutting through the molding member 136, the die 250, the buffer die 100, and the support carrier 50 such that outer side surfaces of the molding member 136, the buffer die 100, and the die 250 are coplanar with each other to form the semiconductor package (Fig. 14-15: 136, 136, 250, 100, 50, paragraph 0075).
and the first die 250 further includes a die region 200 and a scribe lane region 201 surrounding the die region 200 in a plan view, and the cutting is along the scribe lane region 200 (Fig. 14-15: 136, 136, 250, 100, 50, paragraph 0075).
Therefore, it would have been obvious to a person of ordinary skill in the art at the time of the claimed invention to have combined the teachings of Ryu et al., Melikyan and Sun et al. in order to have a step of cutting through the molding member (of Melikyan), the plurality of memory dies, the buffer die, and the support carrier of Ryu et al. such that outer side surfaces of the molding member, the buffer die, and the plurality of memory dies are coplanar with each other to form the semiconductor package similar to the teachings of Sun et al, and have the first memory die of Ryu et al. further include a die region and a scribe lane region surrounding the die region in a plan view according to the teachings of Sun et al., such that the cutting is along the scribe lane region, through which, the respective distances are measured before the cutting. Doing so would allow for more efficient and reproducible singulation after respective distance are measured, as recognized by Sun et al. (paragraph 0076).
Further, it would have been obvious to a person of ordinary skill in the art to perform the above step of cutting after measuring the respective distances, and have the first light transmitting region of Ryu et al. modified by Melikyan disposed in the scribed lane region of Ryu et al. modified by Sun et al.
Regarding Claim 2, the combination of Ryu et al. and Sun et al. teaches the method of claim 1, wherein measuring the respective distances between the buffer die 12a and the plurality of memory dies 12b, 12c, 12d further includes: irradiating second light I3 on the second memory die 12c; and measuring a distance between the second memory 12c die and the buffer die 12a through second detected light I7’, wherein the second detected light I7’ is formed by the second light I3 sequentially passing through a second light transmitting region of the second memory die 12c, being incident on the buffer die 12a, and reflected from the buffer die 12a (as taught by Ryu et al., see annotated Fig. 2: I3, I7’, paragraph 0032), wherein the cutting is performed in the second light transmitting region (as suggested by the combined teachings of Melikyan, Ryu et al. and Sun et al., see rejection of Claim 1 above).
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Annotated Fig. 4 of Melikyan (US 11664318 B2)
Regarding Claim 3, Ryu et al. teaches the method of claim 2, wherein measuring the respective distances between the buffer die 12a and the plurality of memory dies 12b, 12c, 12d further includes: measuring a distance d between the second memory die 12c and a third memory die 12b through third detected light I5’, wherein the third memory die 12b is positioned immediately below the second memory die 12c among the plurality of memory dies 12b, 12c, 12d, and wherein the third detected light I5’ is formed by the second light I3 passing through the second light transmitting region of the second memory die 12c, being incident on the third memory die 12b, and reflected from the third memory die 12b (see annotated Fig. 2: I3, I5’, paragraph 0032).
Regarding Claim 4, Melikyan teaches the method of claim 3, wherein the first light transmitting region and the second light transmitting region at least partially overlap each other in a plan view (see annotated Fig. 5).
Note that the light-transmitting regions are embedded in the plurality of overlapping die 102, in the form of a light-transmittable supporting material layer (see column 6, lines 57-64), and therefore would overlap each other in a plan view.
Regarding Claim 5, Melikyan teaches the method of claim 1, wherein the first light transmitting region extends horizontally from an outer surface of the first memory die 105a in the first active layer 114 to have a predetermined length LO (see annotated Fig. 4: LO, 105a).
Note that the active layer 114 includes a light-transmitting layer (see column 6, lines 57-64), and the active layer 114 extends horizontally from an outer surface of the first memory die 105a across a length LO as shown in annotated Fig. 4.
Regarding Claim 7, Ryu et al. teaches the method of claim 1, teaches wherein the light includes infrared radiation wavelength (paragraph 0014).
Regarding Claim 8, Melikyan teaches the method of claim 1, wherein the first light transmitting region includes a plurality of light transmitting spots within the first active layer (see column 6, lines 57-64).
Note that each active layer 114 include a supporting material layer that is light-transmitting (see column 6, lines 57-64), and the extent of this material is interpreted as the light-transmitting spots.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Ryu et al. (US 20170363418 A1), in view of Melikyan (US 11664318 B2) and Sun et al. (US 20230420330 A1), as applied to Claim 5 above, further in view of Wang et al. (US 20210257521 A1).
The combination of Melikyan, Sun et al. and Ryu et al. fails to teach the method of claim 5, wherein the predetermined length is within a range of 25 µm to 35 µm.
However, Wang et al. teaches a method of manufacturing a semiconductor package comprising a first light transmitting region 104e having a predetermined length W3, wherein the predetermined length W3 is within a range of 100 µm to 1000 µm (Fig. 5: 104e, W3, paragraph 0056).
While Wang fails to explicitly teaches a range 25 µm to 35 µm, a person of ordinary skill in the art would have combined the teachings Melikyan, Ryu et al. and Wang et al. to recognize that the claimed range can be achieved through routine optimization unless there is evidence indicating such range is critical. (According to MPEP § 2144.05 (II-A), "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)). Doing so would ensure the light-transmitting region is sufficiently wide to allow light to pass through the semiconductor die without any obstruction.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Ryu et al. (US 20170363418 A1), in view of Melikyan (US 11664318 B2) and Sun et al. (US 20230420330 A1), as applied to Claim 1 above, further in view of Chandolu et al. (US 20210225715 A1).
Regarding Claim 9, the combination of Melikyan, Sun et al. and Ryu et al. fails to teach the method of claim 1, wherein the first light transmitting region includes a plurality of reflective pads provided in the first active layer to reflect a portion of the light.
However, Chandolu et al. teaches a method of manufacturing a semiconductor package including a plurality of reflective pads 132c provided in the first active layer 102c to reflect a portion of the light 562 (Fig. 5: 562, Fig.1: 132c, 102c, paragraph 0019).
Note that the body of the semiconductor die 102c will inherently comprise active layers. Further the reflective pads are made of metal layers (paragraph 0019). The light source 562 is configured to illuminate the semiconductor package and the detector 564 captures the light reflected from the package (Fig. 5: 562, 564, see paragraph 0033).
Therefore, a person of ordinary skill in the art would have combined the teachings of Melikyan, Sun et al., Ryu et al. and Chandolu et al. in order to have the first light transmitting region include a plurality of reflective pads provided in the first active layer to reflect a portion of the light. Doing so would improve the intensity of the reflected light and therefore improve the measurement accuracy.
Claims 11-15, 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Ryu et al. (US 20170363418 A1), in view of Sun et al. (US 20230420330 A1).
Regarding Claim 11, Ryu et al. teaches a method of manufacturing a semiconductor package, comprising:
disposing a semiconductor device T on a support carrier 100 (see annotated Fig. 2: 100, T, paragraph 0019),
wherein the semiconductor device T includes a buffer die 12a and a plurality of memory dies 12b, 12c, 12d, vertically stacked on the buffer die 12a (see annotated Fig. 2: T, 12a, 12b, 12c, 12d, paragraph 0019);
Note that while Ryu et al. does not explicitly teach a memory die, it does teach the plurality of die 12a-12d can be any semiconductor chip (see paragraph 0003), which includes memory die. Therefore, it would have been obvious to a person of ordinary skill in the art to include a memory die in the semiconductor package of Ryu et al, as it is well known in the art to integrate memory die in semiconductor packages for improved performance.
irradiating light I1 on a first memory die 12d positioned at an uppermost position among the plurality of memory dies 12b, 12c, 12d, (see annotated Fig 4A: I1, annotated Fig. 2: I1, paragraph 0030);
passing the light I1 through a first light transmitting region in a first scribe lane region of a first active layer of the first memory die in a thickness direction of the first active layer (see annotated Fig 4A: I1, annotated Fig. 2: I1, paragraph 0030);
Note that the stack of die 12a-12d shown in Fig. 4A-4B transmits the light I1 and hence each of their body is interpreted as the light transmitting region of each die. Further, each semiconductor die 12a-12d is a semiconductor chip and therefore will inherently comprise active layers.
detecting first light I3’ reflected from a second memory die 12c positioned immediately below the first memory die 12d among the plurality of memory dies 12b, 12c, 12d (see annotated Fig 4A: I1, annotated Fig. 2: I1, paragraph 0030);
measuring a distance d between the first and second memory dies 12d, 12c through the detected first light I3’ (see annotated Fig 4A: I1, annotated Fig. 2: I1, paragraph 0030);
and after measuring the distance, cutting along the first scribe lane region through the semiconductor device and the support carrier such that outer side surfaces of the buffer die and the plurality of memory dies are coplanar with each other to form the semiconductor package.
Sun et al. teaches a method of manufacturing a semiconductor package, comprising:
cutting along the first scribe lane region 201 through the semiconductor device and the support carrier 50 such that outer side surfaces of the buffer die 100, and the die 250 are coplanar with each other to form the semiconductor package 200 (Fig. 14-15: 136, 136, 250, 100, 50, paragraph 0075).
Therefore, it would have been obvious to a person of ordinary skill in the art at the time of the claimed invention to have combined the teachings of Ryu et al. and Sun et al. in order to have a step of cutting along the first scribe lane region through the semiconductor device and the support carrier of Ryu et al. similar to the teachings of Sun et al. such that outer side surfaces of the buffer die and the plurality of memory dies are coplanar with each other to form the semiconductor package. . Doing so would allow for more efficient and reproducible singulation, as recognized by Sun et al. (paragraph 0076). Further, it would have been obvious to a person of ordinary skill in the art to perform the above step of cutting after measuring the distance according to Ryu, and have the first light transmitting region of Ryu disposed in the scribed lane region according to the teachings of Sun et al.
Regarding Claim 12, the combination of Ryu et al. and Sun et al. teaches the method of claim 11, further comprising: passing the light I1 through a second light transmitting region (as taught by Ryu et al., see annotated Fig, 2) in a second scribe lane region 201 (as taught by Sun et al. in Fig. 14) of a second active layer of the second memory die 12c (as taught by Ryu et al., see annotated Fig, 2); detecting second light I7’ reflected from the buffer die 12a positioned below the second memory die 12c; and measuring a distance between the second memory die 12c and the buffer die 12a through the detected second light I7’ (as taught by Ryu et al., see annotated Fig. 2: I1, I7’, paragraph 0032), wherein the cutting is performed along the second scribe lane region 201 (as taught by Sun et al. in Fig. 14).
Regarding Claim 13, Ryu et al. teaches the method of claim 12, further comprising: detecting third light I5’ reflected from a third memory die 12b positioned immediately below the second memory die 12c among the plurality of memory dies 12b, 12c, 12d; and measuring a distance d between the second and third memory dies 12c, 12b through the third detected light I5’ (see annotated Fig. 2: I1, I5’, paragraph 0032).
Regarding Claim 14, Ryu et al. teaches the method of claim 13, wherein the first light transmitting region and the second light transmitting region at least partially overlap each other in a plan view (see annotated Fig. 2).
Note that the light-transmitting regions of each die correspond to the middle light-transmitting portion of the plurality of die 12a-12d, which overlap with each other in a plan view (see annotated Fig. 2).
Regarding Claim 15, Ryu et al. teaches the method of claim 11, wherein the first light transmitting region extends horizontally from an outer surface of the first memory die in the first active layer to have a predetermined length (see annotated Fig. 2).
Note that the first light-transmitting region included in the body of die 12d extends horizontally from an outer surface of the first memory die 12d across the length of the die as shown in annotated Fig. 2. The length of the die 12d is therefore interpreted as the predetermined length.
Regarding Claim 17, Ryu et al. teaches the method of claim 11, teaches wherein the light includes infrared radiation wavelength (paragraph 0014).
Regarding Claim 18, Ryu et al. teaches the method of claim 11, wherein the first light transmitting region includes a plurality of light transmitting spots within the first active layer (Note that the portion of the die 12d in Fig. 4A on which light is irradiated is interpreted as the light-transmitting spots).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Ryu et al. (US 20170363418 A1), in view of Sun et al. (US 20230420330 A1), as applied to Claim 15 above, further in view of Wang et al. (US 20210257521 A1).
The combination of Ryu et al. and Sun et al. fails to teach the method of claim 15, wherein the predetermined length is within a range of 25 µm to 35 µm.
However, Wang et al. teaches a method of manufacturing a semiconductor package comprising a first light transmitting region 104e having a predetermined length W3, wherein the predetermined length W3 is within a range of 100 µm to 1000 µm (Fig. 5: 104e, W3, paragraph 0056). Further, according to MPEP § 2144.05 (II-A), "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955)).
While Wang fails to explicitly teaches a range 25 µm to 35 µm, a person of ordinary skill in the art would have combined the teachings Ryu et al., Sun et al. and Wang et al. in order to have the predetermined length within a range of 25 µm to 35 µm through routine optimization unless there is evidence indicating such range is critical. Doing so would ensure the light-transmitting region is sufficiently wide to allow light to pass through the semiconductor die without any obstruction.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Ryu et al. (US 20170363418 A1), in view of Sun et al. (US 20230420330 A1), as applied to Claim 11 above, further in view of Chandolu et al. (US 20210225715 A1).
Regarding Claim 19, the combination of Ryu et al. and Sun et al. fails to each the method of claim 11, wherein the first light transmitting region includes a plurality of reflective pads that are disposed in the first active layer to reflect a portion of the light.
However, Chandolu et al. teaches a method of manufacturing a semiconductor package including a plurality of reflective pads 132c provided in the first active layer 102c to reflect a portion of the light 562 (Fig. 5: 562, Fig.1: 132c, 102c, paragraph 0019).
Note that the body of the semiconductor die 102c will inherently comprise active layers. Further the reflective pads 132 are made of metal layers (paragraph 0019). The light source 562 is configured to illuminate the semiconductor package and the detector 564 captures the light reflected from the package (Fig. 5: 562, 564, see paragraph 0033).
Therefore, a person of ordinary skill in the art would have combined the teachings of Ryu et al. and Chandolu et al. in order to have the first light transmitting region include a plurality of reflective pads provided in the first active layer to reflect a portion of the light. Doing so would improve the intensity of the reflected light and therefore improve the measurement accuracy.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAMNA F IQBAL whose telephone number is 571-272-1587. The examiner can normally be reached M-F: 8.30 am - 5.30 pm EST.
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/HAMNA FATHIMA IQBAL/Examiner, Art Unit 2817
/Kretelia Graham/Supervisory Patent Examiner, Art Unit 2817
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