9DETAILED ACTION
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the communications dated 10/15/2025.
Claims 1-19 are pending in this application.
Applicant made a provisional election without traverse to prosecute the
invention of Group I, claims 1-5, is acknowledged.
Claims 6-19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a non-elected group there being no allowable generic or linking claim.
Applicant has the right to file a divisional application covering the subject matter of the non-elected claims.
Foreign Priority
2. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Specification
3. The specification has been checked to the extent necessary to determine the presence of possible minor errors. However, the applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objection
4. The claim is objected to for the following reason:
In claim 1, line 13, the limitation “the device region” lacks an antecedent basis. As best understood, it should be read as – the first device region --. The search will be performed accordingly.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
5. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
6. Claims 1-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yeap et al. (US 2019/0288690)
Regarding claim 1, Yeap discloses a semiconductor structure, comprising:
a substrate 102 (see fig. 5) including a base substrate 102, the base substrate including a first device region (surrounded by isolation 133, and on which a fin 106 is located; see also fig. 2) and a second device region (on which another fin 106 is located; see also fig. 2);
a first active region (FIN 106) on the first device region and a second active region (FIN 106) on the second device region;
an isolation layer 133 (fig. 5) between the first active region and the second active region; and
a first gate electrode 101 (fig. 2) and a second gate electrode 102 on the substrate,
wherein:
the first active region 106 and the second active region 106 extend along a first direction (fig. 2);
the first active region 106 includes a first functional region (source region and source contact 108, fig. 2) and a first shared region 110-1 or 110-1 & 112 (drain and common drain contact region 110-1 and/or cross-coupled contact 112);
the first gate electrode 101 and the second gate electrode 102 are parallel to a second direction, wherein the first direction and the second direction are perpendicular to each other;
the first gate electrode 101 is located on the first device region (associated with active region or FIN 106 connecting to cross-coupled contact 112 in fig. 2) and on a portion of a surface of the first active region 106;
the second gate electrode 102 is located on the second device region (associated with active region or FIN 106 connecting to cross-coupled contact 114) and on a portion of a surface of the second active region 106; and
the second gate electrode 102 also extends to a surface of the first shared area 110-1/112.
Regarding claim 2, Yeap discloses the structure according to claim L, wherein:
the second active region 106 includes a second functional region (source region and source contact 108, fig. 2) and a second shared region 110-2 or 110-2 & 114 (drain and common drain contact region 110-2 and/or cross-coupled contact 114); and
the first gate electrode 101 also extends to a surface of the second shared region 110-2/114. See fig. 2.
Regarding claim 3, Yeap discloses the structure according to claim 1, further comprising:
first source/drain layers (forming transistor PU1 in fig. 2) in the first active region 106 at two sides of the first gate electrode 101;
a first channel layer in the first active region under the first gate electrode 101 and between the adjacent first source/drain layers;
second source/drain layers (forming transistor PU2) in the second active region 106 at two sides of the second gate electrode 102; and
a second channel layer in the second active region 106 under the second gate electrode 102 and between the adjacent second source/drain layers.
Regarding claim 4, Yeap discloses the structure according to claim 3, further comprising:
an interlayer dielectric layer 162 (see fig. 9) on the substrate 102, wherein the first gate electrode 101 and the second gate electrode are located in the interlayer dielectric layer 162;
a first dielectric layer on the interlayer dielectric layer, where the first dielectric layer includes a plurality of contact layers respectively located on surfaces of the first gate electrode, the second gate electrode, the first source/drain layers, and the second source/drain layers;
a second dielectric layer located on the first dielectric layer; and a metal interconnection layer inside the second dielectric layer, wherein the metal interconnection layer and the plurality of contact layers are electrically connected (see para. 0027: contact structures (conductive lines and/or vias) formed in one or more metallization layers formed above the transistor devices (e.g., M0, M1/V0, etc.)).
Regarding claim 5, Yeap discloses the structure according to claim 1, wherein:
the first gate electrode 101 is made of a material including metal or its derivatives, wherein the metal or its derivatives include titanium nitride, tantalum nitride, titanium, aluminum, tungsten, copper, lanthanide metal oxides or a combination thereof; and
the second gate electrode 102 is made of a material including metal or its derivatives, wherein the metal or its derivatives include titanium nitride, tantalum nitride, titanium, aluminum, tungsten, copper, lanthanide metal oxides or a combination thereof. See para. 0032.
Conclusion
7. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the day of this letter. Failure to respond within the period for response will cause the application to become abandoned (see M.P.E.P 710.02(b)).
A shortened time for reply may be extended up to the maximum six-month period (35 U.S.C. 133). An extension of time fee is normally required to be paid if the reply period is extended. The amount of the fee is dependent upon the length of the extension. Extensions of time are generally not available after an application has been allowed.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300.
Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633.
/DAO H NGUYEN/Primary Examiner, Art Unit 2818 November 14, 2025