DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/09/2023 has been considered by the examiner.
Drawings
The drawings were received on 03/09/2023 and amended drawings including a replacement sheet showing amended FIG. 33 were received on 05/30/2023. The drawings as amended are acceptable.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: IMAGE SENSOR HAVING FIRST SUBPIXEL AND SECOND SUBPIXEL INCLUDING SECOND TRANSFER TRANSISTOR COMPRISING VERTICAL MULTI-GATE.
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Status of Claims
Claims 1-17 and 21-23 are pending.
Claims 18-20 are canceled.
Claims 1-17 and 21-23 are original.
Claims 1-7, 11-17 and 21-22 are rejected herein.
Claims 8-10, 21 and 23 are objected to herein.
Claim Objections
Claim 21 is objected to because of the following informalities.
Claim 21 recites “wherein the second transfer gate comprises a vertical multi-gate transistor” in line 14. It appears incorrect to recite that a gate comprises a transistor. It appears that the foregoing should be “wherein the second transfer gate comprises a vertical multi-gatetransistor comprises a vertical multi-gate transistor.”
No status for claim 21 has been included or indicated in the Listing of Claims filed 03/09/2023 in noncompliance with the requirements of 37 CFR 1.121(c). It appears the identifier “(Original)” should have been used for claim 21.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 21 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yamachi (US 20230299162 A1).
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ANNOTATED FIG. 13 OF YAMACHI
Regarding claim 1, Yamachi discloses (see generally, e.g., FIGS. 12, 21 and 23 along with FIG. 13 as annotated herein):
An image sensor (100) comprising:
a plurality of pixels (PU), wherein each pixel (PU) of the plurality of pixels (PU) comprises:
a first sub-pixel (102’) comprising a first photoelectric conversion area (PD’), a first floating diffusion area (FD’), and a first transfer transistor (TR’) configured to transfer charges accumulated in the first photoelectric conversion area (PD’) to the first floating diffusion area (FD’); and
a second sub-pixel (102’’) disposed adjacent to the first sub-pixel (102’) and comprising a second photoelectric conversion area (PD’’), a second floating diffusion area (FD’’) and a second transfer transistor (TR’’) configured to transfer charges accumulated in the second photoelectric conversion area (PD’’) to the second floating diffusion area (FD’’),
wherein the first transfer transistor (TR’) comprises a first transfer gate (e.g., the gate 15 as shown in FIG. 23 – hereinafter 15’) (see also paragraph [0162] – “the planar MOS transistor Tr′ shown in FIG. 23 may be applied to the transfer transistor TR”),
wherein the second transfer transistor (TR’’) comprises a second transfer gate (e.g., the gate 15 as shown in FIG. 21 – hereinafter 15’’) (see also paragraph [0162] – “in the above-mentioned imaging device 100, the MOS transistor TrB that is a FinFET shown in FIG. 21 … may be applied to the transfer transistor TR disposed inside the sensor pixel 102”), and
wherein the second transfer gate (15’’) comprises a vertical multi-gate (152,153).
Regarding claim 21, Yamachi discloses (see generally, e.g., FIGS. 12, 21 and 23 along with FIG. 13 as annotated herein):
A pixel (PU) included in an image sensor (100), the pixel (PU) comprising:
a first sub-pixel (102’) comprising:
a first photoelectric conversion area (PD’), a first floating diffusion area (FD’), and
a first transfer transistor (TR’) which comprises a first transfer gate (e.g., the gate 15 as shown in FIG. 23 – hereinafter 15’) (see also paragraph [0162] – “the planar MOS transistor Tr′ shown in FIG. 23 may be applied to the transfer transistor TR”), and is configured to transfer charges accumulated in the first photoelectric conversion area ()PD’) to the first floating diffusion area (FD’); and
a second sub-pixel (102’’) disposed adjacent to the first sub-pixel (102’) and comprising:
a second photoelectric conversion area (PD’’), a second floating diffusion area (FD’’), and
a second transfer transistor (TR’’) which comprises a second transfer gate (e.g., the gate 15 as shown in FIG. 21 – hereinafter 15’’) (see also paragraph [0162] – “in the above-mentioned imaging device 100, the MOS transistor TrB that is a FinFET shown in FIG. 21 … may be applied to the transfer transistor TR disposed inside the sensor pixel 102”), and is configured to transfer charges accumulated in the second photoelectric conversion area (PD’’) to the second floating diffusion area (FD’’),
wherein the second transfer gate (15’’) comprises a vertical multi-gate (152,153) transistor.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-2, 13 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Shishido (US 20200295064 A1) in view of Yamachi.
Regarding claim 1, Shishido discloses (see generally, e.g., FIGS. 3, 5-10 and 13):
An image sensor (100) comprising:
a plurality of pixels (30), wherein each pixel (30) of the plurality of pixels (30) comprises:
a first sub-pixel (31’) comprising a first photoelectric conversion area (PDL), a first floating diffusion area (FDL), and a first transfer transistor (TXL) configured to transfer charges accumulated in the first photoelectric conversion area (PDL) to the first floating diffusion area (FDL); and
a second sub-pixel (31) disposed adjacent to the first sub-pixel (31’) and comprising a second photoelectric conversion area (PDS), a second floating diffusion area (FDS) and a second transfer transistor (TXS) configured to transfer charges accumulated in the second photoelectric conversion area (PDS) to the second floating diffusion area (FDS),
wherein the first transfer transistor (TXL) comprises a first transfer gate (note, transistor (TXL) is depicted as including a gate and hence the gate of the first transfer transistor (TXL) reads on the first transfer gate – hereinafter this shall be referenced as “G1”), and
wherein the second transfer transistor (TXS) comprises a second transfer gate (note, transistor (TXS) is depicted as including a gate and hence the gate of the second transfer transistor reads on the second transfer gate – hereinafter this shall be referenced as “G2”).
Shishido does not explicitly disclose:
wherein the second transfer gate comprises a vertical multi-gate.
However, in analogous art, Yamachi discloses a transfer transistor (TR) having a transfer gate (15) that comprises a vertical multi-gate (152,153). See, e.g., FIGS. 13 and 21, along with paragraph [0162].
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have used a transfer transistor (TR) having a transfer gate (15) that comprises a vertical multi-gate (152,153) as taught by Yamachi for the second transfer transistor (TXS) of Shishido according to known methods to yield predictable results, for example, in order to suppress dielectric breakdown and improve reliability of the gate insulating film and improve the conversion efficiency of the signal of the voltage applied to the gate electrode. See, e.g., paragraph [0138] of Yamachi. Further, the vertical multi-gate structure of the finFET provides superior electrostatic control over the transistor's channel which can result in benefits such as lower power consumption, reduced leakage current, higher performance and faster switching speeds, better short-channel effect suppression, enhanced scalability, etc. For example, the multi-gate structure increases the effective surface area of the channel, leading to a higher drive current and improved performance.
Regarding claim 2, Shishido in view of Yamachi as applied to claim 1 discloses the image sensor of claim 1.
Shishido further discloses a substrate (300) in which the first photoelectric conversion area (PDL) and the second photoelectric conversion area (PDS) are disposed,
wherein, in a plan view, an area of the first photoelectric conversion area (PDL) is larger than an area of the second photoelectric conversion area (PDS). See, e.g., FIG. 10.
Regarding claim 13, Shishido discloses (see generally, e.g., FIGS. 3, 5-10 and 13):
An image sensor (100) comprising:
a substrate (300, 301);
a first photoelectric conversion area (PDL) disposed in the substrate (300, 301) and having a first width in a horizontal direction (x direction) (see, e.g., FIGS. 5-10);
a second photoelectric conversion area (PDS) disposed in the substrate (300, 301) and having a second width in the horizontal direction (x direction), wherein the second width is smaller than the first width (see, e.g., FIGS. 5-10);
a first floating diffusion area (FDL) disposed in the substrate (300, 301) and spaced apart from a second floating diffusion area (FDS) disposed in the substrate (300, 301);
a first transfer transistor (TXL) at least partially disposed in the substrate (300, 301) or on a face of the substrate (300, 301), the first transfer transistor (TXL) being configured to transfer charges accumulated in the first photoelectric conversion area (PDL) to the first floating diffusion area (FDL); and
a second transfer transistor (TXS) at least partially disposed in the substrate (300, 301) or on the face of the substrate (300, 301), the second transfer transistor (TXS) being configured to transfer charges accumulated in the second photoelectric conversion area (PDS) to the second floating diffusion area (FDS),
wherein the first transfer transistor (TXL) comprises a first transfer gate (note, transistor (TXL) is depicted as including a gate and hence the gate of the first transfer transistor (TXL) reads on the first transfer gate – hereinafter this shall be referenced as “G1”), and
wherein the second transfer transistor (TXS) comprises a second transfer gate (note, transistor (TXS) is depicted as including a gate and hence the gate of the second transfer transistor reads on the second transfer gate – hereinafter this shall be referenced as “G2”).
Shishido does not explicitly disclose:
wherein the second transfer gate comprises a vertical multi-gate.
However, in analogous art, Yamachi discloses a transfer transistor (TR) having a transfer gate (15) that comprises a vertical multi-gate (152,153). See, e.g., FIGS. 13 and 21, along with paragraph [0162].
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have used a transfer transistor (TR) having a transfer gate (15) that comprises a vertical multi-gate (152,153) as taught by Yamachi for the second transfer transistor (TXS) of Shishido according to known methods to yield predictable results, for example, in order to suppress dielectric breakdown and improve reliability of the gate insulating film and improve the conversion efficiency of the signal of the voltage applied to the gate electrode. See, e.g., paragraph [0138] of Yamachi. Further, the vertical multi-gate structure of the finFET provides superior electrostatic control over the transistor's channel which can result in benefits such as lower power consumption, reduced leakage current, higher performance and faster switching speeds, better short-channel effect suppression, enhanced scalability, etc. For example, the multi-gate structure increases the effective surface area of the channel, leading to a higher drive current and improved performance.
Regarding claim 21, Shishido discloses (see generally, e.g., FIGS. 3, 5-10 and 13):
A pixel (30) included in an image sensor (100), the pixel (30) comprising:
a first sub-pixel (31’) comprising:
a first photoelectric conversion area (PDL),
a first floating diffusion area (FDL), and
a first transfer transistor (TXL) which comprises a first transfer gate (note, transistor (TXL) is depicted as including a gate and hence the gate of the first transfer transistor (TXL) reads on the first transfer gate – hereinafter this shall be referenced as “G1”), and is configured to transfer charges accumulated in the first photoelectric conversion area (PDL) to the first floating diffusion area (FDL); and
a second sub-pixel (31) disposed adjacent to the first sub-pixel (31’) and comprising:
a second photoelectric conversion area (PDS),
a second floating diffusion area (FDS), and
a second transfer transistor (TXS) which comprises a second transfer gate (note, transistor (TXS) is depicted as including a gate and hence the gate of the second transfer transistor reads on the second transfer gate – hereinafter this shall be referenced as “G2”), and is configured to transfer charges accumulated in the second photoelectric conversion area (PDS) to the second floating diffusion area (FDS).
Shishido does not explicitly disclose:
wherein the second transfer gate comprises a vertical multi-gate transistor.
However, in analogous art, Yamachi discloses a transfer transistor (TR) having a transfer gate (15) that comprises a vertical multi-gate (152,153). See, e.g., FIGS. 13 and 21, along with paragraph [0162].
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have used a transfer transistor (TR) having a transfer gate (15) that comprises a vertical multi-gate (152,153) as taught by Yamachi for the second transfer transistor (TXS) of Shishido according to known methods to yield predictable results, for example, in order to suppress dielectric breakdown and improve reliability of the gate insulating film and improve the conversion efficiency of the signal of the voltage applied to the gate electrode. See, e.g., paragraph [0138] of Yamachi. Further, the vertical multi-gate structure of the finFET provides superior electrostatic control over the transistor's channel which can result in benefits such as lower power consumption, reduced leakage current, higher performance and faster switching speeds, better short-channel effect suppression, enhanced scalability, etc. For example, the multi-gate structure increases the effective surface area of the channel, leading to a higher drive current and improved performance.
Claims 1, 11-17 and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Iwata (US 20140042507 A1) in view of Yamachi.
Regarding claim 1, Iwata discloses (see generally, e.g., FIGS. 1A, 1B, 2, 3A, 10A and 10B):
An image sensor (1000) comprising:
a plurality of pixels (P11 and P12 are read as a first pixel “P’”; and P21 and P22 are read as a second pixel “P”” – P’ and P’’ constitute a plurality of pixels “PP”), wherein each pixel (P’, P’’) of the plurality of pixels (PP) comprises:
a first sub-pixel (P11 is read as the first subpixel of P’; and P21 is read as the first subpixel of P’’) comprising a first photoelectric conversion area (108, 10 is read as the first photoelectric conversion area of P11; and 107, 10 is read as the first photoelectric conversion area of P21), a first floating diffusion area (124 is read as the first floating diffusion area for P11; and 124 is read as the first floating diffusion area for P21), and a first transfer transistor (118 is read as the first transfer transistor for P11; and 117 is read as the first transfer transistor for P21) configured to transfer charges accumulated in the first photoelectric conversion area (108, 107) to the first floating diffusion area (124); and
a second sub-pixel (P12 is read as the second subpixel of P’; and P22 is read as the second subpixel of P’’) disposed adjacent to the first sub-pixel (see, e.g., FIGS. 2 and 3A) and comprising a second photoelectric conversion area (104, 20 is read as the second photoelectric conversion area of P12; and 103, 20 is read as the second photoelectric conversion area of P22), a second floating diffusion area (122 is read as the second floating diffusion area for P12; and 122 is read as the second floating diffusion area for P22) and a second transfer transistor (114 is read as the second transfer transistor for P12; and 113 is read as the second transfer transistor for P22) configured to transfer charges accumulated in the second photoelectric conversion area (104, 103) to the second floating diffusion area (122),
wherein the first transfer transistor (118, 117) comprises a first transfer gate (see gates depicted for transistors 118 and 117 in FIG. 2 – hereinafter G1), and
wherein the second transfer transistor (114, 113) comprises a second transfer gate (see gates depicted for transistors 114 and 113 in FIG. 2 – hereinafter G2).
Iwata does not explicitly disclose:
wherein the second transfer gate comprises a vertical multi-gate.
However, in analogous art, Yamachi discloses a transfer transistor (TR) having a transfer gate (15) that comprises a vertical multi-gate (152,153). See, e.g., FIGS. 13 and 21, along with paragraph [0162].
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have used a transfer transistor (TR) having a transfer gate (15) that comprises a vertical multi-gate (152,153) as taught by Yamachi for the second transfer transistor (114, 113) of Iwata according to known methods to yield predictable results, for example, in order to suppress dielectric breakdown and improve reliability of the gate insulating film and improve the conversion efficiency of the signal of the voltage applied to the gate electrode. See, e.g., paragraph [0138] of Yamachi. Further, the vertical multi-gate structure of the finFET provides superior electrostatic control over the transistor's channel which can result in benefits such as lower power consumption, reduced leakage current, higher performance and faster switching speeds, better short-channel effect suppression, enhanced scalability, etc. For example, the multi-gate structure increases the effective surface area of the channel, leading to a higher drive current and improved performance.
Regarding claim 11, Iwata in view of Yamachi as applied to claim 1 discloses the image sensor of claim 1.
Iwata further discloses wherein the first floating diffusion area (124) is spaced apart from the second floating diffusion area (122). See, e.g., FIG. 3A.
Regarding claim 12, Iwata in view of Yamachi as applied to claim 11 discloses the image sensor of claim 11.
Iwata further discloses a source follower transistor (132, 134) configured to output the charges accumulated in the first floating diffusion area (124) and the charges accumulated in the second floating diffusion area (122). See, e.g., FIG. 2 and paragraph [0048].
Regarding claim 13, Iwata discloses (see generally, e.g., FIGS. 1A, 1B, 2, 3A, 10A and 10B):
An image sensor (1000) comprising:
a substrate (100);
a first photoelectric conversion area (104, 10) disposed in the substrate (100) and having a first width in a horizontal direction (see, e.g., FIG. 10A);
a second photoelectric conversion area (107, 20) disposed in the substrate (100) and having a second width in the horizontal direction (see, e.g., FIG. 10B);
a first floating diffusion area (122) disposed in the substrate (100) and spaced apart from a second floating diffusion (124);
a first transfer transistor (114) at least partially disposed in the substrate (100) or on a face of the substrate (100), the first transfer transistor (114) being configured to transfer charges accumulated in the first photoelectric conversion area (104, 10) to the first floating diffusion area (122); and
a second transfer transistor (117) at least partially disposed in the substrate (100) or on the face of the substrate (100), the second transfer transistor (117) being configured to transfer charges accumulated in the second photoelectric conversion area (107, 20) to the second floating diffusion area (124),
wherein the first transfer transistor (114) comprises a first transfer gate (note gate depicted for transistor 114, e.g., in FIG. 2 – hereinafter “G1”), and
wherein the second transfer transistor (117) comprises a second transfer gate (note gate depicted for transistor 117, e.g., in FIG. 2 – hereinafter “G2”).
Iwata does not explicitly disclose:
wherein the second transfer gate comprises a vertical multi-gate.
However, in analogous art, Yamachi discloses a transfer transistor (TR) having a transfer gate (15) that comprises a vertical multi-gate (152,153). See, e.g., FIGS. 13 and 21, along with paragraph [0162].
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have used a transfer transistor (TR) having a transfer gate (15) that comprises a vertical multi-gate (152,153) as taught by Yamachi for the second transfer transistor (117) of Iwata according to known methods to yield predictable results, for example, in order to suppress dielectric breakdown and improve reliability of the gate insulating film and improve the conversion efficiency of the signal of the voltage applied to the gate electrode. See, e.g., paragraph [0138] of Yamachi. Further, the vertical multi-gate structure of the finFET provides superior electrostatic control over the transistor's channel which can result in benefits such as lower power consumption, reduced leakage current, higher performance and faster switching speeds, better short-channel effect suppression, enhanced scalability, etc. For example, the multi-gate structure increases the effective surface area of the channel, leading to a higher drive current and improved performance.
Regarding claim 14, Iwata in view of Yamachi as applied to claim 13 discloses the image sensor of claim 13.
Iwata further discloses:
wherein the first photoelectric conversion area (10) comprises a first maximum impurity concentration area (see the “dotted line” in element 12 and paragraph [0033]) at a first depth (see FIG. 10A) from the face (upper face) of the substrate (100),
wherein the second photoelectric conversion area (20) comprises a second maximum impurity concentration area (see the “dotted line” in element 22 and paragraph [0033]) at a second depth (see FIG. 10B) from the face (upper face) of the substrate (100), and
wherein the first depth is smaller than the second depth (see FIGS. 10A and 10B).
Regarding claim 15, Iwata in view of Yamachi as applied to claim 14 discloses the image sensor of claim 14.
Iwata in view of Yamachi discloses that the second transfer gate comprises a vertical multi-gate (see, e.g., the treatment of claim 1 above), but does not explicitly disclose a gate type of the first transfer gate that is different from a gate type of the second transfer gate.
However, in analogous art, Yamachi discloses a transfer transistor (TR) that has a transfer gate (15) of the planar type. See, e.g., FIGS. 13 and 23, along with paragraph [0162].
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have used a transfer transistor (TR) having a transfer gate (15) that is the planar type as taught by Yamachi for the first transfer transistor (114) of Iwata according to known methods to yield predictable results, for example, in order to simplify fabrication of the first transfer transistor (i.e., insomuch as planar transistors with planar gates are generally simpler to fabricate, e.g., as compared to finFETs or other like multi-gate transistors).
Notably, when so constituted, the gate type of the first transfer gate (i.e., planar gate type) is different from the gate type of the second transfer gate (i.e., vertical multi-gate type).
Regarding claim 16, Iwata in view of Yamachi as applied to claim 15 discloses the image sensor of claim 15.
Yamachi further disclose that the first transfer gate is a horizontal gate. See, e.g., gate (15) shown in FIG. 23 of Yamachi.
Regarding claim 17, Iwata in view of Yamachi as applied to claim 15 discloses the image sensor of claim 15.
Yamachi further disclose that the first transfer gate is a single gate. See, e.g., gate (15) shown in FIG. 23 of Yamachi.
Regarding claim 21, Iwata discloses (see generally, e.g., FIGS. 1A, 1B, 2, 3A, 10A and 10B):
A pixel (P12, P21) included in an image sensor (1000) comprising:
a first sub-pixel (P12) comprising:
a first photoelectric conversion area (104, 10),
a first floating diffusion area (122), and
a first transfer transistor (114) which comprises a first transfer gate (note gate depicted for transistor 114, e.g., in FIG. 2 – hereinafter “G1”), and is configured to transfer charges accumulated in the first photoelectric conversion area (104, 10) to the first floating diffusion area (122); and
a second sub-pixel (P21) comprising:
a second photoelectric conversion area (107, 20),
a second floating diffusion area (124), and
a second transfer transistor (117) which comprises a second transfer gate (note gate depicted for transistor 117, e.g., in FIG. 2 – hereinafter “G2”), and is configured to transfer charges accumulated in the second photoelectric conversion area (107, 20) to the second floating diffusion area (124).
Iwata does not explicitly disclose:
wherein the second transfer gate comprises a vertical multi-gate transistor.
However, in analogous art, Yamachi discloses a transfer transistor (TR) having a transfer gate (15) that comprises a vertical multi-gate (152,153). See, e.g., FIGS. 13 and 21, along with paragraph [0162].
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have used a transfer transistor (TR) having a transfer gate (15) that comprises a vertical multi-gate (152,153) as taught by Yamachi for the second transfer transistor (117) of Iwata according to known methods to yield predictable results, for example, in order to suppress dielectric breakdown and improve reliability of the gate insulating film and improve the conversion efficiency of the signal of the voltage applied to the gate electrode. See, e.g., paragraph [0138] of Yamachi. Further, the vertical multi-gate structure of the finFET provides superior electrostatic control over the transistor's channel which can result in benefits such as lower power consumption, reduced leakage current, higher performance and faster switching speeds, better short-channel effect suppression, enhanced scalability, etc. For example, the multi-gate structure increases the effective surface area of the channel, leading to a higher drive current and improved performance.
Regarding claim 22, Iwata in view of Yamachi as applied to claim 21 discloses the image sensor of claim 21.
Iwata further discloses a substrate (100) in which the first photoelectric conversion area (10) and the second photoelectric conversion area (20) are disposed (see, e.g., FIGS. 10A and 10B),
wherein the first photoelectric conversion area (10) comprises a first maximum impurity concentration area (see the “dotted line” in element 12 and paragraph [0033]) at a first depth (see FIG. 10A) from a face (upper face) of the substrate (100),
wherein the second photoelectric conversion area (20) comprises a second maximum impurity concentration area (see the “dotted line” in element 22 and paragraph [0033]) at a second depth (see FIG. 10B) from the face (upper face) of the substrate (100), and
wherein the first depth is smaller than the second depth (see FIGS. 10A and 10B).
Claims 2-7 is rejected under 35 U.S.C. 103 as being unpatentable over Iwata in view of Yamachi as applied to claim 1 above, and further in view of Shishido.
Regarding claim 2, Iwata in view of Yamachi as applied to claim 1 discloses the image sensor of claim 1.
Iwata further discloses a substrate (100) in which the first photoelectric conversion area (10) and the second photoelectric conversion area (20) are disposed. See, e.g., FIGS. 10A and 10B.
Iwata does not explicitly disclose:
wherein, in a plan view, an area of the first photoelectric conversion area is larger than an area of the second photoelectric conversion area.
However, in analogous art, Shishido discloses a substrate (300) in which the first photoelectric conversion area (PDL) and the second photoelectric conversion area (PDS) are disposed, wherein, in a plan view, an area of the first photoelectric conversion area (PDL) is larger than an area of the second photoelectric conversion area (PDS). See, e.g., FIG. 10.
. It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have made, in a plan view, an area of the first photoelectric conversion area (10) of Iwata larger than an area of the second photoelectric conversion area (20) of Iwata as taught by Shishido according to known methods to yield predictable results, for example, in order to achieve a pixel having a combination of varied subpixels including a subpixel corresponding to low noise and a subpixel corresponding to high saturation. See, e.g., paragraph [0042] of Shishido.
Regarding claim 3, Iwata in view of Yamachi and Shishido as applied to claim 2 discloses the image sensor of claim 2.
Iwata further discloses:
wherein the first photoelectric conversion area (10) comprises a first maximum impurity concentration area (see the “dotted line” in element 12 and paragraph [0033]) at a first depth (see FIG. 10A) from a face (upper face) of the substrate (100),
wherein the second photoelectric conversion area (20) comprises a second maximum impurity concentration area (see the “dotted line” in element 22 and paragraph [0033]) at a second depth (see FIG. 10B) from the face (upper face) of the substrate (100), and
wherein the first depth is smaller than the second depth (see FIGS. 10A and 10B).
Regarding claim 4, Iwata in view of Yamachi and Shishido as applied to claim 3 discloses the image sensor of claim 3.
Iwata in view of Yamachi discloses that the second transfer gate comprises a vertical multi-gate (see, e.g., the treatment of claim 1 above), but does not explicitly disclose a gate type of the first transfer gate that is different from a gate type of the second transfer gate.
However, in analogous art, Yamachi discloses a transfer transistor (TR) that has a transfer gate (15) of the planar type. See, e.g., FIGS. 13 and 23, along with paragraph [0162].
It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have used a transfer transistor (TR) having a transfer gate (15) that is the planar type as taught by Yamachi for the first transfer transistor (118, 117) of Iwata according to known methods to yield predictable results, for example, in order to simplify fabrication of the first transfer transistor (i.e., insomuch as planar transistors with planar gates are generally simpler to fabricate, e.g., as compared to finFETs or other like multi-gate transistors).
Notably, when so constituted, the gate type of the first transfer gate (i.e., planar gate type) is different from the gate type of the second transfer gate (i.e., vertical multi-gate type).
Regarding claim 5, Iwata in view of Yamachi and Shishido as applied to claim 4 discloses the image sensor of claim 4.
Yamachi further disclose that the first transfer gate is a horizontal gate. See, e.g., gate (15) shown in FIG. 23 of Yamachi.
Regarding claim 6, Iwata in view of Yamachi and Shishido as applied to claim 4 discloses the image sensor of claim 4.
Yamachi further disclose that the first transfer gate is a single gate. See, e.g., gate (15) shown in FIG. 23 of Yamachi.
Regarding claim 7, Iwata in view of Yamachi and Shishido as applied to claim 3 discloses the image sensor of claim 3.
Yamachi further discloses (see, e.g., FIG. 21) that the second transfer gate (15) comprises a first sub-gate (152) and a second sub-gate (153),
wherein the first sub-gate (152) faces the second sub-gate (153), and
wherein the first sub-gate (152) is spaced apart from the second sub-gate (153).
Allowable Subject Matter
Claims 8-10 and 23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter.
Regarding claim 8, the prior art of record, alone or in combination, fails to disclose, along with the other claimed limitations and/or features, inter alia: “the second maximum impurity concentration area is positioned between the first sub-gate and the second sub-gate in the plan view,” in such a manner as to anticipate the claim or render the claim obvious.
Regarding claim 9, the prior art of record, alone or in combination, fails to disclose, along with the other claimed limitations and/or features, inter alia: first and second maximum impurity concentration areas in the first and second photoelectric conversion areas, respectively, and having first and second maximum electric potentials, respectively, “wherein the first maximum electric potential is greater than the second maximum electric potential,” in such a manner as to anticipate the claim or render the claim obvious.
Claim 10 depends from claim 9, and accordingly is indicated as including allowable subject matter for at least the same reason as claim 9.
Regarding claim 23, the prior art of record, alone or in combination, fails to disclose, along with the other claimed limitations and/or features, inter alia: “wherein the second transfer transistor extends further into the substrate than the first transfer transistor,” in such a manner as to anticipate the claim or render the claim obvious.
Conclusion
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JOHN P. CORNELY
Examiner
Art Unit 2812
/J.P.C./Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812