DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of species 1 in the reply filed on 06/02/2026 is acknowledged.
Claims 5,7,10,11,15,17 and 23-28 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 06/02/2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-4,6,8,12,13 and 18-22 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Sanuki et al. (US11257802B2).
Regarding claim 1, Fig.4 of Sanuki teaches a semiconductor device comprising:
a first semiconductor structure 2 (col.2, line 23) including a lower substrate 19 (col.2, line 27); and
a second semiconductor structure 1 (col.2, line 12) on and bonded to the first semiconductor structure 2 through a bonding structure 37/41 (col.3, lines 9-11), the second semiconductor structure 1 comprising:
a pattern structure 13 (col.2, line 15);
an upper insulating layer 14 col.2, line 15) on the pattern structure 13;
a stack structure 11 (col.3, line 40) including gate electrode layers WL (col.3, line 41) and interlayer insulating layers 51 (col.3, lines 41-42) alternately stacked between the first semiconductor structure 2 and the pattern structure 13 in a vertical direction that is perpendicular to a lower surface of the pattern structure 13; channel structures CL (Fig.2, col.3, line 45) that extend through the stack structure 11, each channel structure CL respectively including a channel layer 55 (col.3, line 47); and
separation structures 44/46 (col.4, lines 43-44) that extend through the stack structure 11 and separate the stack structure 11;
wherein each of the separation structures 44/46 includes a first portion 44 (col.4, line 43) that extends through the stack structure 11 and a second portion 46 (col.4, line 44) that vertically extends from the first portion 44 and extends through the pattern structure 13, and
wherein the second semiconductor structure 1 further includes a spacer layer 45 (col.4, line 43) that separates the second portions 46 of the separation structures 44/46 from the pattern structure 11.
Regarding claim 2, Sanuki further teaches the semiconductor device of claim 1, wherein the separation structures 44/46 (col.4, lines 43-44) extend in a first horizontal direction (z direction) and separate the stack structure 11 (col.3, line 40) into a plurality of stack portions spaced apart from each other in a second horizontal direction (x direction) that crosses the first horizontal direction (z direction).
Regarding claim 3, Sanuki further teaches the semiconductor device of claim 1, wherein the spacer layer 45 (col.4, line 43) surrounds an outer surface of the second portion 46 (col.4, line 44) of each of the separation structures 44/46 (col.4, lines 43-44).
Regarding claim 4, Sanuki further teaches the semiconductor device of claim 1, wherein an upper end of the spacer layer 45 (col.4, line 43) is located farther from a surface of the lower substrate 19 (col.2, line 27) than an upper surface of the pattern structure 13 (col.2, line 15) is from the surface of the lower substrate 19.
Regarding claim 6, Sanuki further teaches the semiconductor device of claim 1, wherein each of the separation structures 44/46 (col.4, lines 43-44) has a bent portion between the first portion 44 (col.4, line 43) and the second portion 46 (col.4, line 44).
Regarding claim 8, Sanuki further teaches the semiconductor device of claim 1, wherein:
the first portion 44 (col.4, line 43) of each separation structure 44/46 (col.4, lines 43-44) has a continuous shape and extends in a first horizontal direction (z direction), and
the second portion 46 (col.4, line 44) of each separation structure 44/46 has an intermittent shape and extends in the first horizontal direction (z direction) on the first portion 44.
Regarding claim 12, Sanuki further teaches the semiconductor device of claim 1, further comprising:
a conductive pad 47 (col.3, line 23) on the upper insulating layer 14 col.3, line 23);
a landing pad 46 (col.4, line 44) that extends through the upper insulating layer 14 and the pattern structure 13 (col.2, line 15) and is in contact with the conductive pad 47;
a pad spacer layer 45 (col.3, line 22) that surrounds an outer surface of the landing pad 46; and
an input/output 75 (col.7, lines 5-6) contact that electrically connects an upper wiring structure 42/43 (col.3, line 13) to the landing pad 46,
wherein the landing pad 46 is spaced apart from the pattern structure 13 by the pad spacer 45.
Regarding claim 13, Sanuki further teaches the semiconductor device of claim 12, wherein an upper surface of the landing pad 46 (col.4, line 44) is coplanar with or higher than an upper surface of the second portion 46 (col.4, line 44).
Regarding claim 18, Fig.4 of Sanuki teaches a semiconductor device comprising:
a lower substrate 19 (col.2, line 27); circuit elements 31/32/33 (col.2, lines 61-62,65) on the lower substrate 19;
a lower wiring structure 35/36 (col.3, line 4) electrically connected to the circuit elements 31/32/33;
a lower bonding structure 37 (col.3, line 5) connected to the lower wiring structure 35/36;
an upper bonding structure 41 (col.3, line 9) bonded to the lower bonding structure 37;
an upper wiring structure 42/43 (col.3, line 13) connected to the upper bonding structure 41;
a pattern structure 13 (col.2, line 15) on the upper wiring structure 42/43;
gate electrode layers WL (col.3, line 41) stacked on each other in a vertical direction, perpendicular to a lower surface of the pattern structure 13;
channel structures CL (Fig.2, col.3, line 45) that extend through the gate electrode layers WL, each channel structure CL respectively including a channel layer 55 (col.3, line 47); and
separation structures 44/46 (col.4, lines 43-44) extending in a first horizontal direction through the gate electrode layers WL and separating the gate electrode layers WL,
wherein each of the separation structures 44/46 includes a first portion 44 (col.4, line 43) that extends through the gate electrode layers WL a second portion 46 (col.4, line 44) that is on the first portion 44 and that extends through the pattern structure 13, and a bent portion defined by the first portion 44 and the second portion 46.
Regarding claim 19, Sanuki further teaches the semiconductor device of claim 18, wherein the bent portion is located on a level higher than an upper surface of an uppermost gate electrode layer WL (col.3, line 41), and is located on substantially the same level or lower than a lower surface of the pattern structure 13 (col.2, line 15).
Regarding claim 20, Sanuki further teaches the semiconductor device of claim 18, wherein a first width of an upper end of the first portion 44 (col.4, line 43) in a second horizontal direction (x direction) that crosses the first horizontal direction (z direction), is smaller than a second width of a lower end of the second portion 46 (col.4, line 44) in the second horizontal direction (x direction).
Regarding claim 21, Sanuki further teaches the semiconductor device of claim 18, wherein the second portion 46 (col.4, line 44) has an inclined side surface so that a width decreases toward the lower substrate 19 (col.2, line 27) in a second horizontal direction that crosses the first horizontal direction.
Regarding claim 22, Fig.3 of Jung teaches a data storage system comprising:
a semiconductor storage device (col.2, line 9, a three-dimensional memory in which a memory array chip 1 (hereinafter, simply referred to as an array chip 1) and a circuit chip 2 are bonded) including a first semiconductor structure 2 (col.2, line 23) including a lower substrate 19 (col.2, line 27), circuit elements 31/32/33 (col.2, lines 61-62,65) on the lower substrate 19, a second semiconductor structure 1 (col.2, line 12) on and bonded to the first semiconductor structure 2, and an input/output (I/O) pad 75 (col.7, lines 5-6) electrically connected to the circuit elements 31/32/33; and
a controller 3 (col.7, line 21) electrically connected to the semiconductor storage device through the I/O pad 75 and controlling the semiconductor storage device,
wherein the second semiconductor structure 1 includes:
a pattern structure 13 (col.2, line 15); an upper insulating layer 14 col.2, line 15) on the pattern structure 13;
a stack structure 11 (col.3, line 40) including gate electrode layers WL (col.3, line 41) and interlayer insulating layers 51 (col.3, lines 41-42) alternately stacked between the first semiconductor structure 2 and the pattern structure 13 in a vertical direction that is perpendicular to a lower surface of the pattern structure 13;
channel structures CL (Fig.2, col.3, line 45) that extend through the stack structure 11, each channel structure CL respectively including a channel layer 55 (col.3, line 47); and
separation structures 44/46 (col.4, lines 43-44) that extend through the stack structure 11 and separate the stack structure 11;
wherein each of the separation structures 44/46 includes a first portion 44 (col.4, line 43) that extends through the stack structure 11 and a second portion 46 (col.4, line 44) that vertically extends from the first portion 44 and extends through the pattern structure 13, and
wherein the second semiconductor structure 1 further includes a spacer layer 45 (col.4, line 43) that separates the second portions 46 of the separation structures from the pattern structure 13.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 9 rejected under 35 U.S.C. 103 as being unpatentable over Sanuki et al. (US11257802B2) in view of Lee et al. (US20150318301A1).
Regarding claim 9, Sanuki does not teach wherein:
each of the separation structures includes an insulating material that extends continuously within the first portion and the second portion, and
the insulating material includes at least one of silicon oxide, silicon nitride, or silicon carbide.
Fig.5A of Lee teaches a semiconductor memory device that includes an isolation insulating pattern 180 surrounding a conductive layer 182b. The isolation insulating pattern 180 may include a nitride layer, an oxynitride layer, or an oxide layer (page 6, col.2, para.004).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the isolation insulating pattern 180 of Lee in the teachings of Sanuki in order to provide electrical isolation.
Claims 14 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Sanuki et al. (US11257802B2) in view of Jung et al. (US20210202458A1).
Regarding claim 14, Fig.3 of Sanuki further teaches the semiconductor device of claim 1, wherein:
the gate electrode layers WL (col.3, line 41) extend to have different lengths in a horizontal direction,
Sanuki does not teach wherein each gate electrode layer including a gate pad region having a lower surface that is exposed downwardly,
wherein the semiconductor device further includes:
an upper wiring structure;
gate contacts connected to the upper wiring structure and extending into the pattern structure through the gate pad regions of the gate electrode layers; and
an insulating structure alternately arranged with the interlayer insulating layers on the gate pad regions and surrounding the gate contacts, respectively.
Fig.3 of Jung teaches a semiconductor device that includes a second chip structure CS2 that may include a gate wiring structure 162 and plurality of horizontal layers 150 that may include pad regions 150p; wherein the pad regions 150p of the plurality of horizontal layers 150 may have a stepped structure lowered in a direction close to the conductive material pattern 175a and wherein respective lengths of the horizontal layers 150 in the stack may decrease with distance from the conductive material pattern 175a (para.0047, 0060).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the gate wiring structure and the pad regions of Jung in the teachings of Sanuki in order to provide electrical connection (Jung, [para.0153]).
Regarding claim 16, Jung further teaches the semiconductor device of claim 14, wherein a lower surface of each of the gate contacts 162 (para.0060) is coplanar with a lower surface of each of the channel structures 132 (para.0037).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VINCENT KIPKEMOI RONO whose telephone number is (571)270-5977. The examiner can normally be reached Mon-Fri, 8am-5pm.
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VINCENT KIPKEMOI. RONO
Examiner
Art Unit 2891
/V.K.R./Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891
Prosecution Insights