DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 3-6 & 8-20 have been considered but are moot because the new ground of rejection argument.
Drawings
Figure 1 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated, see paragraph [0024] and [0041] which states “Figure 1 depicts a conventional control architecture 10”. See MPEP § 608.02(g). Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the ““each of the active wide-bandgap transistor and the reference wide-bandgap transistor is configured to receive a respective radio-frequency signal” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 20 is objected to because of the following informalities:
In Claim 20, line 2, recites the limitation of “active wide-bandgap devices” should correctly be ---active wide-bandgap transistors---.
In Claim 20, line 3-4, recites the limitation of “the reference wide-bandgap device is utilized for each of the active wide-bandgap devices”---. Should change to read as ---the reference wide-bandgap transistor is utilized for each of the active wide bandgap transistors---.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In Claim 4, the recitation of “each of the active wide-bandgap transistor and the reference wide-bandgap transistor is configured to receive a respective radio-frequency signal” is unclear the reference wide-bandgap transistor appear acts as reference transistor which does not amplify signal and it appear that only active transistor Q1 appear receive the RF signal. Further clarification is needed. Claims 5 & 6 are rejected because they depend on claim 4.
For the purpose of the examining, the examiner interpret claim as best understood, see claims 4-6 as discussing following.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4-6, 8-11 & 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Griffiths et al. (US 20090051435 A1, hereinafter Griffiths).
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Regarding claim 1:
Griffiths discloses in Figs. 1 & 2 a semiconductor chip (integrated circuit, paragraph [0017] comprising:
a substrate (substrate 14, Fig. 1);
an active wide-bandgap transistor (transistor 42) implemented on the substrate; and
a reference wide-bandgap transistor (transistor 76) implemented on the substrate, the reference wide-bandgap transistor configured to provide a response to a condition that also affects the active wide-bandgap transistor, each of the active wide-bandgap transistor (resistor 70 which provides bias signal to gate terminal of transistor 42) and the reference wide-bandgap transistor (a resistor 72 which provides bias signal to gate terminal of transistor 76) configured to receive a respective bias signal during operation.
Regarding claim 4:
Griffiths discloses wherein each of the active wide-bandgap transistor (transistor 42) and the reference wide-bandgap transistor (transistor 76) is configured to receive a respective radio-frequency signal (signal 20).
Regarding claim 5:
Griffiths discloses wherein the active wide-bandgap transistor (42) and the reference wide-bandgap transistor (76) are arranged in a mirror device configuration with a resistance (resistor 84) provided between gates of the active wide-bandgap transistor and the reference wide-bandgap transistor.
Regarding claim 6:
Griffiths discloses wherein the radio-frequency signal (20) received by the reference wide-bandgap transistor (transistor 76) is representative of the radio-frequency signal (20) received by the active wide-bandgap transistor (transistor 42).
Regarding claim 8:
Griffiths discloses wherein the bias signal provided to the reference wide-bandgap transistor (76) is adjusted in response to the condition during the operation (selective switches 74 for biasing signal).
Regarding claim 9:
Griffiths discloses wherein the adjusted bias signal includes an adjustment resulting from a feedback during the operation (see Fig. 2, feedback from drain to gate of transistor 76).
Regarding claim 10:
Griffiths discloses wherein the adjusted bias signal for the reference wide-bandgap transistor (transistor 76) is utilized as a reference for generation of the bias signal for the active wide-bandgap transistor (transistor 42).
Regarding claim 11:
Griffiths discloses wherein each of the active wide-bandgap transistor (42) and the reference wide-bandgap transistor (76) is configured as a field-effect transistor (as seen from Fig. 2) having a gate, a drain and a source.
Regarding claim 17:
Griffiths discloses wherein the active wide-bandgap transistor(42) and the reference wide-bandgap transistor (76) are physically separate from each other.
Regarding claims 18 & 19:
Griffiths discloses wherein the active wide-bandgap transistor (42) and the reference wide-bandgap transistor (76) share a common portion (both connected to common ground which share at least a common portion); and wherein the common portion includes a common source region (both source terminals of transistors 42 and 73 being connected to same common ground which appears same common portion and includes same source area).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Griffiths et al. (US 20090051435 A1, hereinafter, Griffiths).
Regarding claim 20:
Griffiths discloses all the limitations as applied in claim 1 except for further comprising one or more additional active wide-bandgap devices implemented on the substrate, such that the response provided by the reference wide-bandgap device is utilized for each of the active wide-bandgap devices.
It would have been obvious to one of ordinary skill in the art at the time the invention was made to add one or more additional active wide-bandgap devices implemented on the substrate, such that the response provided by the reference wide-bandgap device is utilized for each of the active wide-bandgap devices since it has been held that mere duplication of essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Claims 1, 3-6, 8-11 & 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Su et. Al. (US 20140043102 A1, hereinafter, Su) in view of Griffiths et al. (US 20090051435 A1, hereinafter, Griffiths).
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Regarding claim 1:
Su discloses in Fig. 5 a semiconductor chip (see paragraph [0046, chip) comprising:
an active wide-bandgap transistor (transistor 320); and
a reference wide-bandgap transistor (transistor 320R), the reference wide-bandgap transistor (transistor 320R) configured to provide a response to a condition that also affects the active wide-bandgap transistor (transistor 320), each of the active wide-bandgap transistor and the reference wide-bandgap transistor configured to receive a respective bias signal (see bias circuit 450, which provide a bias signal Vbias to transistor 320R and provide bias signal to gate terminal of transistor 320 through inductor LS) during operation.
Su does not explicitly disclose the active wide-bandgap transistor and the reference wide-bandgap device transistor implemented on a substrate.
Griffiths discloses in Figs. 1 & 2 an amplifier circuit 22 which form on a semiconductor substrate 14.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have implemented transistors of Su on the substrate as taught by Griffiths in order to provide the benefits saving
valuable area on semiconductor substrate (see paragraph [0034], [0036], occupy less area on substrate 14) and further stabilizing the quiescent bias point of the amplifier.
Regarding claim 3:
The combination (Su in view of Griffiths) further discloses wherein the active wide-bandgap transistor (transistor 320, Fig. 5) is configured to receive and process a radio-frequency signal (RF_IN), and the reference wide-bandgap transistor is configured to not receive a radio-frequency signal.
Insofar Claim 4 is understood:
The combination (Su in view of Griffiths) further discloses wherein
Regarding claim 5:
The combination (Su in view of Griffiths) further discloses wherein the active wide- bandgap transistor (transistor 320) and the reference wide-bandgap transistor (transistor 320R) are arranged in a mirror device configuration with a resistance (resistance of resistor RB) provided between gates of the active wide- bandgap transistor and the reference wide-bandgap transistor.
Insofar Claim 6 is understood:
The combination (Su in view of Griffiths) further discloses wherein
Regarding claim 8:
The combination (Su in view of Griffiths) further discloses wherein the bias signal provided to the reference wide-bandgap transistor (transistor 320R, bias signal being adjusted by bias circuit block 450, where circuit OA1 compares condition signals V1 and V2) is adjusted in response to the condition during the operation.
Regarding claim 9:
The combination (Su in view of Griffiths) further discloses wherein the adjusted bias signal includes an adjustment resulting from a feedback (see circuit OA1 and feedback and paragraph [0034], feedback configuration of OA1) during the operation.
Regarding claim 10:
The combination (Su in view of Griffiths) further discloses wherein the adjusted bias signal for the reference wide-bandgap transistor (transistor 320R) is utilized as a reference for generation of the bias signal for the active wide-bandgap transistor.
Regarding claim 11:
The combination (Su in view of Griffiths) further discloses wherein each of the active wide-bandgap transistor (transistor 320) and the reference wide-bandgap transistor (transistor 320R) is configured as a field-effect transistor having a gate, a drain and a source (FETs transistors as seen from Fig. 5 above).
Regarding claim 17:
The combination (Su in view of Griffiths) further discloses wherein the active wide-bandgap transistor (transistor 320) and the reference wide-bandgap transistor(transistor 320R) are physically separate from each other.
Regarding claim 18:
The combination (Su in view of Griffiths) further discloses wherein the active wide-bandgap transistor and the reference wide-bandgap transistor share a common portion (no common portion being defined by the applicant, broadly, at least common portion of the substrate).
Regarding claim 19:
The combination (Su in view of Griffiths) further discloses wherein the common portion includes a common source region (both sources transistors 320 and 320 being connected to common ground).
Regarding claim 20:
The combination (Su in view of Griffiths) discloses further comprising one or more additional active wide-bandgap devices implemented on the substrate, such that the response provided by the reference wide-bandgap device is utilized for each of the active wide-bandgap devices.
Claims 12-16 are rejected under 35 U.S.C. 103 as being unpatentable over the combination (Su in view of Griffiths) in view of Tiren et al. (US 6,522,203 B1, of record), hereinafter called Tiren.
Regarding claim 12:
The combination (Su in view of Griffiths) further discloses all of the limitations as applied in claim 11 and wherein transistor 320R being parallel with transistor 320 except for wherein the field-effect transistor has a finger configuration, such that each gate having a width is implemented between the respective drain and source.
Tiren discloses in Figs. 6a & 6b, an electronics circuit having transistors being connect parallel wherein transistors having finger arrangement (Fig. 6a of Tiren, source 3, gate 7 which included width and drain 5).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the combination (Su in view of Griffiths) to have the field-effect transistor has a finger configuration, such that each gate having a width is implemented between the respective drain and source as taught by Tiren. Such a modification would have imparted the advantageous benefit of improving cooling of the chip and efficient use of chip area (Col. 2, lines 21-24, also see Col. 4, last paragraph, “cooling of the chip can be better” as taught by Tiren, to the combination (Su in view of Griffiths) reference, thereby suggesting the obviousness of such a modification.
Regarding claim 13:
The combination (Su and Griffiths in view of Tiren) further discloses wherein the active wide-bandgap transistor is implemented as a multi-finger transistor (Figs. 6a, 6b) having multiple gates interleaved between alternating source and drain regions (Fig. 6a), and the reference wide-bandgap transistor is implemented to have one or more gates interleaved between alternating source and drain regions, the number of gate(s) of the reference wide-bandgap transistor being less than the number of gates of the active wide-bandgap transistor (known in advance which considered as intended use, see Quaglietta, of record, as shown in Fig. 6, two transistors 102 and one transistor 104).
Regarding claim 14:
The combination (Su and Griffiths in view of Tiren) further discloses the reference wide-bandgap transistor has one finger (Fig. 5 of Su, transistor 320R).
Regarding claims 15 & 16:
The combination (Su and Griffiths in view of Tiren) discloses the limitations as applied in claim 12 except for wherein the reference wide- bandgap transistor has at least one scaled-down dimension relative to the active wide- bandgap transistor; and wherein the scaled-down dimension includes the width of the gate. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have characterized the reference wide-bandgap transistor has at least one scaled-down dimension relative to the active wide- bandgap transistor; and wherein the scaled-down dimension includes the width of the gate, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHIEM D NGUYEN whose telephone number is (571)270-3941. The examiner can normally be reached Mon-Fri 8:00 AM-5:00 PM EST.
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/KHIEM D NGUYEN/Examiner, Art Unit 2843
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