Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1 – 10) in the reply filed on 7/21/2026 is acknowledged.
Claims 11 – 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected device and method, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 7/21/2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 – 6, 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Vadlamani (US 20190198436).
Regarding claim 1, Vadlamani discloses a motherboard, comprising:
a first layer (the layer comprising the structures 206, Fig. 2I) with a first trace with a shape;
a layer comprising insulating material (the core substrate 221) over the first layer; and
a second layer with a second trace (another layer 206 on top of layer 221) with the shape over the layer, wherein the second trace is provided directly over the first trace (Fig. 2m), and wherein the first trace is electrically coupled to the second trace by one or more vias (207) through the layer.
Regarding claim 2, Vadlamani discloses the claimed invention as set forth in claim 1. Vadlamani further discloses the one or more vias (207) are at a first end of the shape (end of 206, Fig. 2m) and/or a second end of the shape.
Regarding claim 3, Vadlamani discloses the claimed invention as set forth in claim 1. Vadlamani further suggests a magnetic block (110, 210) embedded in the insulating layer between the first trace and the second trace.
Regarding claim 4, Vadlamani discloses the claimed invention as set forth in claim 4. Vadlamani further suggests the magnetic block is secured to the insulating layer by an adhesive or, wherein the magnetic block is press fitted to the insulating layer (the block 110 and/or 210 is fitted into the insulating layer of the substrate).
Regarding claim 5, Vadlamani discloses the claimed invention as set forth in claim 1. Vadlamani further suggests the first trace and the second trace form an inductor (the inductor 250, Fig. 2m) that is integrated into the motherboard.
Regarding claim 6, Vadlamani discloses the claimed invention as set forth in claim 5. Vadlamani further suggests the inductor is part of a voltage regulator (paragraph 29) or part of a noise filtering circuit.
Regarding claim 9, Vadlamani discloses the claimed invention as set forth in claim 1. Vadlamani further discloses a second insulator (layer 201, Fig. 2e) over the second layer; and a third layer with a third trace (top layer 206) with the shape over the second insulating layer, wherein the third trace is provided directly over the first trace and the second trace (Fig. 2e).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 7, 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Vadlamani (US 20190198436), in view of Ji (US 12131861).
Regarding claim 7, Vadlamani discloses the claimed invention as set forth in claim 1.
Vadlamani does not explicitly disclose the shape is an S-shape.
Ji suggests the inductor having component with S-shape (Fig. 36).
It would have been obvious to one having skill in the art at the effective filing date of the invention to modify the shape of the component in order to make a component function as intended such as an inductor in this case.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Vadlamani (US 20190198436), in view of Hill (US 20200020652).
Regarding claim 8, Vadlamani discloses the claimed invention as set forth in claim 1.
Vadlamani does not explicitly disclose the shape is a U-shape.
Hill suggests the inductor having component with U-shape (Fig. 1D).
It would have been obvious to one having skill in the art at the effective filing date of the invention modify the shape of the component in order to make a component function as intended such as an inductor in this case.
Allowable Subject Matter
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons for Allowance
The following is an examiner’s statement of reasons for allowance:
Regarding claim 1, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claim 1, a combination of limitations that the first trace and the second trace have a first width, and wherein an adjacent third trace has a second width, wherein the first width is greater than the second width. None of the reference art of record discloses or renders obvious such a combination.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Shekhar (US 20200051884) discloses an inductor in a circuit board, Fig. 1.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH B TRAN whose telephone number is (571)272-9289. The examiner can normally be reached M-F 8:00 AM - 6:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy J Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/BINH B TRAN/Primary Examiner, Art Unit 2847
Prosecution Insights