Attorney’s Docket Number: Q281249
Filing Date: 03/13/2023
Claimed Foreign Priority Date: 06/08/2022 (KR 10-2022-0069224)
Applicants: Hong et al.
Examiner: Younes Boulghassoul
DETAILED ACTION
This Office action responds to the Amendment filed on 12/04/2025.
Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment
The Amendment filed on 12/04/2025, responding to the Office action mailed on 09/04/2025, has been entered. The present Office action is made with all the suggested amendments being fully considered. Accordingly, pending in this application are claims 1-20.
Response to Amendment
Applicant’s amendments to the Claims have overcome the respective claim rejections under 35 U.S.C. 112, 35 U.S.C. 102, and 35 U.S.C. 103, as previously formulated in the Non-Final Office action mailed on 09/04/2025. However, the previously presented prior art remains relevant, and new grounds of rejection are presented below, as required by Applicant’s amendments to the claims.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-6, 8, 12, and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (US2016/0351570).
Regarding Claim 1, Park (see, e.g., Figs. 1-2, 7-9 and 10; and Par. [0085]) shows all aspects of the instant invention, including a semiconductor device (e.g., semiconductor device 100) comprising:
- a first gate structure (e.g., gate structure 140 of transistor 100A in region I) on a substrate (e.g., substrate 101), the first gate structure extending in a second direction (e.g., X direction) parallel to an upper surface of the substrate
- a first source/drain layer (e.g., source/drain 110) at a side of the first gate structure in a first direction (e.g., Y direction), the first direction being substantially parallel to the upper surface of the substrate and crossing the second direction, and a central portion in the first direction of an upper surface of the first source/drain layer being lower than an edge portion in the first direction of the upper surface of the first source/drain layer (see, e.g., Fig. 7A, cut A-A’, for a clear view of 110 shape prior to contact plug formation: upper surface of 110 has a central recessed portion RS and two opposing edge portions in the Y direction)
- a first contact plug (see, e.g., contact plug comprising 170,180) on the first source/drain layer, the first contact plug contacting the edge portion of the upper surface of the first source/drain layer so that a center of the first contact plug is offset from a center of the upper surface in the first direction of the first source/drain layer (see, e.g., Fig. 10 and Par. [0085]: contact hole C1 is biased/offset toward left gate 140, with contact recess RSC1 formed at left edge portion of 110)
- wherein the first contact plug (see, e.g., 170,180) partially contacts a portion of the first source/drain layer (e.g., 110) between a lowermost point of the first source/drain layer and an uppermost point of the first source/drain layer, and wherein the lowermost point is a center of the central portion (see, e.g., Applicant Annotated Fig. 10: 170,180 does contact 110 at least between the lowermost point and the uppermost point of 110, on the left side of annotated dashed vertical line)
Regarding Claim 2, Park (see, e.g., Figs. 7A, cut A-A’ or 13A, cut A-A’) shows that the upper surface of the first source/drain layer (e.g., 110) is concave (e.g., at least due to the shape of RS or RS’).
Regarding Claim 3, Park (see, e.g., Fig. 13A, cut A-A’) shows that a slope of the upper surface of the first source/drain layer (e.g., 110) with respect to the upper surface of the substrate gradually increases from the central portion to the edge portion of the upper surface (e.g., at least due to the shape of RS’).
Regarding Claim 5, Park (see, e.g., Figs. 2A and 19A; and Par. [0105]-[0109]) shows that a cross-section of the first source/drain layer (e.g., 110/110b in region I) in the second direction has a shape of a pentagon or a rhombus.
Regarding Claim 6, Park (see, e.g., Figs. 9A and 10) shows a gate spacer (e.g., sidewall spacers 150) on each of opposite sidewalls of the first gate structure in the first direction, wherein the first contact plug is spaced apart from a sidewall of the gate spacer in the first direction.
Regarding Claim 8, Park (see, e.g., Figs. 1-2, 7-9) shows:
- a second gate structure (e.g., gate structure 240 of transistor 100B in region II) on the substrate, the second gate structure extending in the second direction
- a second source/drain layer (e.g., sources/drain 210) at a side of the second gate structure in the first direction, a central portion in the first direction of an upper surface of the second source/drain layer not being lower than an edge portion in the first direction of the upper surface of the second source/drain layer (see, e.g., Fig. 7A, cut B-B’, for a clear view of 210 shape prior to contact plug formation: upper surface of 210 is substantially flat)
- a second contact plug (see, e.g., contact plug 270,280) on the second source/drain layer, the second contact plug contacting the central portion of the upper surface of the second source/drain layer (see, e.g., Fig. 9A, cut B-B’).
Regarding Claim 12, Park (see, e.g., Figs. 9A and 10; and Par. [0034]) discloses that transistor 100A in region I is a FinFET. Therefore, Park shows that the first gate structure (e.g., 140) protrudes from the upper surface of the substrate in a vertical direction (e.g., Z direction) substantially perpendicular to the upper surface of the substrate.
Regarding Claim 18, Park (see, e.g., Figs. 1-2, 7-9 and 10; and Par. [0085]) shows all aspects of the instant invention, including a semiconductor device (e.g., semiconductor device 100) comprising:
- first gate structures (e.g., gate structures 140 of transistor 100A in region I) on a substrate (e.g., substrate 101) including a first region and a second region (e.g., region I and region II respectively), the first gate structures being spaced apart from each other in a first direction (e.g., Y direction) by a first distance on the first region of the substrate, each of the first gate structures extending in a second direction (e.g., X direction), each of the first direction and the second direction being substantially parallel to an upper surface of the substrate, and the first direction crossing the second direction
- a first source/drain layer (e.g., source/drain 110) on a portion of the substrate between the first gate structures, a central portion in the first direction of an upper surface of the first source/drain layer being lower than an edge portion in the first direction of the upper surface of the first source/drain layer (see, e.g., Fig. 7A, cut A-A’, for a clear view of 110 shape prior to contact plug formation: upper surface of 110 has a central recessed portion RS and two opposing edge portions in the Y direction)
- a first contact plug (see, e.g., contact plug comprising 170,180) on the first source/drain layer, the first contact plug contacting the edge portion of the upper surface of the first source/drain layer so that a center of the first contact plug is offset from a center of the upper surface of the first source/drain layer (see, e.g., Fig. 10 and Par. [0085]: contact hole C1 is biased toward left gate 140, with contact recess RSC1 formed at left edge portion of 110)
- second gate structures (e.g., gate structures 240 of transistor 100B in region II) on the substrate, the second gate structures being spaced apart from each other in the first direction by a second distance on the second region of the substrate, each of the second gate structures extending in the second direction
- a second source/drain layer (e.g., source/drain 210) on a portion of the substrate between the second gate structures, a central portion in the first direction of an upper surface of the second source/drain layer not being lower than an edge portion in the first direction of the upper surface of the second source/drain layer (see, e.g., Fig. 7A, cut B-B’, for a clear view of 210 shape prior to contact plug formation: upper surface of 210 is substantially flat)
- a second contact plug (see, e.g., contact plug comprising 270,280) on the second source/drain layer, the second contact plug contacting the central portion of the upper surface of the second source/drain layer (see, e.g., Fig. 9A, cut B-B’)
- wherein the first contact plug (see, e.g., 170,180) partially contacts a portion of the first source/drain layer (e.g., 110) between a lowermost point of the first source/drain layer and an uppermost point of the first source/drain layer, and wherein the lowermost point is a center of the central portion (see, e.g., Applicant Annotated Fig. 10: 170,180 does contact 110 at least between the lowermost point and the uppermost point of 110, on left side of dashed vertical line)
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US2016/0351570).
Regarding Claim 14, Park (see, e.g., Figs. 1-2, 7-9 and 10; and Par. [0085]) shows most aspects of the instant invention, including a semiconductor device (e.g., semiconductor device 100) comprising:
- a gate structure (e.g., gate structure 140 of transistor 100A in region I) on a substrate (e.g., substrate 101), the gate structure extending in a second direction (e.g., X direction) parallel to an upper surface of the substrate
- a first source/drain layer and a second source/drain layer at opposite sides, respectively, in a first direction of the gate structure (e.g., pair of source/drain 110 flanking 140 in the Y direction), the first direction being substantially parallel to the upper surface of the substrate and crossing the second direction, and a central portion in the first direction of an upper surface of each of first source/drain layer and the second source/drain layer being lower than an edge portion in the first direction of the upper surface (see, e.g., Fig. 7A, cut A-A’, for a clear view of 110s shape prior to contact plug formation: upper surface of 110 has a central recessed portion RS and two opposing edge portions in the Y direction)
- a first contact plug and a second contact plug (see, e.g., Fig. 9A: pair of contact plugs comprising 170,180 flanking 140 in the Y direction) on the first source/drain layer and the second source/drain layer, respectively,
- wherein the first contact plug contacts one edge portion of opposite edge portions of the upper surface of the first source/drain layer so that a center of the first contact plug is offset from a center of the one edge portion of the upper surface of the first source/drain layer, the one edge portion being proximal to the gate structure in the first direction (see, e.g., Fig. 10 and Par. [0085]: one contact hole C1 is biased to the left toward left gate 140, with contact recess RSC1 formed at left edge portion of 110 and proximal to 140)
- wherein the first contact plug (see, e.g., 170,180) partially contacts a portion of the first source/drain layer (e.g., 110) between a lowermost point of the first source/drain layer and an uppermost point of the first source/drain layer, and wherein the lowermost point is a center of the central portion (see, e.g., Applicant Annotated Fig. 10: 170,180 does contact 110 at least between the lowermost point and the uppermost point of 110, on left side of dashed vertical line)
Furthermore, since Park shows that: 1/ contact plugs are formed between neighboring gates 140 (see, e.g., Fig. 9A); and 2/ that at least one of said contacts can be formed in a contact hole C1 that is offset to the left from a S/D region 110 center (see, e.g., Fig. 10); it would have been obvious to one of skill in the art to have the second contact plug arranged such that it contacts one edge portion of opposite edge portions of the upper surface of the second source/drain layer so that a center of the second contact plug is offset from a center of the one edge portion of the upper surface of the second source/drain layer, the one edge portion being distal to the gate structure in the first direction, because such second contact plug arrangement would flow from a repetition of the offset contact arrangement at the second source/drain layer of the pair of source/drain 110 flanking 140 in the Y direction; and the Court has held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced. In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).
Regarding Claim 15, Park (see, e.g., Figs. 7A, cut A-A’ or 13A, cut A-A’) shows that the upper surface of each of the first source/drain layer and the second source/drain layer (e.g., 110) is concave (e.g., at least due to the shape of RS or RS’).
Regarding Claim 16, Park (see, e.g., Figs. 9A and 10) shows a first gate spacer and a second gate spacer on opposite sidewalls (e.g., sidewall spacers 150), respectively, in the first direction of the gate structure, wherein the first contact plug is spaced apart from a sidewall of the first gate spacer in the first direction.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US2016/0351570) in view of Joe et al. (US2019/0363009).
Regarding Claim 4, while Park (see, e.g., Figs. 7A, cut A-A’ or 13A, cut A-A’) discloses that upper surfaces of S/D regions 110 can be concave, he is silent about said upper surfaces being shaped such that a slope of the upper surface of the first source/drain layer with respect to the upper surface of the substrate gradually increases from the central portion to a given portion of the upper surface and gradually decreases from the given portion to the edge portion of the upper surface.
Initially, with regards to the particular source/drain layer upper surface shape and resulting slopes, it is noted that the specification fails to provide teachings about the criticality of having said upper surface with slopes as claimed. Therefore, absent any criticality, this limitation is only considered to be an obvious modification of the source/drain layer upper surface shape and slopes thereof disclosed by Park, as the courts have held that a change in shape or configuration, without any criticality, is within the level of skill in the art, and the particular S/D upper surface shape claimed by applicant is nothing more than one of numerous S/D upper surface shapes that a person having ordinary skill in the art will find obvious to provide as a matter of choice, or using routine experimentation based on its suitability for the intended use of the invention. See In re Daily, 149 USPQ 47 (CCPA 1976).
Additionally, the claimed shape of the upper surface of the first source/drain layer and resulting slopes is known in the art. Joe (see, e.g., Fig. 16-18), in the same field of endeavor, teaches that a S/D region 130 can have an upper surface with a plurality of different profiles, such as convex (see, e.g., Fig. 16), concave (see, e.g., Fig. 18), or such that a slope of the upper surface of the source/drain layer 130F with respect to the upper surface of the substrate 110F gradually increases from the central portion to a given portion of the upper surface and gradually decreases from the given portion to the edge portion of the upper surface (see, e.g., Fig. 17).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the upper surface of the first source/drain layer as claimed in the structure of Park, because said upper surface shape and slopes thereof are known in the semiconductor art as one of plurality of shapes for implementing S/D regions in FinFETs, as suggested by Joe, and implementing a known S/D region profile for its conventional use would have been a common sense choice by the skilled artisan. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
Claims 7 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US2016/0351570) in view of Yeo et al. (US2016/0308008).
Regarding Claim 7, Park (see, e.g., Figs. 9-10 and Par. Par. [0085]) discloses that a S/D contact 170,180 can be formed with a contact hole C1 biased towards one of a pair of adjacent gate structures 140, such that intervening dielectric layer 154 may remain. Therefore, although not explicitly depicted, Park contemplates the possibility of an alternative embodiment where etch-stop layer 154 may not remain, resulting in S/D contact 170,180 contacting a sidewall of the gate spacer 150 in the first direction Y.
Furthermore, and in the same field of endeavor, Yeo (see, e.g., Fig. 3B and 4) teaches that such contact arrangement is known, i.e., a source/drain contact CA can be arranged as separated from a neighboring gate spacer 125 in a direction D2, or offset towards a gate structure and in contact with the neighboring gate spacer (see, e.g., Fig. 3B vs. Fig. 4).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have the first contact plug contacting a sidewall of the gate spacer in the first direction in the structure of Park, because it is known in the semiconductor art that S/D contacts can be spaced from or, in the alternative, be in contact with neighboring gate spacers, as suggested by Yeo, and implementing a known electrical connection arrangement for its conventional use would have been a common sense choice by the skilled artisan. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
Regarding Claim 17, Park (see, e.g., Figs. 9A and 10) shows a first gate spacer and a second gate spacer on opposite sidewalls (e.g., sidewall spacers 150), respectively, in the first direction of the gate structure. However, Park is silent about the first contact plug contacting a sidewall of the first gate spacer in the first direction. Also, see comments stated above in Par. 30-32 with regards to Claim 7, which are considered repeated here.
Claims 9-11, 13, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US2016/0351570) in view of Jao et al. (US2022/0359677).
Regarding Claims 9-11, while Park (see, e.g., Figs. 9-10) discloses gates 140 in region I and gates 240 in region II, he is silent about a width in the first direction of the first gate structure is greater than a width in the first direction of the second gate structure; a width in the first direction of the first source/drain layer is greater than a width in the first direction of the second source/drain layer; or the first gate structure is one of a plurality of first gate structures spaced apart from each other in the first direction by a first distance, and the second gate structure is one of a plurality of second gate structures spaced apart from each other in the first direction by a second distance less than the first distance.
Additionally, Jao (see, e.g., Figs. 1A-D) in the same filed of endeavor, teaches a device 10 having transistors arranged in a first region 20D,20E and in a second region 20A,20B,20C, wherein the transistors have respective gates structures 200D-E and 200A-C extending in a second direction Y, and arranged along a first direction X, and wherein:
- a width in the first direction X of the first gate structure (e.g., one of 200D-E) is greater than a width in the first direction of the second gate structure (e.g., one of 200A-C), as required by claim 9
- a width in the first direction X of the first source/drain layer (e.g., wide S/D 82) is greater than a width in the first direction of the second source/drain layer (e.g., narrow S/D 82), as required by claim 10
- the first gate structure (e.g., one of 200D-E) is one of a plurality of first gate structures spaced apart from each other in the first direction X by a first distance, and the second gate structure (e.g., one of 200A-C) is one of a plurality of second gate structures spaced apart from each other in the first direction by a second distance less than the first distance, as required by claim 11.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have any one of the gate widths arrangement, the source/drain layer widths arrangement, or the gate spacings arrangement as required by respective claims 9-11 in the structure of Park, because it is known in the semiconductor art that gate widths, source/drain layer widths, or gate spacings are recognized design parameters for implementing a semiconductor device comprising multiple regions of non-planar transistors, as suggested by Jao, and implementing known non-planar transistor arrangements for their conventional use would have been a common sense choice by the skilled artisan. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
Furthermore, with regards to the first and second widths or first and second distances arranged as claimed, the courts have held that differences in widths/distances will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such widths/distances are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation”. In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality (see next paragraph below) of the claimed arrangements of first and second widths or first and second distances, and since Jao teaches first and second widths/distances arrangements commonly known in the art to implementing a semiconductor device comprising multiple regions of non-planar transistors, it would have been obvious to one of ordinary skill in the art to use these arrangements in the device of Park.
CRITICALITY: The specification contains no disclosure of either the critical nature of the claimed first and second widths/distances arrangements or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen variables are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1939 (Fed. Cir. 1990).
Regarding Claim 13, while Park (see, e.g., Figs. 9-10 and Par. [0034]) discloses that his invention is directed to non-planar transistors such as FinFETs, he is silent about having channels spaced apart from each other in a third direction on an active pattern, as well as the remaining associated limitations. Jao (see, e.g., Figs. 1A-D), on the other hand and in the same field of endeavor, teaches that his invention is related to three-dimensional fin-line FETs (FinFETs), or gate-all-around (GAA) devices, wherein, the gate-all-around (GAA) devices comprise channels (e.g., semiconductor channels 22Ax-22Bx-22Cx) spaced apart from each other in a third direction (Z direction) on an active pattern (e.g., base fin 322), wherein a first gate structure (e.g., one of 200D-E) covers lower and upper surfaces and each of opposite sidewalls in the second direction of each of the channels Jao (see, e.g., Fig. 10B).
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed of have the channels and first gate structure arranged as claimed in the structure of Park, because it is known in the semiconductor art that FinFET and Gate-all-around transistors are alternate transistor architectures for implementing non-planar devices, as suggested by Jao, and implementing a known non-planar transistor architecture for its conventional use would have been a common sense choice by the skilled artisan. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
Regarding Claims 19-20, while Park (see, e.g., Figs. 9-10) discloses gates 140 in region I and gates 240 in region II, he is silent about the first distance is greater than the second distance, or a width in the first direction of the first source/drain layer is greater than a width in the first direction of the second source/drain layer.
Additionally, Jao (see, e.g., Figs. 1A-D) in the same filed of endeavor, teaches a device 10 having transistors arranged in a first region 20D,20E and in a second region 20A,20B,20C, wherein the transistors have respective gates structures 200D-E and 200A-C extending in a second direction Y, and arranged along a first direction X, and wherein:
- the first gate structure (e.g., one of 200D-E) is one of a plurality of first gate structures spaced apart from each other in the first direction X by a first distance, and the second gate structure (e.g., one of 200A-C) is one of a plurality of second gate structures spaced apart from each other in the first direction by a second distance, the first distance being greater than the second distance, as required by claim 19.
- a width in the first direction X of the first source/drain layer (e.g., wide S/D 82) is greater than a width in the first direction of the second source/drain layer (e.g., narrow S/D 82), as required by claim 20.
Also, see comments stated above in Par. 37-40 with regards to Claim 9-11, which are considered repeated here.
Response to Arguments
Applicant’s arguments with respect to the claims filed on 12/04/2025 have been considered but have not been found persuasive:
Applicant argues:
“[A]ccording to the amended claim, the first contact plug 282 can contact the first source/drain laver 192 even if the first contact plug 282 is not formed deep enough to contact the lowest point (center) of the source/drain layer”; and “By contrast, in Park, […] the contact plug 186 contacts the center of the recess RS, which is the lowest point of the source/drain 110 (refer to FIG. 10, as follows):” (see, e.g., Remarks, Page 12-13)
The examiner responds:
The examiner respectfully disagrees. Initially, in response to applicant's arguments that the Park reference fails to show the claimed amended feature arrangement, it is noted that the examiner is entitled to the broadest reasonable interpretation of the claim language. Additionally, although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Therefore, while the examiner agrees with applicant’s interpretation of the disclosure of Park, i.e., the contact plug contacting the center of the recess RS which is the lowest point of the source/drain 110 (see, e.g., Applicant Annotated Fig. 10), the examiner does not understand the amended limitation “wherein the first contact plug partially contacts a portion of the first source/drain layer between a lowermost point of the first source/drain layer and an uppermost point of the first source/drain layer” as precluding the contact plug from also contacting the first source/drain layer at other locations, including said lowermost point.
As such, since the body of amended claims 1, 14, and 18 merely requires that the first contact plug partially contacts a portion of the first source/drain layer between a lowermost point of the first source/drain layer and an uppermost point of the first source/drain layer, and since Park discloses that contact plug 170,180 does contact 110 at least between the lowermost point and the uppermost point of 110, the amended limitations as recited in the body of the claims are deemed met by Park, as detailed in the new rejections supra.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Younes Boulghassoul whose telephone number is (571) 270-5514. The examiner can normally be reached Monday-Friday 9am-6pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YOUNES BOULGHASSOUL/Primary Examiner, Art Unit 2814