DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Information Disclosure Statement
The information disclosure statement filed on 03/13/2023 and 12/15/2025 have been considered.
Drawings
The drawings filed on 03/132/2023 are acceptable.
Specification
The abstract of the disclosure and the specification filed on 03/13/2023 are acceptable.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 10-15, and 17 is/are rejected under 35 U.S.C. 102a1 as being anticipated by Tai (US 2021/0118806).
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Regarding claim 1, Tai (US 2021/0118806) discloses:
A semiconductor package, comprising:
a substrate (carrier 11, ¶0020) having a first surface (111) and a second surface that are opposite to each other (112);
a redistribution layer (carrier 10 including redistribution layer 10r, ¶0017) provided on the first surface (111) of the substrate (11), the redistribution layer having a third (102) surface and a fourth surface (101, ¶0017) that are opposite to each other, the third surface (102) of the redistribution layer facing the first surface (111) of the substrate (11);
a semiconductor chip (electronic component 13, ¶0024) provided between the substrate (11) and the redistribution layer (10), the semiconductor chip (13) being spaced apart from the first surface (111) of the substrate (10) and electrically connected (at least through conductive pillars 13p, ¶0024) to the third surface (102) of the redistribution layer (10);
a connection structure (11p, ¶0020) provided between the substrate (11) and the redistribution layer (10) and horizontally spaced apart from the semiconductor chip (13), the connection structure being configured to electrically connect the substrate and the redistribution layer (¶0020); and
a first dielectric layer (package body 16, ¶0025) provided between the substrate (11) and the redistribution layer (10), wherein the semiconductor chip (13) and the connection structure (11p) are provided in the first dielectric layer (16).
Regarding claim 2, Tai further discloses:
wherein the substrate (11) is a printed circuit board (“carrier 11 is a circuit layer”, ¶0020).
Regarding claim 10, Tai further discloses:
wherein a lateral surface of the substrate (11) is exposed without being covered with the first dielectric layer (16).
Regarding claim 11, Tai further discloses:
wherein a lateral surface of the substrate (11), a lateral surface of the first dielectric layer (16), and a lateral surface of the redistribution layer (10) are aligned with each other along a direction perpendicular to the first surface of the substrate (11).
Regarding claim 12, Tai further discloses;
wherein the semiconductor chip (13) is configured to electrically connect to the substrate (11) through the redistribution layer (10) and the connection structure (11p).
Regarding claim 13, Tai does further discloses:
at least one first upper semiconductor chip (12a, ¶0022) on the fourth surface (101) of the redistribution layer (10), wherein the at least one first upper semiconductor chip (12a) is configured to electrically connect to the fourth surface of the redistribution layer (¶0022).
Regarding claim 14, the prior art does not disclose “wherein the redistribution layer comprises a third dielectric layer and a plurality of redistribution patterns in or on the third dielectric layer, the at least one first upper semiconductor chip comprises a plurality of first upper chip pads, the plurality of first upper chip pads are configured to electrically connect to first redistribution patterns, among the plurality of redistribution patterns, and the first redistribution patterns are adjacent to the fourth surface of the redistribution layer” in combination with the remaining claimed features.
Regarding claim 15, Tai further discloses:
an upper semiconductor package (12a, ¶0022 discloses the additional 12a can be a package) provided on the fourth surface of the redistribution layer; and
a plurality of connection bumps between the redistribution layer and the upper semiconductor package (¶0022, figure 1), wherein the connection bumps and the at least one first upper semiconductor chip (12a) are horizontally spaced apart from each other between the redistribution layer and the upper semiconductor package, wherein the connection bumps are configured to electrically connect the upper semiconductor package and the redistribution layer (¶0022).
Regarding claim 17, Tai further discloses:
an upper semiconductor package (12a, ¶0022) provided on the fourth surface of the redistribution layer; and a plurality of connection bumps between the redistribution layer and the upper semiconductor package, wherein the connection bumps are configured to electrically connect the upper semiconductor package and the redistribution layer (¶0022).
Regarding claim 21, Tai discloses:
A semiconductor package, comprising:
a substrate (11);
a redistribution layer (10) provided on the substrate (11);
a dielectric layer (16) provided between the substrate (11) and the redistribution layer (10), and comprising:
a semiconductor chip (13);
a plurality of connection structures (11p) spaced apart from each other, and from the semiconductor chip, the plurality of connection structures being configured to electrically connect the substrate and the redistribution layer (¶0020).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tai.
Regarding claim 9, Tai does not disclose “wherein the first dielectric layer comprising a dielectric film comprising a thermosetting resin” .
However, ¶0018 and 0025 disclose an Ajinmoto Build-up film (thermosetting resin) as one of several preferred materials for executing a dielectric layer in the disclosed device. It would have been obvious to one of ordinary skill in the art at the time the claimed invention was made to provide a thermosetting resin as claimed, since it has been held by the courts that selection of a prior art material on the basis of its suitability for its intended purpose is within the level of ordinary skill. In re Leshing, 125 USPQ 416 (CCPA 1960) and Sinclair & Carroll Co. v. Interchemical Corp., 65 USPQ 297 (1945).
Claim(s) 18 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen (US 2018/028888) in view of Tai.
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Regarding claim 18, Chen (US 2018/0288886) discloses:
A semiconductor package comprising:
a substrate (insulating substrate 20, ¶0030) comprising a first surface (20a) and a second surface (20b) that are opposite to each other;
a redistribution layer (24, ¶0041) provided on the first surface (20a) of the substrate (20), the redistribution layer (24) having a third surface and a fourth surface that are opposite to each other, the third surface of the redistribution layer facing the first surface of the substrate; and
wherein the substrate (20) is a printed circuit board (insulating substrate 20 includes circuit layers 211 and 212, ¶0030), and wherein the substrate (20) comprises:
a wiring dielectric layer (20, ¶0030);
a plurality of upper wiring patterns (211, ¶0030) exposed on surface in the wiring dielectric layer (20) and adjacent to the first surface (20a) of the substrate (20);
a plurality of lower wiring patterns (212,¶030) exposed on surface (20b) on the wiring dielectric layer (20) and adjacent to the second surface (20b) of the substrate; and
a mask layer (surrounding conductive elements 270, figure 2d, ¶0050)adjacent to the second surface of the substrate and adjacent to the plurality of lower wiring patterns.
Chen does not disclose “at least one sub-semiconductor chip provided on the fourth surface of the redistribution layer”. In a similar device, however, Tai discloses a semiconductor package comprising a substrate (11) comprising a first surface (111) and a second surface (112) that are opposite to each other;
a redistribution layer (10) provided on the first surface (111) of the substrate (10), the redistribution layer (10) having a third surface (102) and a fourth surface (101) that are opposite to each other, the third surface (102) of the redistribution layer facing the first surface (111) of the substrate (11) and at least one sub-semiconductor chip (12b, ¶022) provided on the fourth surface (101) of the redistribution layer (10). Tai discloses that a structure as taught provides a package with increased functionality (¶0022). Therefore, it would have been obvious to one having skill in the art before the effective filing date of the claimed invention to modify the device of Chen including providing at least one sub-semiconductor chip provided on the fourth surface of the redistribution layer in order to provide the advantages as taught by Tai.
Regarding claim 19, Tai further discloses:
wherein the redistribution layer (24) comprises:
a redistribution dielectric layer, a plurality of redistribution patterns provided in the redistribution dielectric layer, and a plurality of redistribution vias provided in the redistribution dielectric layer and connected to the redistribution patterns, and wherein first redistribution vias, among the plurality of redistribution vias, are connected to the plurality of upper wiring patterns (211) of the substrate (20, figure 2b).
Allowable Subject Matter
Claims 3-8, 16 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 3, Tai does not disclose ”wherein the substrate comprises a second dielectric layer and a plurality of upper wiring patterns buried in the second dielectric layer, the plurality of upper wiring patterns being adjacent to the first surface of the substrate, and the connection structure is connected to a first upper wiring pattern among the plurality of upper wiring patterns” in combination with the remaining claimed features.
Regarding claim 6, the prior art does not disclose “wherein the redistribution layer comprises a third dielectric layer, a plurality of redistribution patterns in the third dielectric layer, and a plurality of redistribution vias in the third dielectric layer, the plurality of redistribution vias being connected to the redistribution patterns, and at least one of the redistribution vias penetrates a portion of the first dielectric layer and is connected to the connection structure.” In combination with the remaining claimed features.
Regarding claim 16, the prior art does not disclose “wherein the upper semiconductor package comprises; an upper substrate; at least one second upper semiconductor chip provided on the upper substrate; and an upper mold layer provided on the upper substrate and the at least one second upper semiconductor chip, wherein the connection bumps are configured to electrically connect to substrate pads of the upper substrate” in combination with the remaining claimed features.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM A HARRISTON whose telephone number is (571)270-3897. The examiner can normally be reached Mon-Fri, 9AM-5PM.
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/WILLIAM A HARRISTON/ Primary Examiner, Art Unit 2899