This is a copy of the original Detailed Action, reproduced to correct the
Office Action Summary mailed 1/30/2026. All claims 1-20 should had been indicated to be pending and rejected.
A SHORTENED STATUTORY PERIOD FOR REPLY IS SET TO EXPIRE 3 MONTHS FROM THE MAILING DATE OF THIS COMMUNICATION.
DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4-9, and 15-16 are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Kenneth K. Yu et. al., hereinafter Yu, (US 5086477 A).
Regarding claim 1,
Yu discloses
An integrated circuit (IC) layout extraction system comprising:
(Yu, ABSTRACT “A system for extracting design information from a semiconductor integrated circuit (IC) is disclosed.”)
a microscope
(Yu, ABSTRACT “The system includes a microscope and camera for capturing a composite image of the IC in the form of a video signal.”)
an electronic processor
(Yu, ABSTRACT “An image processor receives the video signal from the optical means and generates an abstract representation of the die in the form of lists of identifying features such as the size, type and relative location of all transistors, and the width, length and relative location of all of the metal interconnects to the IC.”)
a display operatively connected with the electronic processor
(Yu, col. 10, lines 44-47 “The selected image region or tile is then subjected to image processing/filtering algorithms to produce an enhanced image which can be displayed on a CRT monitor along side the original image.”)
and a non-transitory storage medium storing instructions readable and executable by the electronic processor to perform an IC layout extraction method including
(Yu, col. 2, lines 13-19 “This image capture operation continues until a "photographic" image of all of the sections of the die has been obtained. Central to the capture process is the fact that the table means is responsive to a control signal delivered by a microprocessor or computer, which enables the IC to be repositioned relative to the optical means.”)
(Yu, col. 4, lines 15-25 “The system of FIG. 1 also includes a controller/file server 13 which interfaces between the image capturing and processing unit 14, disk memory unit 12 and the computer workstation. Within controller 13 is stored the image construction software in block 15. The image construction software contains specific algorithms and routines whose purpose is to analyze the stored image and reconstruct the circuit under inspection. Control software for directing the design verification process is also resident within block 15 of the computer controller..”)
performing an iterative method N times to extract N layout portions of an IC wherein the performing of each iteration of the iterative method includes
(Yu, col. 10, lines 10-18 “Once the computer divides the area of the die to be captured into a matrix of overlapping screen images (i.e., tiles), the actual image capture process may proceed. That is, individual screen images or tiles are digitized by the microprocessor in unit 14 and the resulting pixel data stored in memory 12. The microscope and camera 10 is then instructed by the processor to move to the next screen image to be captured and the process of digitization is repeated.”)
(i) receiving a tile image of a tile of the IC acquired by the microscope
(Yu, col. 10, lines 10-15 “Once the computer divides the area of the die to be captured into a matrix of overlapping screen images (i.e., tiles), the actual image capture process may proceed. That is, individual screen images or tiles are digitized by the microprocessor in unit 14 and the resulting pixel data stored in memory 12.”)
and (ii) extracting a layout portion from the tile image;
(Yu, col. 19-30 “Next, the photographic image of the die is processed by the computer system (including the image processing routines contained in block 15) to generate another, more condensed and abstract representation of the die. This "intermediate" form of the IC image contains layout geometry information, lists of features detected, and their relative positions. These lists provide a means by which rapid and accurate identification of individual circuit cells can be performed. By way of example, the lists usually contain the types and locations of individual transistors along with the relative locations of their connecting terminals.”)
and combining the extracted N layout portions to form an extracted layout for the IC.
(Yu, col. 4, lines 25-28 “The end result of the execution of the software routines stored in block 15 is the extracted circuit and/or layout information in the form of a schematic or netlist.”)
(Yu, col. 4, lines 48-53 “Thus, using the image processing system of FIG. 1, along with some of the algorithmic techniques to be described shortly, the procedure of extracting design and layout information from a piece of silicon material is greatly automated, thereby shortening the reverse engineering or design cycle.”)
(Yu, col. 16, lines 31-35 “There are two important outputs of image construction software block 15. One is the design information in the form of a schematic netlist as described above. The other important output is the layout data provided on a layer-by-layer basis.”)
Regarding claim 2
Yu teaches all the features of claim 1 as disclosed above.
Yu discloses further,
The IC layout extraction system of claim 1 wherein the non-transitory storage medium further stores a reference IC layout and each iteration further includes:
(Yu, col. 2 lines 33-42 “A memory means is employed for storing the captured images, the abstract representations and also a reference library of circuit elements. The reference library of circuit elements preferably contains the raw pixel data for each of the reference circuits as well as an abstract representation in the form of descriptor lists of identifying circuit features. The reference library of circuits can be generated by collecting all of the unique and identified cells of the IC.”)
(Yu, col. 2 lines 46-50 “The computer means is also utilized for recognizing individual circuit cells by matching the abstract representation of a portion of the composite image with a corresponding entry in the reference library.”)
(Yu, col 6, lines 2-3 “Normally, the reference library is stored in disk memory or on tape.”)
(iii) comparing the extracted layout portion with a corresponding portion of the reference IC layout;
(Yu, col. 12, lines 62-68 “Referring now to FIG. 8, there is shown a flow diagram of the circuit recognition phase of the design verification process of the present invention. Circuit recognition is the process of matching small portions of the intermediate representation of the die to one of many "circuit templates" contained in the reference library.”)
(Yu, col. 14 lines 30-32 “The flow chart of FIG. 8 illustrates an alternative embodiment in which the circuit recognition process is accelerated with the assistance of a trained operator.”)
(Yu, col. 14 lines 46-52 “Next, for each circuit representation to be identified the operator first examines the intermediate representation of the die. Then, using a mouse, or some other input device, the operator draws a box or boundary around the circuit. The computer then searches through its reference circuit library looking for a circuit or cell that matches the operator-defined boundary region.”)
(Yu, col. 14 line 64 – col. 15, line 1 “After all extraneous metal has been removed from the visual field, the operator directs the computer to attempt a circuit identification by specifying one of three types searches to be performed. These searches are based on the relative size of the outlined circuit and the particular reference circuit specified.”)
and (iv) if the comparison does not satisfy an acceptance criterion then performing at least one remedial action.
(Yu, col.15, line 14-20 “If the computer finds a match which exceeds a predetermined threshold level, a successful match status is reported and the circuit template from the reference library is currently displayed in a window adjacent to the outline of the circuit area defined by the operator. The operator is then prompted whether he or she wishes to accept the computer's identification.”)
(Yu, col.15, lines 27-28 “If the operator rejects the identification, the search continues through the remaining reference library cells.”)
(Yu, col.15, lines 34-36 “In the event that the computer does not find a match which exceeds the predetermined matching threshold level, the operator has several options.”)
Regarding claim 4
Yu teaches all the features of the claims 1 and 2 as disclosed above. Yu discloses further,
The IC layout extraction system of claim 2 further comprising: at least one user input device;
(Yu, col. 14, lines 46-50 “Next, for each circuit representation to be identified the operator first examines the intermediate representation of the die. Then, using a mouse, or some other input device, the operator draws a box or boundary around the circuit.”)
wherein the non-transitory storage medium further stores a reference IC layout
(Yu, col. 5, line 66 - col. 6, line 3 “Existing artificial intelligence software programs are employed to examine the intermediate representation of the die and identify certain cells or circuits which are stored concurrently in a reference library. Normally, the reference library is stored in disk memory or on tape.”)
(Yu, col. 6, lines 11 – 16 “Utilizing a reference library of circuits stored either within the workstation or in disk memory 12, the computer system recognizes instances of reference library circuits identified on the die.”)
and the at least one remedial action includes displaying the extracted layout portion and the corresponding portion of the reference IC layout on the display
(Yu, col. 15, lines 14-18 “If the computer finds a match which exceeds a predetermined threshold level, a successful match status is reported and the circuit template from the reference library is currently displayed in a window adjacent to the outline of the circuit area defined by the operator.”)
and receiving an indication via the at least one user input device of whether to accept the extracted layout portion.
(Yu, col. 15, lines 14-18 “If the computer finds a match which exceeds a predetermined threshold level, a successful match status is reported and the circuit template from the reference library is currently displayed in a window adjacent to the outline of the circuit area defined by the operator. The operator is then prompted whether he or she wishes to accept the computer's identification.”)
Regarding claim 5
Yu teaches all the features of the claim 1 as disclosed above.
Yu discloses further
The IC layout extraction system of claim 1 wherein each iteration of the iterative method performed after the first iteration overlaps the performing of at least one preceding iteration in time.
(Yu, ABSTRACT “This image capture operation continues until a composite image of the IC is obtained by successive capture of contiguous or partially overlapping images covering all of the different sections of the die.”)
(Yu, col. 2 lines 8-15 “The image capture process occurs on a section-by-section basis in which a "snapshot" of a section is obtained by the optical means, the table means stepped so that a new section is positioned under the optical means, and a snapshot of the new section obtained. This image capture operation continues until a "photographic" image of all of the sections of the die has been obtained.”)
(Yu, col. 2 lines 19-23 This permits a composite image of the circuit to be obtained by successive capture of contiguous or partially overlapping images covering all of the different sections of the die.”)
Regarding claim 6
Yu teaches all the features of the claim 1 as disclosed above.
Yu discloses further
The IC layout extraction system of claim 1 wherein, for each iteration of the iterative method, the operation (ii) extracts the layout portion only from the tile image received by operation (i) of that same iteration.
(Yu, col. 10, lines 10-20 “Once the computer divides the area of the die to be captured into a matrix of overlapping screen images (i.e., tiles), the actual image capture process may proceed. That is, individual screen images or tiles are digitized by the microprocessor in unit 14 and the resulting pixel data stored in memory 12. The microscope and camera 10 is then instructed by the processor to move to the next screen image to be captured and the process of digitization is repeated. This continues until all of the screen images within the boundary areas established by the measurement grid are captured.”)
(Yu, col. 10, lines 30-35 “As a by-product, a more abstract "intermediate representation" of the captured image is produced. Both the original pixel representation "pieces" of the image, and the composite intermediate representation of the image are correlated and maintained for future use.”)
Regarding claim 7
Yu teaches all the features of the claim 1 as disclosed above.
Yu discloses further
The IC layout extraction system of claim 1 wherein the combining of the extracted N layout portions to form the extracted layout for the IC is performed after completion of all N iterations of the iterative method.
(Yu, col 10, lines 21-27 “After all of the "pieces" of the image layer are captured, a single composite image is then constructed. This is the primary function of the image construction software in block 15. Each tile or piece of the image must be positioned with respect to its neighboring tiles or images such that lines and features of the boundaries of adjacent tiles match up.”)
(Yu, col. 10, lines 65-68 “The computer then builds a composite image of the intermediate representation of the single layer by matching the features at the boundaries of adjacent pieces. The pixel pieces are then correlated with the composite intermediate representation for that layer and both are saved for later use in memory 12.”)
Regarding claim 8
Yu teaches all the features of the claim 1 as disclosed above.
Yu discloses further
The IC layout extraction system of claim 1 wherein each tile of the IC overlaps at least two other tiles of the image.
(Yu, col. 7, line 62- col. 8, line 4 “Because of the inherent mechanical imprecision of the image capture operation, each of the tiles is intentionally overlapped with one another to a certain extent. This ensures that no portion of the die will escape image capture. By way of example, in FIG. 2 the overlap between tile 26 and tile 27 is shown by the cross hatched region 28. Likewise, the overlap between tiles 27 and 29 is shown by the cross hatched region 25. The overlap of tiles 29 and 26 is represented by the intersection of regions 28 and 25.”)
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media_image1.png
528
430
media_image1.png
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It is very clear from the figure above that a tile will always overlap with at least two neighboring tiles.
Regarding claim 9
Yu teaches all the features of the claim 1 as disclosed above. Yu discloses further
The IC layout extraction system of claim 1 wherein the microscope comprises a scanning electron microscope (SEM) or an optical microscope.
(Yu, col. 7, lines 3-11 “Image capture begins with taking a magnified image of the wafer or die and inputting that image into a computer memory by means of a microscope and a video camera. Since the system presently relies on visible light, a standard microscope (e.g., 500X to 1000X magnification) and an ordinary imaging device such as a television or video camera may be utilized. In another embodiment, a scanning election microscope (SEM) is employed for greater magnification and resolution.”)
Regarding claim 15
Yu discloses
An integrated circuit (IC) layout extraction method comprising:
(Yu, col. 1, lines 7-11 “The present invention relates generally to the field of optical pattern recognition; more specifically, to methods for examining an existing integrated circuit (IC) to obtain various design and layout information”)
moving a field of view (FOV) of the microscope to a tile of the IC and acquiring a tile image of the next tile using the microscope;
(Yu, ABSTRACT “The system includes a microscope and camera for capturing a composite image of the IC in the form of a video signal.”)
(Yu, col. 3, lines 3-5 “FIG. 2 shows the image capture process whereby the visible features of the integrated circuit are optically recorded as a plurality of sections or tiles.”)
(Yu, col. 5, lines 7-9 “In accordance with the preferred embodiment, image capture is performed on a section-by-section or a "tile-by-tile" basis.”)
extracting a layout portion from the tile image
(Yu, col. 19-30 “Next, the photographic image of the die is processed by the computer system (including the image processing routines contained in block 15) to generate another, more condensed and abstract representation of the die. This "intermediate" form of the IC image contains layout geometry information, lists of features detected, and their relative positions. These lists provide a means by which rapid and accurate identification of individual circuit cells can be performed. By way of example, the lists usually contain the types and locations of individual transistors along with the relative locations of their connecting terminals.”)
repeating the operations (i) and (ii) for all tiles of the IC
(Yu, col. 10, lines 10-20 “Once the computer divides the area of the die to be captured into a matrix of overlapping screen images (i.e., tiles), the actual image capture process may proceed. That is, individual screen images or tiles are digitized by the microprocessor in unit 14 and the resulting pixel data stored in memory 12. The microscope and camera 10 is then instructed by the processor to move to the next screen image to be captured and the process of digitization is repeated. This continues until all of the screen images within the boundary areas established by the measurement grid are captured.”)
combining the extracted layout portions to form an extracted layout for the IC;
(Yu, col. 4, lines 25-28 “The end result of the execution of the software routines stored in block 15 is the extracted circuit and/or layout information in the form of a schematic or netlist.”)
(Yu, col. 4, lines 48-53 “Thus, using the image processing system of FIG. 1, along with some of the algorithmic techniques to be described shortly, the procedure of extracting design and layout information from a piece of silicon material is greatly automated, thereby shortening the reverse engineering or design cycle.”)
(Yu, col. 16, lines 31-35 “There are two important outputs of image construction software block 15. One is the design information in the form of a schematic netlist as described above. The other important output is the layout data provided on a layer-by-layer basis.”)
(i), (ii), (iii), and (iv) are performed using a computer.
(Yu, col. 2, lines 15-23 “Central to the capture process is the fact that the table means is responsive to a control signal delivered by a microprocessor or computer, which enables the IC to be repositioned relative to the optical means. This permits a composite image of the circuit to be obtained by successive capture of contiguous or partially overlapping images covering all of the different sections of the die.”)
(Yu, col. 2, lines 43-50 “A computer means coupled to the image processing and memory means is also included for combining the abstract representations of the captured images to obtain the composite image of the integrated circuit. The computer means is also utilized for recognizing individual circuit cells by matching the abstract representation of a portion of the composite image with a corresponding entry in the reference library.”)
Regarding claim 16
Yu teaches all the features of claim 15 as disclosed above.
Yu discloses further
The IC layout extraction method of claim 15 wherein the operation (ii) includes:(a) comparing the extracted layout portion with a corresponding portion of a reference IC layout
(Yu, col. 12, lines 62-68 “Referring now to FIG. 8, there is shown a flow diagram of the circuit recognition phase of the design verification process of the present invention. Circuit recognition is the process of matching small portions of the intermediate representation of the die to one of many "circuit templates" contained in the reference library.”)
(Yu, col. 14 lines 30-32 “The flow chart of FIG. 8 illustrates an alternative embodiment in which the circuit recognition process is accelerated with the assistance of a trained operator.”)
(Yu, col. 14 lines 46-52 “Next, for each circuit representation to be identified the operator first examines the intermediate representation of the die. Then, using a mouse, or some other input device, the operator draws a box or boundary around the circuit. The computer then searches through its reference circuit library looking for a circuit or cell that matches the operator-defined boundary region.”)
(Yu, col. 14 line 64 – col. 15, line 1 “After all extraneous metal has been removed from the visual field, the operator directs the computer to attempt a circuit identification by specifying one of three types searches to be performed. These searches are based on the relative size of the outlined circuit and the particular reference circuit specified.”)
and (b) if the comparison does not satisfy an acceptance criterion then performing at least one remedial action.
(Yu, col.15, line 14-20 “If the computer finds a match which exceeds a predetermined threshold level, a successful match status is reported and the circuit template from the reference library is currently displayed in a window adjacent to the outline of the circuit area defined by the operator. The operator is then prompted whether he or she wishes to accept the computer's identification.”)
(Yu, col.15, lines 27-28 “If the operator rejects the identification, the search continues through the remaining reference library cells.”)
(Yu, col.15, lines 34-36 “In the event that the computer does not find a match which exceeds the predetermined matching threshold level, the operator has several options.”)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Yu as applied to claims 1, 2, 15, and 16 above, respectively, and further in view of Joachim Wienecke et. al., hereinafter Wienecke (US 20070076943 A1).
Yu teaches all the features of the claims 1, 2, 15, and 16 as disclosed above.
Yu further teaches.
Claim3: The IC layout extraction system of claim 2 wherein the at least one remedial action includes repeating the operations (ii) and (iii) for the received re-acquired tile image.
Claim 17: The IC layout extraction method of claim 16 wherein the at least one remedial action includes
(Yu, col.15, lines 34-38 “In the event that the computer does not find a match which exceeds the predetermined matching threshold level, the operator has several options. First, the operator can redraw the boundaries of the circuit and try again.”)
(Yu, col. 3, lines 17-19 “FIG. 6 is a detailed flow diagram of the image capture process of the currently preferred embodiment of the present invention.”)
(Yu, col. 3, lines 23-24 “FIG. 8 is a detailed flow diagram of the circuit recognition process of the present invention.”)
(Yu, col. 4, lines 57-61 According to the currently preferred embodiment of the present invention, the method for extracting design information from an existing IC die or wafer is described by six basic high level steps. These steps are illustrated by the flow diagram of FIG. 5.)
Yu does not explicitly teach
Claim 3: wherein the at least one remedial action repeating the operation (i) to receive a re-acquired tile image that is re-acquired by the microscope.
Claim 17: repeating the operation (i) to re-acquire the tile image and repeating the operation (ii) for the re-acquired tile image
However, Wienecke explicitly teaches
Claim 3: wherein the at least one remedial action repeating the operation (i) to receive a re-acquired tile image that is re-acquired by the microscope.
Claim 17: repeating the operation (i) to re-acquire the tile image and repeating the operation (ii) for the re-acquired tile image
(Wienecke, p. 2, “[0033] Suitably it is provided that the re-imaging depends on one or more predefined threshold values. [0034] This is advantageous in that certain deviations of the image from the reference image are tolerated, and there is no erroneous detection of a defective image. [0035] … comparing whether each absolute difference value exceeds the threshold values; if the threshold values are exceeded, evaluating the image as defective; and causing the image to be re-imaged.”)
(Wienecke, p. 2, “[0037] It is advantageously provided for the image to be a partial image of the wafer. [0038] Recording of a partial image is thus evaluated as to whether or not the partial image is defective. It is only hereafter that the next partial image is recorded or the partial images are combined to form the overall image. [0039] This is advantageous in that the imaging errors of a partial image can be immediately corrected by re-imaging and in that the whole imaging process for the wafer does not have to be repeated.”)
Therefore, it would have been obvious before the effective priority date of the claim to a person having ordinary skill in the art to combine the teachings of Yu and Wienecke so that “the imaging errors of a partial image can be immediately corrected by re-imaging and in that the whole imaging process for the wafer does not have to be repeated.”
Claims 10, 12-14, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yu (US 5086477 A) in view of David F. Skoll, hereinafter Skoll (US 20020046386 A1)
Yu discloses
A non-transitory storage medium storing:
(Yu, col 4, lines 8-14 “The system of FIG. 1 also includes a disk memory 12 for storing the captured image, and an image capture and processing unit 14 for digitizing the image received from camera 10 and for performing certain image processing operations aimed at such things as contrast enhancement, reduction of stored data, etc.”)
a reference integrated circuit (IC) layout
(Yu, col. 6, lines 11-15 “Utilizing a reference library of circuits stored either within the workstation or in disk memory 12, the computer system recognizes instances of reference library circuits identified on the die.”)
and instructions readable and executable by an electronic processor to perform an IC layout extraction method including executing:
(Yu, col. 4, lines 15-22 “The system of FIG. 1 also includes a controller/file server 13 which interfaces between the image capturing and processing unit 14, disk memory unit 12 and the computer workstation. Within controller 13 is stored the image construction software in block 15. The image construction software contains specific algorithms and routines whose purpose is to analyze the stored image and reconstruct the circuit under inspection.”)
an image receiving pipeline that, for each tile n of N tiles of an IC, receives a tile image n of the tile n of the IC acquired using a microscope.
(Yu, col. 2, lines 1-20 “In one embodiment, the system of the present invention includes an optical means for capturing the image of a section of said IC in the form of a video signal. Normally, the optical means comprises a microscope and camera assembly which is positioned directly above a table means. The table means is used for placing the integrated circuit (in the form of a wafer or die) in position for image capture by the optical means. The image capture process occurs on a section-by-section basis in which a "snapshot" of a section is obtained by the optical means, the table means stepped so that a new section is positioned under the optical means, and a snapshot of the new section obtained. This image capture operation continues until a "photographic" image of all of the sections of the die has been obtained. Central to the capture process is the fact that the table means is responsive to a control signal delivered by a microprocessor or computer, which enables the IC to be repositioned relative to the optical means. This permits a composite image of the circuit to be obtained by successive capture of contiguous or partially overlapping images covering all of the different sections of the die.”)
a layout portion extraction pipeline that extracts a layout portion n from each received tile image n
(Yu, col. 2, lines 1-3 “In one embodiment, the system of the present invention includes an optical means for capturing the image of a section of said IC in the form of a video signal.”)
(Yu, col. 2, lines 8-13 “The image capture process occurs on a section-by-section basis in which a "snapshot" of a section is obtained by the optical means, the table means stepped so that a new section is positioned under the optical means, and a snapshot of the new section obtained.”)
(Yu, col 2. Lines 24-33 “The system of the present invention also comprises an image processing means for receiving the video signal from the optical means and for generating an abstract representation of said images therefrom. The abstract representation includes lists of identifying features of each of the sections along with the relative locations of each of the identifying features. Such features frequently include the size, type and relative location of all transistors, and the width, length and relative location of all of the metal interconnects on the IC.”)
and a layout portion comparison pipeline that compares each layout portion n with a corresponding portion of the reference IC layout
(Yu, col. 2, lines 19-23 “This permits a composite image of the circuit to be obtained by successive capture of contiguous or partially overlapping images covering all of the different sections of the die.”)
(Yu, col. 2, lines 24-27 “The system of the present invention also comprises an image processing means for receiving the video signal from the optical means and for generating an abstract representation of said images therefrom.”)
(Yu, col. 2, lines 43-50 “A computer means coupled to the image processing and memory means is also included for combining the abstract representations of the captured images to obtain the composite image of the integrated circuit. The computer means is also utilized for recognizing individual circuit cells by matching the abstract representation of a portion of the composite image with a corresponding entry in the reference library.”)
Note that a single tile image can also be considered as a portion of the composite image.
Yu does not teach
wherein the image receiving pipeline, the layout portion extraction pipeline, and the layout portion comparison pipeline are parallel pipelines that are executed by the electronic processor concurrently in time.
However, Skoll discloses
f. wherein the image receiving pipeline, the layout portion extraction pipeline, and the layout portion comparison pipeline are parallel pipelines that are executed by the electronic processor concurrently in time.
(p.2 [0023] “In accordance with the invention, there is further provided a system for extracting design and layout information from a plurality of image-mosaics representative of a deconstructed integrated circuit. The system comprises means for enabling parallel design analysis of the image-mosaics by a plurality of engineer analysts concurrently reverse engineering an IC.”)
Therefore, it would have been obvious before the effective priority date of the claim to a person having ordinary skill in the art to combine the teachings of Yu and Skoll and make the process of imaging, extraction of layout, and comparison parallel in order to shorten the whole process and reduce the time required to complete the task.
Regarding claim 12
Yu and Skoll teach all the features of the claim 10 as disclosed above. Yu discloses further
The non-transitory storage medium of claim 10 wherein the layout portion extraction pipeline extracts the layout portion n only from each corresponding tile image n and not from any other tile image received by the image receiving pipeline.
(Yu, col. 10, lines 10-20 “Once the computer divides the area of the die to be captured into a matrix of overlapping screen images (i.e., tiles), the actual image capture process may proceed. That is, individual screen images or tiles are digitized by the microprocessor in unit 14 and the resulting pixel data stored in memory 12. The microscope and camera 10 is then instructed by the processor to move to the next screen image to be captured and the process of digitization is repeated. This continues until all of the screen images within the boundary areas established by the measurement grid are captured.”)
(Yu, col. 10, lines 30-35 “As a by-product, a more abstract "intermediate representation" of the captured image is produced. Both the original pixel representation "pieces" of the image, and the composite intermediate representation of the image are correlated and maintained for future use.”)
Regarding claim 13
Yu and Skoll teach all the features of the claim 10 as disclosed above. Yu discloses further
The non-transitory storage medium of claim 10 wherein the IC layout extraction method further includes: combining of the extracted layout portions for the N tiles of the IC to form the extracted layout for the IC; wherein the combining is not part of the image receiving pipeline and is not part of the layout portion extraction pipeline and is not part of the layout portion comparison pipeline.
(Yu, col 10, lines 21-27 “After all of the "pieces" of the image layer are captured, a single composite image is then constructed. This is the primary function of the image construction software in block 15. Each tile or piece of the image must be positioned with respect to its neighboring tiles or images such that lines and features of the boundaries of adjacent tiles match up.”)
(Yu, col. 10, lines 65-68 “The computer then builds a composite image of the intermediate representation of the single layer by matching the features at the boundaries of adjacent pieces. The pixel pieces are then correlated with the composite intermediate representation for that layer and both are saved for later use in memory 12.”)
Regarding claim 14
Yu and Skoll teach all the features of the claim 10 as disclosed above. Yu discloses further
The non-transitory storage medium of claim 10 wherein the IC layout extraction method further includes executing: an image acquisition pipeline that, for each tile n of N tiles of an IC, controls the microscope to move a field of view (FOV) of the microscope to tile n of the IC and acquires a tile image n of the tile n using the microscope, the acquired tile image being received via the image receiving pipeline.
(Yu, col. 2, lines 1-20 “In one embodiment, the system of the present invention includes an optical means for capturing the image of a section of said IC in the form of a video signal. Normally, the optical means comprises a microscope and camera assembly which is positioned directly above a table means. The table means is used for placing the integrated circuit (in the form of a wafer or die) in position for image capture by the optical means. The image capture process occurs on a section-by-section basis in which a "snapshot" of a section is obtained by the optical means, the table means stepped so that a new section is positioned under the optical means, and a snapshot of the new section obtained. This image capture operation continues until a "photographic" image of all of the sections of the die has been obtained. Central to the capture process is the fact that the table means is responsive to a control signal delivered by a microprocessor or computer, which enables the IC to be repositioned relative to the optical means. This permits a composite image of the circuit to be obtained by successive capture of contiguous or partially overlapping images covering all of the different sections of the die.”)
Regarding claim 18
Yu and Skoll teach all the features of 10 and 14 as disclosed above. Yu teaches further
The IC layout extraction method of claim 14 wherein each repetition of the operations (i) and (ii) overlaps at least one preceding occurrence of the operations (i) and (ii) in time.
(Yu, col. 10, lines 10-20 “Once the computer divides the area of the die to be captured into a matrix of overlapping screen images (i.e., tiles), the actual image capture process may proceed. That is, individual screen images or tiles are digitized by the microprocessor in unit 14 and the resulting pixel data stored in memory 12. The microscope and camera 10 is then instructed by the processor to move to the next screen image to be captured and the process of digitization is repeated. This continues until all of the screen images within the boundary areas established by the measurement grid are captured.”)
(Yu, col. 10, lines 30-35 “As a by-product, a more abstract "intermediate representation" of the captured image is produced. Both the original pixel representation "pieces" of the image, and the composite intermediate representation of the image are correlated and maintained for future use.”)
Regarding claim 19
Yu and Skoll teach all the features of 10 and 14 as disclosed above. Yu teaches further
The IC layout extraction method of claim 14 wherein each repetition of the operation (ii) extracts the layout portion only from the tile image acquired by the occurrence of operation (i) immediately preceding in time.
(Yu, col. 10, lines 10-20 “Once the computer divides the area of the die to be captured into a matrix of overlapping screen images (i.e., tiles), the actual image capture process may proceed. That is, individual screen images or tiles are digitized by the microprocessor in unit 14 and the resulting pixel data stored in memory 12. The microscope and camera 10 is then instructed by the processor to move to the next screen image to be captured and the process of digitization is repeated. This continues until all of the screen images within the boundary areas established by the measurement grid are captured.”)
(Yu, col. 10, lines 30-35 “As a by-product, a more abstract "intermediate representation" of the captured image is produced. Both the original pixel representation "pieces" of the image, and the composite intermediate representation of the image are correlated and maintained for future use.”)
Regarding claim 20
Yu and Skoll teach all the features of 10 and 14 as disclosed above. Yu teaches further
The IC layout extraction system of claim 14 wherein the operation (iv) is started only after completion of the operation (iii).
(Yu, col 10, lines 21-27 “After all of the "pieces" of the image layer are captured, a single composite image is then constructed. This is the primary function of the image construction software in block 15. Each tile or piece of the image must be positioned with respect to its neighboring tiles or images such that lines and features of the boundaries of adjacent tiles match up.”)
(Yu, col. 10, lines 65-68 “The computer then builds a composite image of the intermediate representation of the single layer by matching the features at the boundaries of adjacent pieces. The pixel pieces are then correlated with the composite intermediate representation for that layer and both are saved for later use in memory 12.”)
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Yu and Skoll as applied to claim 10 above, and further in view of Wienecke (US 20070076943 A1).
Yu and Skoll teaches all the features of the claims 10 as disclosed above.
Yu modified by Skoll also teaches.
The non-transitory storage medium of claim 10 wherein: the image receiving pipeline operates on a queue of tiles of the IC;
(Yu, col.15, lines 34-38 “In the event that the computer does not find a match which exceeds the predetermined matching threshold level, the operator has several options. First, the operator can redraw the boundaries of the circuit and try again.”)
(Yu, col. 3, lines 17-19 “FIG. 6 is a detailed flow diagram of the image capture process of the currently preferred embodiment of the present invention.”)
(Yu, col. 3, lines 23-24 “FIG. 8 is a detailed flow diagram of the circuit recognition process of the present invention.”)
(Yu, col. 4, lines 57-61 According to the currently preferred embodiment of the present invention, the method for extracting design information from an existing IC die or wafer is described by six basic high level steps. These steps are illustrated by the flow diagram of FIG. 5.)
Yu modified by Skoll does not explicitly teach
and the layout portion comparison pipeline re-inserts the tile n into the queue of tiles for re-imaging in response to the comparison failing an acceptance criterion.
However, Wienecke explicitly teaches
and the layout portion comparison pipeline re-inserts the tile n into the queue of tiles for re-imaging in response to the comparison failing an acceptance criterion.
(Wienecke, p. 2, “[0033] Suitably it is provided that the re-imaging depends on one or more predefined threshold values. [0034] This is advantageous in that certain deviations of the image from the reference image are tolerated, and there is no erroneous detection of a defective image. [0035] … comparing whether each absolute difference value exceeds the threshold values; if the threshold values are exceeded, evaluating the image as defective; and causing the image to be re-imaged.”)
(Wienecke, p. 2, “[0037] It is advantageously provided for the image to be a partial image of the wafer. [0038] Recording of a partial image is thus evaluated as to whether or not the partial image is defective. It is only hereafter that the next partial image is recorded or the partial images are combined to form the overall image. [0039] This is advantageous in that the imaging errors of a partial image can be immediately corrected by re-imaging and in that the whole imaging process for the wafer does not have to be repeated.”)
Therefore, it would have been obvious before the effective priority date of the claim to a person having ordinary skill in the art to combine the teachings of Yu and Wienecke so that “the imaging errors of a partial image can be immediately corrected by re-imaging and in that the whole imaging process for the wafer does not have to be repeated.”
Claim Rejections - 35 USC § 112
Claims 15 and 18-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 15
Claim 15
An integrated circuit (IC) layout extraction method comprising: (i) moving a field of view (FOV) of the microscope to a tile of the IC and acquiring a tile image of the next tile using the microscope; (ii) extracting a layout portion from the tile image; (iii) repeating the operations (i) and (ii) for all tiles of the IC; and (iv) combining the extracted layout portions to form an extracted layout for the IC;wherein the operations (i), (ii), (iii), and (iv) are performed using a computer.
recites the limitation "the microscope" in line 2, and “next tile” in line 3. There is insufficient antecedent basis for this limitation in the claim.
By the way
“acquiring a tile image of the next tile” while “field of view (FOV) of the microscope (on) to a tile (is not possible).
“moving a field of view (FOV) of the microscope to a tile of the IC and acquiring (its) will be appropriate.
Regarding claim 18
Claim 18
The IC layout extraction method of claim 14 wherein each repetition of the operations (i) and (ii) overlaps at least one preceding occurrence of the operations (i) and (ii) in time.
recites the limitation " operations (i) and (ii)" in line 2 There is insufficient antecedent basis for this limitation in the claim.
This issue can easily be corrected by moving the dependency of 18 to 15 instead of 14.
Regarding claim 19
Claim 19
The IC layout extraction method of claim 14 wherein each repetition of the operation (ii) extracts the layout portion only from the tile image acquired by the occurrence of operation (i) immediately preceding in time.
recites the limitation "operations (i)" in “lines 2 and 3” There is insufficient antecedent basis for this limitation in the claim.
This issue can easily be corrected by moving the dependency of 18 to 15 instead of 14.
Regarding claim 20
Claim 20
The IC layout extraction system of claim 14 wherein the operation (iv) is started only after completion of the operation (iii).
recites the limitation " operation (iv)" in line 2 and “operation (iii)” in the line 2-3. There is insufficient antecedent basis for this limitation in the claim.
This issue can easily be corrected by moving the dependency of 18 to 15 instead of 14.
Conclusion
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/R.S./Examiner, Art Unit 2851
/JACK CHIANG/Supervisory Patent Examiner, Art Unit 2851