Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
DETAILED ACTION
This office action is in response to application 18/121143 filed on 03/14/23.
Claims 1-20 are remain pending in the application.
Oath/Declaration
The oath/declaration filed on March 14th, 2023 is acceptable.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bahadra et al. (U.S. Patent No. 20140325463).
As to claims 1 the prior art teaches a computer-implemented method for glitch debugging in an electronic design comprising:
receiving, using a processor, the electronic design (see paragraph 25 IC design);
performing a formal glitch analysis (verification IC) of the electronic design to determine if one or more glitches (see paragraph 0037) are present in a clock logic of the electronic design (see fig 6-8 paragraph 0025-0026 and 0034-0037);
if a glitch is identified, causing a generation of a graphical glitch debugger display (see figs. 1, 7-8 paragraph 0037-0039);
receiving an edit to the electronic design (see fig 8-10 paragraph 0038-0039);
re-performing the formal glitch analysis of the electronic design to determine whether a glitch is present (see fig 7-11 paragraph 0038-0042).
As to claims 2 and 14 the prior art teaches wherein causing the generation of the graphical glitch debugger display includes automatically generating one or more labels, colors, or icons at the display (see fig 7-8 paragraph 0036-0038).
As to claims 3 and 15, the prior art teaches wherein causing the generation of the graphical glitch debugger includes displaying a gate diagram showing a glitch path(see fig 7-8 paragraph 0039-0041).
As to claim 4 and 16, the prior art teaches wherein causing the generation of the graphical glitch debugger includes displaying a cycle by cycle waveform (see fig 8-11 paragraph 0040-0043).
As to claim 5 and 17, the prior art teaches wherein the formal glitch analysis includes an 8-value formal verification analysis on a target group of combinational loops (see fig 1-3 and 7-8 paragraph 0025-0030).
As to claim 6 and 18, the prior art teaches wherein a different color is used to highlight a number of different logic elements associated with a glitch path (see fig 2-7 paragraph 0029-0032).
As to claim 7 the prior art teaches wherein the number of different logic elements include one or more of glitch, late edge, and main gate (see fig 3-7 paragraph 0031-0034).
As to claim 8, the prior art teaches a non-transitory computer readable medium having stored thereon instructions, the instructions when executed by a processor resulting in one or more operations, the operations comprising:
receiving, using a processor, the electronic design (see paragraph 25 IC design);
performing a formal glitch analysis of the electronic design to determine if one or more glitches are present in a clock logic of the electronic design (see fig 6-8 paragraph 0025-0026 and 0034-0037);
and if a glitch is identified, causing a generation of a graphical glitch debugger display (see fig 7-8 paragraph 0037-0039),
wherein causing a generation of a graphical glitch debugger display includes a gate diagram showing a glitch path corresponding to the identified glitch (see fig 7-11 paragraph 0038-0042).
As to claim 15 the prior art teaches a system for electronic design synthesis, electronic design setup, and glitch signoff comprising:
a graphical user interface (see fig 1 paragraph 0029);
and at least one processor configured to receive, using a processor, the electronic design, the at least one processor further configured to perform a formal glitch analysis of the electronic design to determine if one or more glitches are present in a clock logic of the electronic design (see fig 6-8 paragraph 0025-0026 and 0034-0037),
if a glitch is identified, the at least one processor further configured to cause a generation of a graphical glitch debugger display via the graphical user interface, the at least one processor further configured to receive an edit to the electronic design at the graphical user interface (see fig 7-8 paragraph 0037-0039),
wherein the at least one processor is further configured to re-perform the formal glitch analysis of the electronic design to determine whether a glitch is present (see fig 7-11 paragraph 0038-0042).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH C TAT whose telephone number is 571 272-1908. The examiner can normally be reached on flex 7:00Am-8PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached on 571 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BINH C TAT/Primary Examiner, Art Unit 2851