DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s amendments necessitated the shift in grounds of rejection detailed below. The shift in grounds of rejection renders Applicant’s arguments moot.
Claim Rejections - 35 USC § 102
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-4, 8,11-13 is/are rejected under 35 U.S.C. 102(A)(1) as being anticipated by Mallik et al. (US-20200395313-A1; Mallik).
Regarding claim 1, Mallik discloses a semiconductor package, comprising: a package substrate (not shown;¶37); a plurality of semiconductor chips (Fig. 3A, 320A/320B/320C; ¶47) on the package substrate, and comprising: a first semiconductor chip (Fig. 3A, 320B; ¶47) ; a second semiconductor chip (Fig. 3A, 320A; ¶47) spaced apart from the first semiconductor chip in a first horizontal direction; and a third semiconductor chip (Fig. 3A, 320C; ¶47) spaced apart from the first semiconductor chip in a second horizontal direction; a plurality of interposers (Fig. 3B/3C, 330; ¶47) between the package substrate and the plurality of semiconductor chips, wherein each of the plurality of interposers are spaced apart from each other in a lateral direction; and a molding layer (Fig. 1A, 122/132; ¶37-38) in contact with the plurality of semiconductor chips (Fig. 3A, 320A/320B/320C; ¶47) and the plurality of interposers (Fig. 3B/3C, 330; ¶47), wherein the plurality of interposers comprise: a first vertical connection interposer(Fig. 3B/3C, 330; ¶47) vertically overlapping the first semiconductor chip (Fig. 3A, 320B; ¶47), and comprising a first through-electrode configured (Fig. 1A, 134; ¶35) to electrically couple the first semiconductor chip to the package substrate (not shown;¶37), a second vertical connection interposer (Fig. 3B/3C, another one of 330; ¶47) vertically overlapping the second semiconductor chip,(Fig. 3A, 320A; ¶47) and comprising a second through-electrode (Fig. 1A, 134; ¶35)configured to electrically couple the second semiconductor chip to the package substrate (not shown;¶37), a first horizontal connection interposer (Fig. 3A/3B/3C, 340; ¶47) vertically overlapping a portion of the first semiconductor chip (Fig. 3A, 320B; ¶47) and a first portion of the second semiconductor chip (Fig. 3A, 320A; ¶47), and comprising a first conductive connection structure (not shown in bridge 340;¶33,36,38) configured to electrically couple the first semiconductor chip to the second semiconductor chip, and a second horizontal connection interposer vertically (Fig. 3A/3B/3C, second one of 340; ¶47) overlapping a second portion of the second semiconductor chip (Fig. 3A, 320A; ¶47) and a portion of the third semiconductor chip (Fig. 3A, 320C; ¶47), and comprising a second conductive connection (not shown in bridge 340;¶33,36,38) structure configured to electrically couple the second semiconductor chip to the third semiconductor chip, wherein the semiconductor package further comprises first bump structures (Fig. 1A, 137; ¶37) between the first vertical connection interposer (Fig. 1A, 130; ¶34) and the package substrate (not shown;¶37) and between the second vertical connection interposer (Fig. 1A, 140; ¶34) and the package substrate, and wherein the first bump structures pass through the molding layer (Fig. 1A, 122/132; ¶37-38) to be in contact with interposer connection pads (Fig. 1A, 143; ¶37-38) of the first vertical connection interposer and the second vertical connection interposer.
Fig. 3A-3C represents a plan view and schematic view of Figures 1A-1B (¶48-49), where 140 is analogous to 340, 130 is analogous to 330, and 320 is analogous to 120. Figures 3A-3C do not show the molding layer and bumps shown in Fig. 1A.
Regarding claim 3, Mallik discloses the semiconductor package of claim 1, wherein the first vertical connection interposer (Fig. 1A, 130; ¶34) is disposed to prevent vertical overlap with the second semiconductor chip (Fig. 3A, 320A; ¶47), and wherein the second vertical connection interposer (Fig. 1A, second one of 130; ¶34) is disposed to prevent vertical overlap with the first semiconductor chip. (Fig. 3A, 320B; ¶47)
Regarding claim 4, Mallik discloses the semiconductor package of claim 1, further comprising first second bump structures (Fig. 3B, 384; ¶48) between the plurality of semiconductor chips (Fig. 3B, 320ABC; ¶48) and the plurality of interposers (Fig. 3B, 330; ¶48)
Regarding claim 8, Yu discloses the semiconductor package of claim 1, wherein the molding layer (Fig. 1A, 132/122; ¶37-38) extends along lower surfaces of the plurality of interposers (Fig. 1A, 130; ¶34) facing the package substrate (not shown; ¶37).
Regarding claim 11, Mallik discloses the semiconductor package of claim 1, wherein the molding layer comprises: a first molding layer (Fig. 1A, 132/122; ¶37-38) in contact with a sidewall of each of the plurality of interposers (Fig. 1A, 130; ¶37-38); and a second molding layer (Fig. 1A, 132/122; ¶37-38) in contact with a sidewall of each of the plurality of semiconductor chips. (Fig. 1A, 120; ¶37-38)
Regarding claim 12, Mallik discloses the semiconductor package of claim 11, wherein the first molding layer (Fig. 1A, 122/132 ¶37-38) is in contact with lower surfaces of the plurality of semiconductor chips (Fig. 1A,120; ¶37-38) facing the package substrate. (not shown; ¶37)
Regarding claim 13, Mallik discloses the semiconductor package of claim 11, wherein the second molding layer (Fig. 1A, 132/122; ¶37-38) is in contact with lower surfaces of the plurality of semiconductor chips (Fig. 1A, 120; ¶37-38) facing the package substrate.(not shown; ¶37)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2,9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mallik et al. (US-20200395313-A1; Mallik) in view of Yu et al. (US 20220223530 A1; Yu).
Regarding claim 2, Mallik discloses the semiconductor package of claim 1, but is silent on wherein the first semiconductor chip comprises a first logic chip, wherein the second semiconductor chip comprises a memory chip, and wherein the third semiconductor chip comprises a second logic chip.
Mallik discloses a package comprising memory devices but is silent on the memory semiconductor chips being memory and logic chips.
Yu discloses the semiconductor package of claim 1, wherein the first semiconductor chip (Fig. 1,LD/MD3 stack; ¶18-25) comprises a first logic chip (LD), wherein the second semiconductor chip (Fig. 1, middle LD/MD3 stack; ¶18-25) comprises a memory chip (MD3), and wherein the third semiconductor chip (Fig. 1,LD/MD3 stack; ¶18-25) comprises a second logic chip. (Fig. 1, LD; ¶22-25)
Before the effective filing date it would have been obvious to one having ordinary skill in the art to make the semiconductor chips logic and memory chips to form a high density multichip package.
Regarding claim 9, Mallik discloses the semiconductor package of claim 1, but is silent on wherein a first chip pad of the first semiconductor chip is directly coupled to a first interposer connection pad of the first vertical connection interposer, and wherein a second chip pad of the second semiconductor chip is directly coupled to a second interposer connection pad of the second vertical connection interposer.
Yu discloses wherein a first chip pad (Fig. 1A, 123; ¶39) of the first semiconductor chip (Fig. 3B, 320B; ¶48) is directly coupled to a first interposer connection pad (Fig. 1, top surface of 26A acts as a pad; ¶18-25) of the first vertical connection interposer (Fig. 1, MD; ¶18-25), and wherein a second chip pad (Fig. 1, 28; ¶18-25) of the second semiconductor chip (Fig. 1, middle LD/MD3 stack; ¶18-25) is directly coupled to a second interposer connection pad (Fig. 1, top surface of 26A acts as a pad; ¶18-25) of the second vertical connection interposer (Fig. 1, MD; ¶18-25).
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art use direct bonding instead of a bump connection structure to minimize process steps and overall package height. Also, one of ordinary skill in the art would have been capable of applying this known method of enhancement to a "base" device (method, or product) in the prior art and the results would have been predictable to one of ordinary skill in the art. The Supreme Court in KSR noted that if the actual application of the technique would have been beyond the skill of one of ordinary skill in the art, then using the technique would not have been obvious. See MPEP 2143 (C) /(D)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5,6,14-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mallik et al. (US-20200395313-A1; Mallik) in view of We et al. (US 20160141234 A1; We).
Regarding claim 5, Mallik discloses the semiconductor package of claim 4, wherein the second bump structures (Fig. 3B, 384; ¶48) comprise: conductive pillars (Fig. 1A, 136; ¶35) in contact with the plurality of interposers (Fig. 1A, 130; ¶34); but is silent on and first solder layers in contact with sidewalls and upper surfaces of the conductive pillars.
Fig. 3A-3C represents a plan view and schematic view of Figures 1A-1B (¶48-49), where 140 is analogous to 340, 130 is analogous to 330, and 320 is analogous to 120. Figures 3A-3C do not show the molding layer and bumps shown in Fig. 1A.
At issue is the type of connection which is known in the art, i.e. pillars, posts, and/or pads.. Mallik is silent on wherein the solder pads are pillars, solder layers are in contact with sidewalls of the conductive pillars and upper surfaces of the conductive pillars,
We discloses a package connection structure comprising a solder joint where a solder material (Fig. 9, 914; ¶102) is on a top surface and sidewalls of a pillar. (Fig. 9, 761; ¶102)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to form solder bumps around top surfaces and sidewalls of conductive pillars for making a sturdy physical and electric connection. Also, one of ordinary skill in the art would have been capable of applying this known method of enhancement to a "base" device (method, or product) in the prior art and the results would have been predictable to one of ordinary skill in the art. The Supreme Court in KSR noted that if the actual application of the technique would have been beyond the skill of one of ordinary skill in the art, then using the technique would not have been obvious. See MPEP 2143 (C) /(D)
Regarding claim 6, Mallik discloses the semiconductor package of claim 4, wherein the second bump structures (Fig. 3B, 384; ¶48) comprise: conductive pillars (Fig. 1A, 136; ¶35) in contact (electric) with the plurality of semiconductor chips (Fig. 1A, 120; ¶38); but is silent on and first solder layers in contact with sidewalls and lower surfaces of the conductive pillars.
Fig. 3A-3C represents a plan view and schematic view of Figures 1A-1B (¶48-49), where 140 is analogous to 340, 130 is analogous to 330, and 320 is analogous to 120. Figures 3A-3C do not show the molding layer and bumps shown in Fig. 1A.
At issue is the type of connection which is known in the art, i.e. pillars, posts, and/or pads.. Mallik is silent on wherein the solder pads are pillars, solder layers are in contact with sidewalls of the conductive pillars and upper surfaces of the conductive pillars,
We discloses a package connection structure comprising a solder joint where a solder material (Fig. 9, 914; ¶102) is on a bottom surface and sidewalls of a pillar. (Fig. 9, 912; ¶102)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to form solder bumps around bottom surfaces and sidewalls of conductive pillars for making a sturdy physical and electric connection. Also, one of ordinary skill in the art would have been capable of applying this known method of enhancement to a "base" device (method, or product) in the prior art and the results would have been predictable to one of ordinary skill in the art. The Supreme Court in KSR noted that if the actual application of the technique would have been beyond the skill of one of ordinary skill in the art, then using the technique would not have been obvious. See MPEP 2143 (C) /(D)
Regarding claim 14, Mallik discloses a semiconductor package, comprising: a package substrate (not shown;¶37); a plurality of interposers (Fig. 3B/3C, 330; ¶47) on the package substrate, and comprising a first vertical connection interposer (Fig. 3B/3C, 330; ¶47) , a second vertical connection interposer (Fig. 3B/3C, second one of 330; ¶47) , and a first horizontal connection interposer (Fig. 3A/3B/3C, 340; ¶47); a plurality of semiconductor chips comprising (Fig. 3A, 320A/320B/320C; ¶47)a first semiconductor chip (Fig. 3A, 320B; ¶47) electrically coupled to the package substrate through the first vertical connection interposer and a second semiconductor chip (Fig. 3A, 320A; ¶47) electrically coupled to the package substrate through the second vertical connection interposer (Fig. 3B/3C, second one of 330; ¶47) , the first semiconductor chip electrically coupled to the second semiconductor chip through a conductive connection structure (Fig. 3A/3B/3C, not shown in 340; ¶36,47) of the first horizontal connection interposer; first bump structures (Fig. 3A/3B/3C, 384; ¶48) between the plurality of interposers and the plurality of semiconductor chips, the first bump structures comprising conductive pillars (Fig. 1B, 184; ¶39) in contact with the plurality of interposers and first solder layers (Fig. 1B, 183; ¶39) extending from the conductive pillars to the plurality of semiconductor chips; second bump structures (Fig. 1A, 137; ¶37) between the plurality of interposers and the package substrate (not shown; ¶37); and a molding layer (Fig. 1A, 122/132; ¶37-38) in contact with the plurality of semiconductor chips and the plurality of interposers; wherein the second bump structures pass through the molding layer to be in contact with interposer connection pads of the plurality of interposers.
Fig. 3A-3C represents a plan view and schematic view of Figures 1A-1B (¶48-49), where 140 is analogous to 340, 130 is analogous to 330, and 320 is analogous to 120. Figures 3A-3C do not show the molding layer and bumps shown in Fig. 1A.
At issue is the type of connection which is known in the art, i.e. pillars, posts, and/or pads.. Mallik is silent on wherein the solder pads are pillars, solder layers are in contact with sidewalls of the conductive pillars and upper surfaces of the conductive pillars,
We discloses a package connection structure comprising a solder joint where a solder material (Fig. 9, 914; ¶102) is on a top surface and sidewalls of a pillar. (Fig. 9, 761; ¶102)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to form solder bumps around top surfaces and sidewalls of conductive pillars for making a sturdy physical and electric connection. Also, one of ordinary skill in the art would have been capable of applying this known method of enhancement to a "base" device (method, or product) in the prior art and the results would have been predictable to one of ordinary skill in the art. The Supreme Court in KSR noted that if the actual application of the technique would have been beyond the skill of one of ordinary skill in the art, then using the technique would not have been obvious. See MPEP 2143 (C) /(D)
Regarding claim 15, Mallik in view of We discloses the semiconductor package of claim 14, wherein the first solder layers are in contact with sidewalls of the conductive pillars and upper surfaces of the conductive pillars facing the plurality of semiconductor chips.
We discloses a package connection structure comprising a solder joint where a solder material (Fig. 9, 914; ¶102) is on a top surface and sidewalls of a pillar. (Fig. 9, 761; ¶102)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to form solder bumps around top surfaces and sidewalls of conductive pillars for making a sturdy physical and electric connection.
Regarding claim 16, Mallik in view of We discloses the semiconductor package of claim 14, wherein an upper surface of the molding layer (Fig. 1A, 122/132; ¶18-25) is coplanar with upper surfaces of the plurality of semiconductor chips (Fig. 1A, 120; ¶38).
Regarding claim 17, Mallik in view of We discloses the semiconductor package of claim 15, further comprising wherein the second bump structures (Fig. 1A, 137; ¶37) are attached to at least one of a lower surface of the first vertical connection interposer (Fig. 1A, 130; ¶34) and a lower surface of the second vertical connection interposer (Fig. 1A, a second one of 130; ¶34), wherein the molding layer (Fig. 1A, 132/122; ¶37-38) is in contact with the lower surface of the first vertical connection interposer and the lower surface of the second vertical connection interposer.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mallik et al. (US-20200395313-A1; Mallik) in view of We et al. (US 20160141234 A1; We), and further in view of Yu et al. (US 20220223530 A1; Yu).
Regarding claim 18, Mallik in view of We discloses the semiconductor package of claim 14, wherein the molding layer (Fig. 1A, 132/122; ¶37-38) comprises a first molding layer (Fig. 1A, 132; ¶37-38) in contact with a sidewall of each of the plurality of interposers (Fig. 1A, 130; ¶35), and a second molding layer (Fig. 1A, 122; ¶37-38) in contact with a sidewall of each of the plurality of semiconductor chips (Fig. 1A, 120; ¶38), wherein an upper surface of the second molding layer is coplanar with upper surfaces of the plurality of semiconductor chips, but is silent on and wherein a lower surface of the second molding layer is coplanar with lower surfaces of the plurality of semiconductor chips
Fig. 3A-3C represents a plan view and schematic view of Figures 1A-1B (¶48-49), where 140 is analogous to 340, 130 is analogous to 330, and 320 is analogous to 120. Figures 3A-3C do not show the molding layer and bumps shown in Fig. 1A.
Yu discloses a package structure comprising interposers (Fig. 1, MD1; ¶18-25) and chips (Fig. 1, sidewalls of LD; ¶18-25) thereon; a molding (Fig. 1, 132; ¶18-25) material that is coplanar with top and bottom surfaces of the chips. (Fig. 1A, LD; ¶18-25)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to expand the second molding material to be coplanar with bottom surfaces of the chips to simplify alignment of layers. Also, such a modification would have involved a mere change in the size or dimensions of the component. A change in size or relative dimensions is generally recognized as being within the level of ordinary skill in the art .. See MPEP 2144.04
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mallik et al. (US-20200395313-A1; Mallik) in view of Kang et al. (US 20190131203 A1; Kang).
Regarding claim 10, Mallik discloses the semiconductor package of claim 1, but is silent on further comprising a dummy chip in the molding layer.
Kang discloses a package device comprising a plurality of chips (Fig. 2, 100/200/300/400;¶22) on a common substrate, a dummy chip (Fig. 2, 130 ;¶44) for heat dissipation and a molding layer (Fig. 2, 720;¶35) encapsulating the chips and dummy chip.
Before the effective filing date it would have been obvious to one having ordinary skill in the art to add a dummy chip to the package for heat dissipation.
Claim(s) 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mallik et al. (US-20200395313-A1; Mallik) in view of Cho et al. (US 20200243450 A1; Cho).
Regarding claim 19, Mallik discloses a semiconductor package, comprising: a package substrate (not shown;¶37); a plurality of semiconductor chips (Fig. 3A, 320A/320B/320C; ¶47) on the package substrate, and comprising a first … chip (Fig. 3A, 320B; ¶47), a …chip spaced apart (Fig. 3A, 320A; ¶47) from the first … chip in a first horizontal direction, and a second … chip (Fig. 3A, 320C; ¶47) spaced apart from the first … chip in a second horizontal direction; a plurality of interposers (Fig. 3B/3C, 330; ¶47) between the package substrate and the plurality of semiconductor chips, wherein each of the plurality of interposers are spaced apart from each other in a lateral direction; first bump structures (Fig. 3B/3C, 384; ¶48) between the plurality of semiconductor chips and the plurality of interposers; second bump structures (Fig. 1A, 137; ¶37) between the plurality of interposers and the package substrate (not shown;¶37); and a molding layer (Fig. 1A, 132/122; ¶37-38) in contact with a sidewall of each of the plurality of semiconductor chips and a sidewall of each of the plurality of interposers, wherein the plurality of interposers comprise: a first vertical connection interposer (Fig. 3B/3C, 330; ¶47) vertically overlapping the first … chip (Fig. 3A, 320B; ¶47)and comprising a first through-electrode (Fig. 1A, 134; ¶35) configured to electrically couple the first … chip to the package substrate, a second vertical connection interposer (Fig. 3B/3C, second one of 330; ¶47) vertically overlapping the… chip (Fig. 3A, 320A; ¶47) and comprising a second through-electrode (Fig. 1A, 134; ¶35) configured to electrically couple the … chip to the package substrate, a third vertical connection interposer (Fig. 3B/3C, third one of 330; ¶47) vertically overlapping the second … chip (Fig. 3A, 320C; ¶47) and comprising a third through-electrode (Fig. 1A, 134; ¶35)configured to electrically couple the second… chip to the package substrate, a first horizontal connection interposer (Fig. 3A/3B/3C, 340; ¶47) vertically overlapping a first portion of the… chip (Fig. 3A, 320B; ¶47) and a first portion of the … chip (Fig. 3A, 320A; ¶47) and comprising a first conductive connection structure (Fig. 1A, 140 not shown ;¶38) configured to electrically couple the first …chip to the ….chip, and a second horizontal connection interposer (Fig. 3A/3B/3C,a second 340; ¶47) vertically overlapping a second portion of the first … chip and a second portion of the second … chip and comprising a second conductive connection structure (Fig. 1A, 140 not shown ;¶38) configured to electrically couple the first … chip to the second…chip, wherein the first horizontal connection interposer is disposed between the first vertical connection interposer and the second vertical connection interposer in the first horizontal direction, wherein the second horizontal connection interposer is spaced apart from the first vertical connection interposer in the second horizontal direction (Fig. 3A),wherein the first vertical connection interposer is spaced apart from the … chip and the second … chip, in a plan view (Fig. 3A), wherein the second vertical connection interposer is spaced apart from the first…chip and the second … chip, in a plan view (Fig. 3A), and wherein the third vertical connection interposer is spaced apart from the … chip and the first …chip, in a plan view.
Fig. 3A-3C represents a plan view and schematic view of Figures 1A-1B (¶48-49), where 140 is analogous to 340, 130 is analogous to 330, and 320 is analogous to 120. Figures 3A-3C do not show the molding layer and bumps shown in Fig. 1A.
Mallik discloses first second and third chips but is silent on the chips comprising a first logic chip, a memory chip spaced apart from the first logic chip in a first horizontal direction, and a second logic chip spaced apart from the first logic chip in a second horizontal direction
Cho discloses a semiconductor package comprising a plurality of chips comprising a first logic chip (Fig. 9, 221a; ¶92/88), a memory chip, (Fig. 9, 222c; ¶92/88) and a second logic chip (Fig. 9, 221b; ¶92/88)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art for the semiconductor chips to be first and second logic chips and a memory chip use in a high capacity network device such as a phone.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mallik et al. (US-20200395313-A1; Mallik) in view of Cho et al. (US 20200243450 A1; Cho) and further in view of We et al. (US 20160141234 A1; We),.
Regarding claim 20, Mallik in view of Cho discloses the semiconductor package of claim 19, wherein the first bump structures (Fig. 3B/3C, 384; ¶48) comprise: conductive pillars (Fig. 1B, 184; ¶398)in contact with the plurality of interposers (Fig. 3B/3C, second one of 330; ¶47), wherein the conductive pillars comprise copper (¶39); solder layers (Fig. 1B, 183; ¶39) extending from the conductive pillars to the plurality of semiconductor chips (Fig. 1B, 120; ¶38), …and wherein the second bump structures (Fig. 1A, 137; ¶37) pass through the molding laver (Fig. 1A, 132/122; ¶37-38) to be in contact with interposer connection pads (Fig. 1A, 133; ¶35) of the plurality of interposers.
At issue is the type of connection which is known in the art, i.e. pillars, posts, and/or pads.. Mallik is silent on wherein the solder pads are pillars, solder layers are in contact with sidewalls of the conductive pillars and upper surfaces of the conductive pillars,
We discloses a package connection structure comprising a solder joint where a solder material (Fig. 9, 914; ¶102) is on a top surface and sidewalls of a pillar. (Fig. 9, 761; ¶102)
Before the effective filing date of the invention it would have been obvious to one having ordinary skill in the art to form solder bumps around top surfaces and sidewalls of conductive pillars for making a sturdy physical and electric connection. Also, one of ordinary skill in the art would have been capable of applying this known method of enhancement to a "base" device (method, or product) in the prior art and the results would have been predictable to one of ordinary skill in the art. The Supreme Court in KSR noted that if the actual application of the technique would have been beyond the skill of one of ordinary skill in the art, then using the technique would not have been obvious. See MPEP 2143 (C) /(D)
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/LAWRENCE C TYNES JR./Examiner, Art Unit 2899
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