DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Acknowledgment is made that applicant's Amendment, filed on July 17th, 2026, has been entered.
Upon entrance of the Amendment, claims 1, 7, and 13 were amended. Claims 1-20 are currently pending.
Response to Arguments
Applicant’s arguments with respect to claims 1, 7, and 13 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 7-10, 13, 15, and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Park et al. (U.S. Patent No. 12,615,825).
Regarding to claim 7, Park teaches an integrated circuit structure, comprising:
a first vertical arrangement of horizontal nanowires (Fig. 4A, elements SP3/SP4 of CH2);
a second vertical arrangement of horizontal nanowires vertically overlapping with the first vertical arrangement of horizontal nanowires along a vertical axis (Fig. 4A, elements SP1/SP2 of CH1);
a P-type gate stack over the first vertical arrangement of horizontal nanowires, the P-type gate stack having a P-type conductive layer over a first gate dielectric (Fig. 4A, element UGE; column 7, lines 8-10; column 6, lines 59-60) comprising a first dipole material (column 9, lines 4-8); and
an N-type gate stack over the second vertical arrangement of horizontal nanowires, the N-type gate stack having an N-type conductive layer over a second gate dielectric (Fig. 4A, element LGE; column 7, lines 8-10; column 5, lines 60-62) comprising a second dipole material, wherein the second dipole material does not include the first dipole material (column 8, lines 46-48, column 9, lines 4-8).
Regarding to claim 8, Park teaches dielectric spacer vertically between and in contact with the P-type gate stack and the N-type gate stack (Fig. 4A, element DSP; column 7, lines 63-65).
Regarding to claim 9, Park teaches the first or the second dipole material comprises an oxide of La, Mg, Y, Ba or Sr (column 8, lines 45-47, lanthanum La in oxide dielectric).
Regarding to claim 10, Park teaches the first or the second dipole material comprises an oxide of Al, Ti, Nb or Ga (column 8, lines 45-47, aluminum Al in oxide dielectric).
Regarding to claim 13, Park teaches computing device, comprising:
a board (Fig. 4, element 100); and
a component coupled to the board, the component including an integrated circuit structure, comprising
first vertical arrangement of horizontal nanowires (Fig. 4A, elements SP3/SP4 of CH2);
a second vertical arrangement of horizontal nanowires vertically overlapping with the first vertical arrangement of horizontal nanowires along a vertical axis (Fig. 4A, elements SP1/SP2 of CH1);
a P-type gate stack over the first vertical arrangement of horizontal nanowires, the P-type gate stack having a P-type conductive layer over a first gate dielectric (Fig. 4A, element UGE; column 7, lines 8-10; column 6, lines 59-60) comprising a first dipole material (column 9, lines 4-8); and
an N-type gate stack over the second vertical arrangement of horizontal nanowires, the N-type gate stack having an N-type conductive layer over a second gate dielectric (Fig. 4A, element LGE; column 7, lines 8-10; column 5, lines 60-62) comprising a second dipole material, wherein the second dipole material has a greater number of layers than the first dipole material or wherein the second dipole material does not include the first dipole material (column 8, lines 46-48, column 9, lines 4-8).
Regarding to claim 15, Park teaches the second dipole material does not include the first dipole material (column 9, lines 4-8).
Regarding to claim 20, Park teaches the component is a packaged integrated circuit die (column 1, lines 20-21).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (U.S. Patent No. 12,615,825) in view of Bao et al. (U.S. Patent Application Publication No. 2023/0261074).
Regarding to claim 1, Park teaches an integrated circuit structure, comprising:
a first vertical arrangement of horizontal nanowires (Fig. 4A, elements SP3/SP4 of CH2);
a second vertical arrangement of horizontal nanowires vertically overlapping with the first vertical arrangement of horizontal nanowires along a vertical axis (Fig. 4A, elements SP1/SP2 of CH1);
a P-type gate stack over the first vertical arrangement of horizontal nanowires, the P-type gate stack having a P-type conductive layer over a first gate dielectric (Fig. 4A, element UGE; column 7, lines 8-10; column 6, lines 59-60) comprising a first dipole material (column 9, lines 4-8); and
an N-type gate stack over the second vertical arrangement of horizontal nanowires, the N-type gate stack having an N-type conductive layer over a second gate dielectric (Fig. 4A, element LGE; column 7, lines 8-10; column 5, lines 60-62) comprising a second dipole material, the second dipole material is different the first dipole material (column 8, lines 46-48).
Park does not disclose the second dipole material having a greater number of layers than the first dipole material.
Bao discloses a second dipole material having a greater number of layers than a first dipole material (Fig. 9, [0043], lines 1-5; second dipole material in stack D4 having dipole layers 130, 145, and 165, greater number of layers than first dipole material in stack D3, which having only dipole layers 145 and 165). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Park in view of Bao to configure the second dipole material having a greater number of layers than the first dipole material in order to balance threshold voltages of the NFET and the PFET stack devices.
Regarding to claim 2, Park teaches a dielectric spacer vertically between and in contact with the P-type gate stack and the N-type gate stack (Fig. 4A, element DSP).
Regarding to claim 3, Park teaches the first or the second dipole material comprises an oxide of La, Mg, Y, Ba or Sr (column 8, lines 45-47, lanthanum La in oxide dielectric).
Regarding to claim 4, Park teaches the first or the second dipole material comprises an oxide of Al, Ti, Nb or Ga (column 8, lines 45-47, aluminum Al in oxide dielectric).
Regarding to claim 5, Park generally discloses a dipole material has a thickness (Fig. 4A). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to configure a thickness of the first dipole material to be in the range of 1-3 Angstroms in order to obtain desired level of threshold voltage, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Regarding to claim 6, Park generally discloses a dipole material has a thickness (Fig. 4A). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to configure a thickness of the second dipole material to be in the range of 4-6 Angstroms in order to obtain desired level of threshold voltage, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (U.S. Patent No. 12,615,825), as applied to claim 7 above.
Regarding to claim 11, Park generally discloses a dipole material has a thickness (Fig. 4A). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to configure a thickness of the first dipole material to be in the range of 1-3 Angstroms in order to obtain desired level of threshold voltage, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Regarding to claim 12, Park generally discloses a dipole material has a thickness (Fig. 4A). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to configure a thickness of the second dipole material to be in the range of 4-6 Angstroms in order to obtain desired level of threshold voltage, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (U.S. Patent No. 12,615,825), as applied to claim 13 above, in view of Bao et al. (U.S. Patent Application Publication No. 2023/0261074).
Regarding to claim 14, Park does not disclose the second dipole material having a greater number of layers than the first dipole material.
Bao discloses a second dipole material having a greater number of layers than a first dipole material (Fig. 9, [0043], lines 1-5; second dipole material in stack D4 having dipole layers 130, 145, and 165, greater number of layers than first dipole material in stack D3, which having only dipole layers 145 and 165). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Park in view of Bao to configure the second dipole material having a greater number of layers than the first dipole material in order to balance threshold voltages of the NFET and the PFET stack devices.
Claim 16-19 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (U.S. Patent No. 12,615,825), as applied to claim 13 above, in view of Hafez et al. (U.S. Patent Application Publication No. 2021/0183857).
Regarding to claim 16, Park is silent as to an intended use of the device. Hafez discloses a camera coupled to the board (Fig. 6). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Park in view of Hafez to couple a camera to the board in order to make to device useful for more applications.
Regarding to claim 17, Park is silent as to an intended use of the device. Hafez discloses a memory coupled to the board (Fig. 6). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Park in view of Hafez to couple a memory to the board in order to make to device useful for more applications.
Regarding to claim 18, Park is silent as to an intended use of the device. Hafez discloses a communication chip coupled to the board (Fig. 6). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Park in view of Hafez to couple a communication chip to the board in order to make to device useful for more applications.
Regarding to claim 19, Park is silent as to an intended use of the device. Hafez discloses a battery coupled to the board (Fig. 6). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Park in view of Hafez to couple a battery to the board in order to make to device useful for more applications.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VU A VU whose telephone number is (571)270-7467. The examiner can normally be reached M-F: 8:00AM - 5:00PM.
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/VU A VU/Primary Examiner, Art Unit 2897
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