CTNF 18/121,720 CTNF 90499 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA Claim s 7-10, 13, and 15-20 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Hafez et al. (U.S. Patent Application Publication No. 2021/0183857) . Regarding to claim 7, Hafez teaches an integrated circuit structure, comprising: a first vertical arrangement of horizontal nanowires (Fig. 2A, elements 210p ); a second vertical arrangement of horizontal nanowires over the first vertical arrangement of horizontal nanowires (Fig. 2A, elements 210n ); a P-type gate stack over the first vertical arrangement of horizontal nanowires (Fig. 2A, element 230 in stack 272p ), the P-type gate stack having a P-type conductive layer over a first gate dielectric comprising a first dipole material (Fig. 2A, Fig. 2E, element 212 P2 , [0042], last 2 lines); and an N-type gate stack over the second vertical arrangement of horizontal nanowires (Fig. 2A, element 230 in stack 272n ), the N-type gate stack having an N-type conductive layer over a second gate dielectric comprising a second dipole material, the second dipole material does not include the first dipole material (Fig. 2A, Fig. 2E, element 212 N2 , [0042], last 2 lines). Regarding to claim 8, Hafez teaches a dielectric spacer vertically between and in contact with the P-type gate stack and the N-type gate stack (Fig. 2A, element 222 , [0033], lines 1-2). Regarding to claim 9, Hafez teaches the first or the second dipole material comprises an oxide of La, Mg, Y, Ba or Sr ([0041], last 2 lines). Regarding to claim 10, Hafez teaches the first or the second dipole material comprises an oxide of Al, Ti, Nb or Ga ([0041], last 2 lines). Regarding to claim 13, Hafez teaches computing device, comprising: a board (Fig. 6; [0071], lines 1-4); and a component coupled to the board, the component including an integrated circuit structure (Fig. 6, Fig. 2), comprising: a first vertical arrangement of horizontal nanowires (Fig. 2A, elements 210p ); a second vertical arrangement of horizontal nanowires over the first vertical arrangement of horizontal nanowires (Fig. 2A, elements 210n ); a P-type gate stack over the first vertical arrangement of horizontal nanowires (Fig. 2A, element 230 in stack 272p ), the P-type gate stack having a P-type conductive layer over a first gate dielectric comprising a first dipole material (Fig. 2A, Fig. 2E, element 212 P2 , [0042], last 2 lines); and an N-type gate stack over the second vertical arrangement of horizontal nanowires (Fig. 2A, element 230 in stack 272n ), the N-type gate stack having an N-type conductive layer over a second gate dielectric comprising a second dipole material, wherein the second dipole material has a greater number of layers than the first dipole material or wherein the second dipole material does not include the first dipole material (Fig. 2A, Fig. 2E, element 212 N2 , [0042], last 2 lines). Regarding to claim 15, Hafez teaches the second dipole material does not include the first dipole material ([0042], last 2 lines). Regarding to claim 16, Hafez teaches a camera coupled to the board (Fig. 6). Regarding to claim 17, Hafez teaches a memory coupled to the board (Fig. 6). Regarding to claim 18, Hafez teaches a communication chip coupled to the board (Fig. 6). Regarding to claim 19, Hafez teaches a battery coupled to the board (Fig. 6). Regarding to claim 20, Hafez teaches the component is a packaged integrated circuit die ([0107], lines 3-4) . 07-15-03-aia AIA Claim s 7-10, 13, 15, and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Zhang et al. (U.S. Patent No. 11,387,342) . Regarding to claim 7, Zhang teaches an integrated circuit structure, comprising: a first vertical arrangement of horizontal nanowires (Figs. 9-14, Structure A, left stack ); a second vertical arrangement of horizontal nanowires over the first vertical arrangement of horizontal nanowires (Figs. 9-14, Structure A, right stack ); a P-type gate stack over the first vertical arrangement of horizontal nanowires (column 12, lines 17-22), the P-type gate stack having a P-type conductive layer over a first gate dielectric comprising a first dipole material (Fig. 11, Structure A, left stack , element 34 , column 10, lines 33-34, dipole material aluminum oxide is used for PFET device ); and an N-type gate stack over the second vertical arrangement of horizontal nanowires (column 12, lines 17-22), the N-type gate stack having an N-type conductive layer over a second gate dielectric comprising a second dipole material (Fig. 11, Structure A, right stack , element 34 , column 10, lines 32-33, dipole material lanthanum oxide is used for PFET device ), the second dipole material does not include the first dipole material ( second dipole material lanthanum oxide, which does not include the first dipole material aluminum oxide ). Regarding to claim 8, Zhang teaches a dielectric spacer vertically between and in contact with the P-type gate stack and the N-type gate stack (Fig. 14, column 12, lines 29-32). Regarding to claim 9, Zhang teaches the first or the second dipole material comprises an oxide of La, Mg, Y, Ba or Sr (column 10, lines 33-34). Regarding to claim 10, Zhang teaches the first or the second dipole material comprises an oxide of Al, Ti, Nb or Ga (column 10, lines 32-33). Regarding to claim 13, Zhang teaches computing device (column 1, lines 10-13), comprising: a board (column 4, lines 21-22); and a component coupled to the board, the component including an integrated circuit structure (Fig. 9-14), comprising: a first vertical arrangement of horizontal nanowires (Figs. 9-14, Structure A, left stack ); a second vertical arrangement of horizontal nanowires over the first vertical arrangement of horizontal nanowires (Figs. 9-14, Structure A, right stack ); a P-type gate stack over the first vertical arrangement of horizontal nanowires (column 12, lines 17-22), the P-type gate stack having a P-type conductive layer over a first gate dielectric comprising a first dipole material (Fig. 11, Structure A, left stack , element 34 , column 10, lines 33-34, dipole material aluminum oxide is used for PFET device ); and an N-type gate stack over the second vertical arrangement of horizontal nanowires (column 12, lines 17-22), the N-type gate stack having an N-type conductive layer over a second gate dielectric comprising a second dipole material (Fig. 11, Structure A, right stack , element 34 , column 10, lines 32-33, dipole material lanthanum oxide is used for PFET device ), wherein the second dipole material has a greater number of layers than the first dipole material or wherein the second dipole material does not include the first dipole material ( second dipole material lanthanum oxide which does not include the first dipole material aluminum oxide ). Regarding to claim 15, Zhang teaches the second dipole material does not include the first dipole material ( second dipole material lanthanum oxide which does not include the first dipole material aluminum oxide ). Regarding to claim 20, Zhang teaches the component is a packaged integrated circuit die (column 1, lines 10-13) . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 1-6 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (U.S. Patent No. 11,387,342) in view of Bao et al. (U.S. Patent Application Publication No. 2023/0261074) . Regarding to claim 1, Zhang teaches an integrated circuit structure, comprising: a first vertical arrangement of horizontal nanowires (Figs. 9-14, Structure A, left stack ); a second vertical arrangement of horizontal nanowires over the first vertical arrangement of horizontal nanowires (Figs. 9-14, Structure A, right stack ); a P-type gate stack over the first vertical arrangement of horizontal nanowires (column 12, lines 17-22), the P-type gate stack having a P-type conductive layer over a first gate dielectric comprising a first dipole material (Fig. 11, Structure A, left stack , element 34 , column 10, lines 38-43); and an N-type gate stack over the second vertical arrangement of horizontal nanowires (column 12, lines 17-22), the N-type gate stack having an N-type conductive layer over a second gate dielectric comprising a second dipole material (Fig. 11, Structure A, right stack , element 34 , column 10, lines 45-47). Zhang does not disclose the second dipole material having a greater number of layers than the first dipole material. Bao discloses a second dipole material having a greater number of layers than a first dipole material (Fig. 9, [0043], lines 1-5; second dipole material in stack D4 having dipole layers 130 , 145 , and 165 , greater number of layers than first dipole material in stack D3 , which having only dipole layers 145 and 165 ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Zhang in view of Bao to configure the second dipole material having a greater number of layers than the first dipole material in order to balance threshold voltages of the NFET and the PFET stack devices. Regarding to claim 2, Zhang teaches a dielectric spacer vertically between and in contact with the P-type gate stack and the N-type gate stack (Fig. 14, column 12, lines 29-32). Regarding to claim 3, Zhang teaches the first or the second dipole material comprises an oxide of La, Mg, Y, Ba or Sr (column 10, lines 32-33). Regarding to claim 4, Zhang teaches the first or the second dipole material comprises an oxide of Al, Ti, Nb or Ga (column 10, lines 33-34). Regarding to claim 5, Bao generally discloses a dipole material has a thickness in the range of 1-20 Angstroms ([0042], lines 11-12). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to configure a thickness of the first dipole material to be in the range of 1-3 Angstroms in order to obtain desired level of threshold voltage, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955) . Regarding to claim 6, Bao generally discloses a dipole material has a thickness in the range of 1-20 Angstroms ([0042], lines 11-12). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to configure a thickness of the second dipole material to be in the range of 4-6 Angstroms in order to obtain desired level of threshold voltage, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955) . Regarding to claim 13, Zhang teaches computing device (column 1, lines 10-13), comprising: a board (column 4, lines 21-22); and a component coupled to the board, the component including an integrated circuit structure (Fig. 9-14), comprising: a first vertical arrangement of horizontal nanowires (Figs. 9-14, Structure A, left stack ); a second vertical arrangement of horizontal nanowires over the first vertical arrangement of horizontal nanowires (Figs. 9-14, Structure A, right stack ); a P-type gate stack over the first vertical arrangement of horizontal nanowires (column 12, lines 17-22), the P-type gate stack having a P-type conductive layer over a first gate dielectric comprising a first dipole material (Fig. 11, Structure A, left stack , element 34 , column 10, lines 33-34, dipole material aluminum oxide is used for PFET device ); and an N-type gate stack over the second vertical arrangement of horizontal nanowires (column 12, lines 17-22), the N-type gate stack having an N-type conductive layer over a second gate dielectric comprising a second dipole material (Fig. 11, Structure A, right stack , element 34 , column 10, lines 32-33, dipole material lanthanum oxide is used for PFET device ), the second dipole material does not include the first dipole material ( second dipole material lanthanum oxide which does not include the first dipole material aluminum oxide ). Zhang does not disclose the second dipole material having a greater number of layers than the first dipole material. Bao discloses a second dipole material having a greater number of layers than a first dipole material (Fig. 9, [0043], lines 1-5; second dipole material in stack D4 having dipole layers 130 , 145 , and 165 , greater number of layers than first dipole material in stack D3 , which having only dipole layers 145 and 165 ). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Zhang in view of Bao to configure the second dipole material having a greater number of layers than the first dipole material in order to balance threshold voltages of the NFET and the PFET stack devices. Regarding to claim 14, Zhang as modified discloses the second dipole material has a greater number of layers than the first dipole material (Bao, Fig. 9) . 07-21-aia AIA Claim s 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (U.S. Patent No. 11,387,342), as applied to claim 7 above . Regarding to claim 11, Zhang discloses the first dipole material has a thickness (Fig. 9). Zhang is silent about a range of thickness, however, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to configure a thickness of the first dipole material to be in the range of 1-3 Angstroms in order to obtain desired level of threshold voltage, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955) . Regarding to claim 12, Zhang discloses the second dipole material has a thickness (Fig. 9). Zhang is silent about a range of thickness, however, it would have been obvious to one having ordinary skill in the art at the time the invention was filed to configure a thickness of the second dipole material to be in the range of 4-6 Angstroms in order to obtain desired level of threshold voltage, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233 (CCPA 1955) . Pertinent Art For the benefits of the Applicant, US-10381490-B2, US-10770353-B2, US-11152264-B2, and US-11329136-B2, are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. These references do not disclose “the second dipole material having a greater number of layers than the first dipole material or the second dipole material has a greater number of layers than the first dipole material.” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VU A VU whose telephone number is (571)270-7467. The examiner can normally be reached M-F: 8:00AM - 5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD M DICKE can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VU A VU/Primary Examiner, Art Unit 2897 Application/Control Number: 18/121,720 Page 2 Art Unit: 2897 Application/Control Number: 18/121,720 Page 3 Art Unit: 2897 Application/Control Number: 18/121,720 Page 4 Art Unit: 2897 Application/Control Number: 18/121,720 Page 6 Art Unit: 2897 Application/Control Number: 18/121,720 Page 7 Art Unit: 2897 Application/Control Number: 18/121,720 Page 8 Art Unit: 2897 Application/Control Number: 18/121,720 Page 9 Art Unit: 2897 Application/Control Number: 18/121,720 Page 10 Art Unit: 2897 Application/Control Number: 18/121,720 Page 11 Art Unit: 2897 Application/Control Number: 18/121,720 Page 12 Art Unit: 2897
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