DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 3-5 is/are rejected under 35 U.S.C. 102(A1) as being anticipated by Chen et al. (US 2019/0043795 A1).
Regarding Claim 1, Chen (Fig. 1-3) discloses a resistive memory device comprising:
a lower electrode (106) having a flat upper surface (top of 106);
a resistance change layer (110) formed on the lower electrode (106); and
an upper electrode (120) formed on the resistance change layer (110), wherein
the upper surface of the lower electrode (top of 106) is wider than a lower surface of the lower electrode (bottom of 106),
therein the lower electrode comprises an upper portion (portion of 106 in 204u) and a lower portion (portion of 106 in 104l), wherein
the lower portion of the electrode (portion of 106 in 104l), which comprises the lower surface of the lower electrode (bottom of 106), has a width that does not increase towards an upper direction (See Fig. 1 and 2A), and
the upper portion of the lower electrode (portion of 106 in 204u), which comprises the upper surface of the lower electrode (top of 106), has an inclined side surface so that a width of the upper portion of the lower electrode is increased upwardly (See Fig. 1 and 2A).
Regarding Claim 3, Chen discloses the resistive memory device of claim 1, further comprising
a conductive layer (112) formed on the resistance change layer (110), wherein the upper electrode (120) is formed on the conductive layer (112).
Regarding Claim 4, Chen discloses the resistive memory device of claim 1, further comprising:
a transistor (306) [0035] formed on a substrate (310);
a first insulating layer (202) formed on the substrate (310) and the transistor (306);
a first contact plug (114b) electrically connected to the transistor (306) through the first insulating layer (202); and
a second insulating layer (BEVA dielectric layer 204,) formed on the first insulating layer (202) and the first contact plug (114b) and having an opening (opening for 106) exposing a portion of an upper surface of the first contact plug (114b), wherein
the lower electrode (106) is formed in the opening (opening for 106).
Regarding Claim 5, Chen discloses the resistive memory device of claim 4, wherein
the opening (opening for 106) has an inclined inner side surface (see side surface of opening for 106 in 104u) so that a width is increased upwardly. (See Fig.1, 2B)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2019/0043795 A1) in view of Murase et al. (US 2015/0364681 A1) and as evidenced by Feustel et al. (US 2010/0164121 A1).
Regarding Claim 6, Chen discloses the resistive memory device of claim 4, wherein
the first insulating layer (202) has a first contact hole (contact hole for 114), a first diffusion barrier layer (114l) are formed on a bottom surface and an inner side surface of the first contact hole (contact hole for 114), and the first contact plug (114b) is formed on the first diffusion barrier layer (114l) to fill the first contact hole (contact hole for 114) (See Fig. 1, 2B).
Chen does not explicitly disclose a first adhesive layer.
However, Murase discloses a first insulating layer (101) has a first contact hole (contact hole for 3), a first adhesive layer (Ta) and a first diffusion barrier layer (TaN) (the first barrier metal layer 102 has a laminated structure composed of a tantalum nitride film (thickness: 5 to 40 nm) and a tantalum film (thickness: 5 to 40 nm” [0137]) are formed on a bottom surface and an inner side surface of the first contact hole (See Fig. 6 of Murase).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the resistive memory device in Chen in view of Murase such that a first adhesive layer and a first diffusion barrier layer are formed on a bottom surface and an inner side surface of the first contact hole in order to meet the requirements in terms of diffusion suppressing and adhesion properties.
The Examiner notes that adhesion layers as part of diffusion barrier multilayers in interconnect wirings are well known in the art and provides evidentiary reference of Feustel et al. (US 2010/0164121 A1) (“Currently, tantalum, titanium, tungsten and their compounds with nitrogen and silicon and the like are preferred candidates for a conductive barrier layer, wherein the barrier layer may comprise two or more sub-layers of different composition so as to meet the requirements in terms of diffusion suppressing and adhesion properties. [0005].
Regarding Claim 7, Chen in view of Murase discloses the resistive memory device of claim 6, wherein the resistance change layer (110) (a variable resistance layer 108; Murase) is electrically insulated (a first diffusion-preventing layer 104 in Murase is SiN-an insulator) from the first adhesive layer (Ta; Murase) by the second insulating layer (204). (a first diffusion-preventing layer 104, SiN; Murase)
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2019/0043795 A1) in view of Tada et al. (US 2011/0272664 A1).
Regarding Claim 8, Chen discloses the resistive memory device of claim 1, further comprising:
a third insulating layer (214) formed on the upper electrode (120);
a second contact plug (118b) electrically connected to the upper electrode (120) through the third insulating layer (214); and
Chen does not explicitly disclose a metal wiring pattern formed on the third insulating layer and the second contact plug.
Tada (Fig. 15, 16) discloses a metal wiring pattern (See 41,47 wiring layers above variable resistance element 22) formed on a third insulating layer (34) and a second contact plug (18).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the resistive memory device in Chen in view of Tada such that a metal wiring pattern formed on the third insulating layer and the second contact plug in order to have FPGA comprising a variable resistance element in a multilevel wiring layer structure on a semiconductor substrate [0075-0076, 0211]
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2019/0043795 A1) in view of Tada et al. (US 2011/0272664 A1) and as evidenced by Feustel et al. (US 2010/0164121 A1).
Regarding Claim 9, Chen in view of Tada discloses the resistive memory device of claim 8, wherein
the third insulating layer (214) has a second contact hole (hole for top 118 above 120), and a second diffusion barrier layer (118l above 120) are formed on a bottom surface and an inner side surface of the second contact hole (hole for top 118), and the second contact plug (118b) is formed on the second diffusion barrier layer (118l) to fill the second contact hole (hole for top 118) (See Fig. 2)
As previously combined Chen in view of Tada does not explicitly disclose a second adhesive layer.
However, Tada discloses a multilayer barrier layer having adhesive layer (Ta; Ti) and diffusion layer (TaN;TiN) (“Ta/TaN multilayer (laminate) body can be used for each of the barrier metals (6, 20, 36, 42, 48, 54, and 60). A Ti/TiN multilayer (laminate) body can be used for the barrier metals 65 and 66.”) [0207].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the resistive memory device in Chen in view of Tada such that a second adhesive layer is formed on a bottom surface and an inner side surface of the second contact hole in order to meet the requirements in terms of diffusion suppressing and adhesion properties.
The Examiner notes that adhesion layers as part of diffusion barrier multilayers in interconnect wirings are well known in the art and provides evidentiary reference of Feustel et al. (US 2010/0164121 A1) (“Currently, tantalum, titanium, tungsten and their compounds with nitrogen and silicon and the like are preferred candidates for a conductive barrier layer, wherein the barrier layer may comprise two or more sub-layers of different composition so as to meet the requirements in terms of diffusion suppressing and adhesion properties. [0005]
Response to Arguments
Applicant’s arguments, see pages 9 and 10, filed08/21/2025, with respect to the rejection(s) of claim(s) 1 under 35 U.S.C. 102(A1) as being anticipated by Narayanan et al. (US 2015/0318333 A1) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of 35 U.S.C. 102(A1) as being anticipated by Chen et al. (US 2019/0043795 A1).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DMITRIY YEMELYANOV whose telephone number is (571)270-7920. The examiner can normally be reached M-F 9a.m.-6p.m.
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/DMITRIY YEMELYANOV/Examiner, Art Unit 2891
/MATTHEW C LANDAU/Supervisory Patent Examiner, Art Unit 2891