Prosecution Insights
Last updated: May 29, 2026
Application No. 18/122,339

ELECTRONIC CIRCUIT PACKAGES

Non-Final OA §102§103
Filed
Mar 16, 2023
Priority
Sep 07, 2022 — provisional 63/404,280
Examiner
DINH, TUAN T
Art Unit
2848
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Apple Inc.
OA Round
2 (Non-Final)
79%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allowance Rate
925 granted / 1174 resolved
+10.8% vs TC avg
Strong +23% interview lift
Without
With
+22.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
24 currently pending
Career history
1209
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
64.6%
+24.6% vs TC avg
§102
17.9%
-22.1% vs TC avg
§112
2.0%
-38.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1174 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-11, and 13-16 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Nomura et al. (U.S. Patent 11,076,484), hereafter Nomura. As to claim 1, Nomura discloses a structure (100) as shown in figures 1-6 and 21-22, comprising: a substrate (10) with first and second regions, wherein the first region is configured to bend (at the groove C3 or T1); a conductive line (3, 4) disposed on the second region; an electronic component (20, 30) disposed on the conductive line; and a molding compound layer (40) disposed on the second region and surrounding the electronic component (20, 30), wherein a modulus of the molding compound layer (the element 40 is made from silica having modulus about 70-73 GPa) is greater than a modulus of the substrate (the substrate 10 having insulator layer 1 made from glass fiber and epoxy resin in a range of 17.8-30 GPa), and wherein the molding compound layer (40) is configured to prevent the second region from bending. As to claims 2-3, Nomura further comprising an underfill layer or molding compound (40) disposed between the electronic component (20, 30) and a top surface of the second region. As to claims 4-5, Nomura discloses in figure 22A that the molding compound layer (40) extends over or substantially coplanar a top surface of the electronic component. As to claim 6, Nomura discloses the molding compound layer (40) comprises a substantially linear top surface profile and a substantially linear sidewall profile. As to claim 7, Nomura discloses the molding compound layer (40) comprises a modulus greater than about 15 GPa, (the element 40 is made from silica having modulus about 70-73 GPa). As to claim 8, Nomura discloses the molding compound layer (40) is non-conformal to surfaces of the electronic component. As to claim 9, Nomura further comprising solder bonding structures (B2) disposed between the electronic component (20, 30) and the second region, wherein the molding compound layer (40) surrounds the solder bonding structures. As to claim 10, Nomura further comprising a metal layer (50) disposed substantially conformally on the molding compound layer (40). As to claim 11, Nomura discloses a structure (100) as shown in figures 13-15 and 21-22, comprising: a substrate (10) with first and second regions, wherein the first region is configured to bend; a first conductive line (3, 4) disposed on a first surface of the second region; a second conductive line (5, 6) disposed on a second surface of the second region, wherein the first and second surfaces are opposite to each other; a first electronic component (20, 30) disposed on the first conductive line; a second electronic component (70) disposed on the second conductive line; a first molding compound layer (40) disposed on the first surface of the second region and surrounding the first electronic component; and a second molding compound layer (90) disposed on the second surface of the second region and surrounding the second electronic component (70), wherein a first modulus of the first molding compound layer (40) is greater than a modulus of the substrate (10) and a second modulus of the second molding compound layer (90) is greater than the modulus of the substrate (10), the modulus of both elements 40, 90 are made from silica approximately about 70-73 GPa, and the substrate 10 having insulator layer 1 made from glass fiber and epoxy resin in a range of 17.8-30 GPa). As to claim 13, Nomura discloses a portion of the first molding compound layer (40) is disposed between the first electronic component (20, 30) and the first surface of the second region; and wherein a portion of the second molding compound layer (90) is disposed between the second electronic component (70) and the second surface of the second region. As to claim 14, Nomura further comprising an underfill layer (40) disposed between the first electronic component (20, 30) and the first surface of the second region. As to claim 15, Nomura discloses a surface of the first molding compound layer (40) is substantially coplanar with a surface of the first electronic component (20, 30); and wherein a surface of the second molding compound layer (90) is substantially coplanar with a surface of the second electronic component (70), figure 14. As to claim 16, Nomura discloses the first and second molding compound layers (40, 90) each comprises a modulus greater than about 15 GPa, (the element 40 is made from silica having modulus about 70-73 GPa). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 12, and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nomura et al. (U.S. Patent 11,076,484) in view of Yang et al. (2018/0269181). Regarding claim 12, Nomura discloses all of the limitations of claimed invention except for a portion of the first molding compound layer overlaps with a second portion of the second molding compound layer. Yang teaches the system-in package (326) as shown in figure 14 comprising a portion of the first molding compound layer (282) overlaps with a second portion of the second molding compound layer (280). It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Yang employed in the electronic package of Nomura in order to provide excellent in size, less power, and higher performance structures. As to claim 17, Nomura discloses a method for forming an electronic package (100) as shown in figures 1-6 and 21-22, comprising: forming a conductive line (3, 4, figure 2) on a first surface (the top surface) of a [[flexible]] substrate (1); mounting a rigid substrate (base member 205 or BL) on a second surface (the bas BL formed on the bottom surface of the substrate 1 or 210) of the substrate, wherein the first and second surfaces are opposite to each other; bonding an electronic component (20, 30 or 220) on the conductive line (3, 4); forming a molding compound layer (40 or 240) surrounding the electronic component (20, 30 or 220); and removing (peel of or detached, column 1, line 39+) the rigid substrate (BL) after forming the molding compound layer, see figures 4B or 22). Nomura does not specifically disclose the substrate (1) being flexible. Yang teaches a system-in-package with double side molding as shown in figure 3 comprising a flexible substrate (170 having flexible insulation layer 172, para-0036+). It would have been obvious to one having ordinary skill in the art before the effective filling date to have a teaching of Yang employed in the electronic package of Nomura in order to provide flexible electronic packaging structure. As to claim 18, Nomura as modified by Yang discloses forming the molding compound layer (40 or 240, the silica material having a modulus approximately 70-73 GPA) comprises depositing a molding compound with a modulus greater than about 15 GPa on the electronic component. As to claim 19, Nomura as modified by Yang further comprising performing a planarization process on the molding compound layer (see figure 22) to co-planarize a surface of the molding compound layer with a surface of the electronic component. As to claim 18, Nomura as modified by Yang further comprising depositing a metal layer (50 or 250) on the molding compound layer (40, 240). Response to Arguments Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN T DINH whose telephone number is (571)272-1929. The examiner can normally be reached MON-FRI: 8AM-4:30PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TUAN T DINH/Primary Examiner, Art Unit 2848
Read full office action

Prosecution Timeline

Mar 16, 2023
Application Filed
Sep 10, 2024
Response after Non-Final Action
Nov 18, 2024
Response after Non-Final Action
May 02, 2025
Non-Final Rejection mailed — §102, §103
Sep 11, 2025
Applicant Interview (Telephonic)
Sep 12, 2025
Examiner Interview Summary
Oct 23, 2025
Response Filed
Mar 11, 2026
Non-Final Rejection mailed — §102, §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
79%
Grant Probability
99%
With Interview (+22.9%)
2y 11m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1174 resolved cases by this examiner. Grant probability derived from career allowance rate.

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