DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/12/2026 has been entered.
Claims 1-20 are pending and have been examined.
Response to Amendments
Applicant's response of 01/16/2026 has been acknowledged. Claims 1 and 11 have been amended. Claims 3 and 14 were previously canceled. No new matter has been added.
This office action considers claims 1-2, 4-13 and 15-20 pending for prosecution and are examined on their merits.
Response to Arguments
Applicant's arguments of 01/16/2026 with respect to the rejections of claims have
been fully considered, and are persuasive. Therefore, the rejection of claims 1-2, 4-13 and 15-20 have been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Choi et al. (US 20190165060 A1 – hereinafter Choi).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all
obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claims 1, 2, 4, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 20190165060 A1 – hereinafter Choi) in view of Nishiyama et al. (US 20140151709 A1 – hereinafter Nishiyama), Choi et al. (US 20130161656 A1 – hereinafter Choi-656) and Lin et al. (US 20170294488 A1 – hereinafter Lin).
Regarding independent claim 1, Choi teaches
(Currently Amended) A display apparatus (100 – Fig. 1 – [0042] –
“foldable display device 100”) comprising:
a substrate (101 – Fig. 2A – [0053] – “substrate 101 including pixel circuit
areas, line areas arranged between the pixel circuit areas, and non-line areas which are arranged between the line areas and in which no line or transistor is arranged;
a pixel circuit (PC – fig 4) (choi (Fig. 2A annotated, see below – [0040] – “In the organic light emitting display panel 110, an organic light emitting element for displaying an image, a circuit for driving the organic light emitting element, lines, and other components may be disposed” – hereinafter ‘PC’) arranged in the pixel circuit areas (Fig. 2A annotated, see below – hereinafter ‘PCA’) and comprising at least one thin film transistor (120 – Fig. 2A – [0084] – “thin film transistor 120”);
a plurality of lines ([0040] – “In the organic light emitting display panel 110, an organic light emitting element for displaying an image, a circuit for driving the organic light emitting element, lines, and other components may be disposed” – this describes a plurality of lines in the pixel circuit) arranged in the pixel circuit areas (PCA) and the line areas (WA); and
a display element (130 – Fig. 2A – [0052] – “an organic light emitting element 130”) including a pixel electrode (131 – Fig. 2A – [0063] – “organic light emitting element 130 includes the anode electrode 131”) connected to the pixel circuit (PC),
wherein in a plan view an area of the pixel electrode is greater than an area in which the pixel circuit is arranged,
wherein the display element overlaps the pixel circuit in the plan view,
wherein an area of one of the non-line areas is about 10 percentages (%) to 25 % of an area of one of the pixel circuit areas in a plan view.
Choi does not expressly disclose the other limitations of claim 1.
However, in an analogous art, Nishiyama teaches
wherein in a plan view an area of the pixel electrode (14a – Fig. 6 – [0050] – “pixel electrodes 14a and 14b”) is greater than an area in which the pixel circuit is arranged ([0042] – “area of each of the pixel electrodes may be an integer multiple of an area of each of the pixel circuits, the integer being equal to or greater than two”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the pixel electrode area as taught by Nishiyama into Choi.
An ordinary artisan would have been motivated to use the known technique of Nishiyama in the manner set forth above to produce the predictable result of a [0009] – “display panel pertaining to one aspect of the present invention can be manufactured in the above-mentioned manufacturing process, reduction in manufacturing yield can be suppressed.”
Choi and Nishiyama do not expressly disclose the other limitations of claim 1.
However, in an analogous art, Choi-656 teaches
wherein the display element (PA – Fig. 3 – [0047] – “light emission areas PA” – this corresponds to a display element) overlaps the pixel circuit (PC – Fig. 3 – [0114] – “first electrode 221 that is electrically connected to the pixel circuit portion PC is included in the light emission area PA, and the pixel circuit portion PC overlaps with the first electrode 221”) in the plan view (Fig. 3 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the display element area as taught by Choi-656 into Choi and Nishiyama.
An ordinary artisan would have been motivated to use the known technique of Choi-656 in the manner set forth above to produce the predictable result of [0009] – “display panel pertaining to one aspect of the present invention can be manufactured in the above-mentioned manufacturing process, reduction in manufacturing yield can be suppressed.”
Choi, Nishiyama, and Choi-656 do not expressly disclose the other limitations of claim 1.
However, in an analogous art, Lin teaches
pixel circuit areas (911, 921, 931 – Fig. 9A – {[0105] – “the control of OLED
stacks 911, 921 and 931”}, {[0053] – “The electrodes 265 and 267 may be configured to implement either an active matrix (with additional pixel-level circuitry not shown in this example) or a passive matrix control methodology of the respective OLEDs 257” – OLED stacks are considered pixel circuits, hereinafter ‘PCA’), line areas (Fig. 9A annotated, see below – {V29 and V49 - Fig. 9A – [0106] – “two column electrodes such as V29 and V49”}, {783-786 – Fig. 7 – [0092] – “row electrode 783 or 785 and column electrode 784 or 786 to form a passive matrix array”} – these are considered line areas, hereinafter ‘WA’) arranged between the pixel circuit areas (PCA), and non-line areas (Fig. 9A annotated, see below – 721-724 – Fig. 7 – [0092] – “The display pixels 711-714 also include transparent areas 721-724. It should be noted that, in the illustrated example, the transparent areas 721-724 surround the respective stacked RGB emitter 775-778. Each stacked RGB emitter 775-778 in respective display pixels 711-714 is interconnected with a row electrode, such as row electrode 783 or 785 and column electrode 784 or 786 to form a passive matrix array” – this describes an area free of wires or pixel circuit components, hereinafter ‘NWA’) which are arranged between the line areas (WA) and in which no line or transistor ([0067] – “Active matrix (AM) OLEDs include transistors” – Fig. 4A shows this) is arranged;
wherein an area of one of the non-line areas (NWA) is about 10 percentages (%) to 25 % of an area ([0061] – “the ratio of area occupied by the OLED stack 375 to transparent area 379 remains at approximately 20% to 80%” – the describes the transparent (non-line) area is approximately 20% of the OLED stack (pixel circuit) area) of one of the pixel circuit areas (911, 921, 931 – Fig. 9A – {[0105] – “the control of OLED stacks 911, 921 and 931”}, {[0053] – “The electrodes 265 and 267 may be configured to implement either an active matrix (with additional pixel-level circuitry not shown in this example) or a passive matrix control methodology of the respective OLEDs 257” – OLED stacks are considered pixel circuits) in a plan view (Fig. 9A shows this).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the pixel circuit area with line and non-line areas as taught by Lin into Choi, Nishiyama, and Choi-656.
An ordinary artisan would have been motivated to use the known technique of Lin in the manner set forth above to produce the predictable result [0010] – “to improve upon the transmissivity of transparent OLED display devices for various applications, including for use as (or as part of) a lighting device.”
Regarding claim 2, Choi, as modified by Nishiyama, Choi-656, and Lin, teaches claim 1 from which claim 2 depends. Choi, Nishiyama, and Choi-656 do not expressly disclose the limitations of claim 2.
However, in an analogous art, Lin teaches
(Original) The display apparatus of claim 1, wherein the pixel circuit areas
(OLED – [0067] – “Active matrix (AM) OLEDs include transistors, interconnections and capacitors” – this is a pixel circuit area) and the line areas (WA) are alternately arranged in a first direction (Fig. 9A annotated, see above – hereinafter ‘x’) and a second direction (Fig. 9A annotated, see above – hereinafter ‘y’) intersecting with the first direction (x – Fig. 9A annotated shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the pixel circuit area with line and non-line areas as taught by Lin into Choi, Nishiyama, and Choi-656.
An ordinary artisan would have been motivated to use the known technique of Lin in the manner set forth above to produce the predictable result as stated above in claim 1.
Regarding claim 4, Choi, as modified by Nishiyama, Choi-656, and Lin, teaches claim 1 from which claim 4 depends. Choi further teaches
(Original) The display apparatus of claim 1, wherein the display
apparatus (100 – Fig. 1 – [0042] – “foldable display device 100”) includes a folding area (FA – Fig. 1 – [0041] – “folding area FA) and a non-folding area (NFA – Fig. 1 – [0041] – “non-folding area NFA), and in the plan view, an area of one of the pixel circuit areas (Fig. 2A annotated, see below – hereinafter ‘PCA’) in the folding area (FA) is the same as an area of one of the pixel circuit areas (PCA) in the non-folding area (NFA – Fig. 2 shows the PCA in FA the same size as in NFA).
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Regarding claim 12, Choi, as modified by Nishiyama, Choi-656, and Lin, teaches claim 11 from which claim 12 depends. Choi, Choi-656, and Lin do not expressly disclose the limitations of claim 12.
However, in an analogous art, Nishiyama teaches
(Original) The display apparatus of claim 11, wherein in a plan view an area of the pixel electrode (14a – Fig. 6 – [0050] – “pixel electrodes 14a and 14b”) is greater than an area in which the pixel circuit is arranged ([0042] – “area of each of the pixel electrodes may be an integer multiple of an area of each of the pixel circuits, the integer being equal to or greater than two”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the pixel electrode area as taught by Nishiyama into Choi, Choi-656, and Lin.
An ordinary artisan would have been motivated to use the known technique of Nishiyama in the manner set forth above to produce the predictable result as stated above in claim 1.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Nishiyama, Choi-656, Lin, and Huang et al. (US 20240379062 A1 – hereinafter Huang).
Regarding claim 5, Choi, as modified by Nishiyama, Choi-656, and Lin, teaches claim 1 from which claim 5 depends. Choi, Nishiyama, Choi-656, and Lin do not expressly disclose the limitations of claim 5.
However, in an analogous art, Huang teaches
(Original) The display apparatus of claim 1, wherein each of the pixel circuit areas (310 – Fig. 3 – [0134] – “circuit area 310 includes a third gate driving circuit (not shown in the figure), a second gate driving circuit GOA2 and a first gate driving circuit GOA1” – this is a pixel circuit area) includes two pixel circuits (GOA1 and Goa2 – Fig. 3 – [0134] – “second gate driving circuit GOA2 and a first gate driving circuit GOA1” – these are pixel circuits).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the two pixel circuit structure as taught by Huang into Choi, Nishiyama, Choi-656, and Lin.
An ordinary artisan would have been motivated to use the known technique of Huang in the manner set forth above to produce the predictable result of [0003] – “active light emitting display devices and have advantages such as self-luminescence, wide viewing angle, high contrast ratio, low power consumption, very high response speed, lightness and thinness, flexibility, and low costs.”
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Nishiyama, Choi-656, Lin, and Yoon et al. (US 20180047802 A1 – hereinafter Yoon).
Regarding claim 6, Choi, as modified by Nishiyama, Choi-656, and Lin, teaches claim 1 from which claim 6 depends. Choi, Nishiyama, Choi-656, and Lin do not expressly disclose the limitations of claim 6.
However, in an analogous art, Yoon teaches
(Original) The display apparatus of claim 1, further comprising an inorganic insulating layer (125 – Fig. 3 –[0084] – “inorganic insulating layer 125 may include a groove GR corresponding to the bending area BA as illustrated in FIG. 3”) defining a groove (GR – Fig. 3 – [0084] – “inorganic insulating layer 125 may include a groove GR corresponding to the bending area BA as illustrated in FIG. 3”) therein in the line areas ([0007] – “wiring unit extending to the second area through the bending area, the wiring unit arranged on the inorganic insulating layer and at least a portion thereof overlapping the opening or the groove”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the inorganic insulating layer and groove structure as taught by Yoon into Choi, Nishiyama, Choi-656, and Lin.
An ordinary artisan would have been motivated to use the known technique of Yoon in the manner set forth above to produce the predictable result [0004] – “to reduce
defects that may occur during manufacturing of the above-described bent display apparatus and also to reduce manufacturing costs.”
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Nishiyama, Choi-656, Lin, and Park et al. (US 20200381507 A1 – hereinafter Park).
Regarding claim 7, Choi, as modified by Nishiyama, Choi-656, and Lin, teaches claim 1 from which claim 7 depends. Choi, Nishiyama, Choi-656, and Lin do not expressly disclose the limitations of claim 7.
However, in an analogous art, Park teaches
(Original) The display apparatus of claim 1, wherein the pixel electrode (191c – Fig. 3 – [0111] – “pixel electrode 191c”) at least partially overlaps the line areas (171a, 171b, 171c – Fig. 3 – [0078] – “plurality of data lines 171a, 171b, and 171c” – this is a line area) in the plan view.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the pixel electrode structure as taught by Park into Choi, Nishiyama, Choi-656, and Lin.
An ordinary artisan would have been motivated to use the known technique of Park in the manner set forth above to produce the predictable result of [0029] – “a capacitance of a parasitic capacitor between the pixel electrode and the data line of the plurality of pixels of the display device may be reduced or a deviation may be reduced, thereby improving display quality.”
Claims 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Nishiyama, Choi-656, Lin, and Zhang et al. (US 20220123074 A1 – hereinafter Zhang).
Regarding claim 8, Choi, as modified by Nishiyama, Choi-656, and Lin, teaches claim 1 from which claim 8 depends. Choi, Nishiyama, Choi-656, and Lin do not expressly disclose the limitations of claim 8.
However, in an analogous art, Zhang teaches
(Original) The display apparatus of claim 1, wherein the plurality of lines ([0016] – “a plurality of pixel driving circuits, wherein the plurality of pixel driving circuits and the plurality of anodes are disposed in a one-one-to correspondence manner, each of the plurality of anodes is electrically connected to a corresponding one of the plurality of pixel driving circuit” – this infers a plurality of lines as they are necessary to connect the drive circuits) comprises a first line (131 – Fig. 8B – [0132] – “reset signal line 131 extending along the first direction”) extending in a first direction (First Direction – Fig. 8B – [0132] – “reset signal line 131 extending along the first direction”) and a second line (152 – Fig. 8D – [0135] – “first conductive layer 150 (that is, the first source-drain metal layer) includes a power wire 151, a data line 152”) extending in a second direction (Second Direction – Fig. 8D shows this”) intersecting with the first direction, the first line (131) is arranged in a same layer as a gate electrode (130 – Fig. 8B – [0113] – “first gate electrode layer 130” – Fig. 8B shows this) of the thin film transistor ([0025] – “gate electrode of a drive thin film transistor” – although not shown, it is specified that it exists in the device), and the second line (152) is arranged in a different layer from the first line (131).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the first and second line structure as taught by Zhang into Choi, Nishiyama, Choi-656, and Lin.
An ordinary artisan would have been motivated to use the known technique of Zhang in the manner set forth above to produce the predictable result of [0005] – “the display substrate can prevent an opening edge of a fine metal mask (FMM) from coming into contact with the spacer, and prevent the generation of foreign bodies such as particles, thereby improving the yield of the display substrate.”
Regarding claim 9, Choi, as modified by Nishiyama, Choi-656, and Lin, teaches claim 8 from which claim 9 depends. Choi, Nishiyama, Choi-656, and Lin do not expressly disclose the limitations of claim 9.
However, in an analogous art, Zhang teaches
(Original) The display apparatus of claim 8, wherein the second line (152) is arranged farther from an upper surface of the substrate (110 – Fig. 18A – [0090] – “base substrate 110”) than the first line (131) in a thickness direction (Fig. 18A annotated, shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the first and second line structure as taught by Zhang into Choi, Nishiyama, Choi-656, and Lin.
An ordinary artisan would have been motivated to use the known technique of Zhang in the manner set forth above to produce the predictable result as stated above in claim 8.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Nishiyama, Choi-656, Lin, Zhang, and Park.
Regarding claim 10, Choi, as modified by Nishiyama, Choi-656, and Lin, and Zhang, teaches claim 8 from which claim 10 depends. Choi, Nishiyama, Choi-656, and Lin and Zhang do not expressly disclose the limitations of claim 10.
However, in an analogous art, Park teaches
(Original) The display apparatus of claim 8, wherein the first line comprises
a scan line (151 – Fig. – [0072] – “First and second scan lines 151 and 152 … may extend to the first direction DR1), and the second line comprises a data line (171a – [0082] – “data lines 171a, 171b, and 171c may be arranged on a first side of the pixel circuit portions PX1, PX2 and PX3 and disposed adjacent to each other in the first direction DR1”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the first and second line structure as taught by Park into Choi, Nishiyama, Choi-656, and Lin and Zhang.
An ordinary artisan would have been motivated to use the known technique of Park in the manner set forth above to produce the predictable result of a display device.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Claims 11 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Choi-656 and Lin.
Regarding independent claim 11, Choi teaches
(Currently Amended) A display apparatus (100 – Fig. 1 – [0042] –
“foldable display device 100”) including a folding area (FA – Fig. 1 – [0041] – “folding area FA) and a non-folding area (NFA – Fig. 1 – [0041] – “non-folding area NFA), the
display apparatus (100) comprising:
a substrate (101 – Fig. 2A – [0053] – “substrate 101”) including pixel circuit
areas (Fig. 2A annotated, see below – hereinafter ‘PCA’), line areas arranged between the pixel circuit areas, and non-line areas which are arranged between the line areas and in which no line or transistor is arranged;
a pixel circuit (Fig. 2A annotated, see below – [0040] – “In the organic light emitting display panel 110, an organic light emitting element for displaying an image, a circuit for driving the organic light emitting element, lines, and other components may be disposed” – hereinafter ‘PC’) arranged in the pixel circuit areas (PCA) and comprising at least one thin film transistor (120 – Fig. 2A – [0084] – “thin film transistor 120”);
a plurality of lines ([0040] – “In the organic light emitting display panel 110, an organic light emitting element for displaying an image, a circuit for driving the organic light emitting element, lines, and other components may be disposed” – this describes a plurality of lines in the pixel circuit) arranged in the pixel circuit areas (PCA) and the line areas (WA); and
a display element (130 – Fig. 2A – [0052] – “an organic light emitting element 130”) including a pixel electrode (131 – Fig. 2A – [0063] – “organic light emitting element 130 includes the anode electrode 131”) connected to the pixel circuit (PC),
wherein in a plan view an area of one of the pixel circuit areas (Fig. 2A annotated, see below – hereinafter ‘PCA’) in the folding area (FA) is the same as an area (NFA – Fig. 2 shows the PCA in FA the same size as in NFA) of one of the pixel circuit areas (PCA) in the non-folding area (NFA),
wherein the display element overlaps the pixel circuit in the plan view,
wherein an area of one of the non-line areas is about 10 percentages (%) to 25 % of an area of one of the pixel circuit areas in a plan view.
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Choi does not expressly disclose the other limitations of claim 11.
However, in an analogous art, Choi-656 teaches
wherein the display element (PA – Fig. 3 – [0047] – “light emission areas PA” – this corresponds to a display element) overlaps the pixel circuit (PC – Fig. 3 – [0114] – “first electrode 221 that is electrically connected to the pixel circuit portion PC is included in the light emission area PA, and the pixel circuit portion PC overlaps with the first electrode 221”) in the plan view (Fig. 3 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the display element area as taught by Choi-656 into Choi.
An ordinary artisan would have been motivated to use the known technique of Choi-656 in the manner set forth above to produce the predictable result of [0009] – “display panel pertaining to one aspect of the present invention can be manufactured in the above-mentioned manufacturing process, reduction in manufacturing yield can be suppressed.”
Choi and Choi-656 do not expressly disclose the other limitations of claim 11.
However, in an analogous art, Lin teaches
pixel circuit areas (911, 921, 931 – Fig. 9A – {[0105] – “the control of OLED
stacks 911, 921 and 931”}, {[0053] – “The electrodes 265 and 267 may be configured to implement either an active matrix (with additional pixel-level circuitry not shown in this example) or a passive matrix control methodology of the respective OLEDs 257” – OLED stacks are considered pixel circuits, hereinafter ‘PCA’), line areas (Fig. 9A annotated, see below – {V29 and V49 - Fig. 9A – [0106] – “two column electrodes such as V29 and V49”}, {783-786 – Fig. 7 – [0092] – “row electrode 783 or 785 and column electrode 784 or 786 to form a passive matrix array”} – these are considered line areas, hereinafter ‘WA’) arranged between the pixel circuit areas (PCA), and non-line areas (Fig. 9A annotated, see below – 721-724 – Fig. 7 – [0092] – “The display pixels 711-714 also include transparent areas 721-724. It should be noted that, in the illustrated example, the transparent areas 721-724 surround the respective stacked RGB emitter 775-778. Each stacked RGB emitter 775-778 in respective display pixels 711-714 is interconnected with a row electrode, such as row electrode 783 or 785 and column electrode 784 or 786 to form a passive matrix array” – this describes an area free of wires or pixel circuit components, hereinafter ‘NWA’) which are arranged between the line areas (WA) and in which no line or transistor ([0067] – “Active matrix (AM) OLEDs include transistors” – Fig. 4A shows this) is arranged;
wherein an area of one of the non-line areas (NWA) is about 10 percentages (%) to 25 % of an area ([0061] – “the ratio of area occupied by the OLED stack 375 to transparent area 379 remains at approximately 20% to 80%” – the describes the transparent (non-line) area is approximately 20% of the OLED stack (pixel circuit) area) of one of the pixel circuit areas (911, 921, 931 – Fig. 9A – {[0105] – “the control of OLED stacks 911, 921 and 931”}, {[0053] – “The electrodes 265 and 267 may be configured to implement either an active matrix (with additional pixel-level circuitry not shown in this example) or a passive matrix control methodology of the respective OLEDs 257” – OLED stacks are considered pixel circuits) in a plan view (Fig. 9A shows this).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the pixel circuit area with line and non-line areas as taught by Lin into Choi and Choi-656.
An ordinary artisan would have been motivated to use the known technique of Lin in the manner set forth above to produce the predictable result [0010] – “to improve upon the transmissivity of transparent OLED display devices for various applications, including for use as (or as part of) a lighting device.”
Regarding claim 13, Choi, as modified by Choi-656, and Lin, teaches claim 11 from which claim 13 depends. Choi and Choi-656 do not expressly disclose the limitations of claim 13.
However, in an analogous art, Lin teaches
(Original) The display apparatus of claim 11, wherein the pixel circuit areas
(OLED – [0067] – “Active matrix (AM) OLEDs include transistors, interconnections and capacitors” – this is a pixel circuit area) and the line areas (WA) are alternately arranged in a first direction (Fig. 9A annotated, see above – hereinafter ‘x’) and a second direction (Fig. 9A annotated, see above – hereinafter ‘y’) intersecting with the first direction (x – Fig. 9A annotated shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the pixel circuit area with line and non-line areas as taught by Lin into Choi, Nishiyama, and Choi-656.
An ordinary artisan would have been motivated to use the known technique of Lin in the manner set forth above to produce the predictable result as stated above in claim 11.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Choi-656, Lin, and Huang.
Regarding claim 15, Choi, as modified by Choi-656, and Lin, teaches claim 11 from which claim 15 depends. Choi, Choi-656, and Lin do not expressly disclose the limitations of claim 15.
However, in an analogous art, Huang teaches
(Original) The display apparatus of claim 11, wherein each of the pixel
circuit areas (310 – Fig. 3 – [0134] – “circuit area 310 includes a third gate driving circuit (not shown in the figure), a second gate driving circuit GOA2 and a first gate driving circuit GOA1” – this is a pixel circuit area) includes two pixel circuits (GOA1 and Goa2 – Fig. 3 – [0134] – “second gate driving circuit GOA2 and a first gate driving circuit GOA1” – these are pixel circuits).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the two pixel circuit structure as taught by Huang into Choi, Choi-656, and Lin.
An ordinary artisan would have been motivated to use the known technique of Huang in the manner set forth above to produce the predictable result as stated above in claim 5.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Choi-656, Lin, and Yoon.
Regarding claim 16, Choi, as modified by Choi-656, and Lin, teaches claim 11 from which claim 16 depends. Choi, Choi-656, and Lin do not expressly disclose the limitations of claim 16.
However, in an analogous art, Yoon teaches
(Original) The display apparatus of claim 11, further comprising an
inorganic insulating layer (125 – Fig. 3 – [0084] – “inorganic insulating layer 125 may include a groove GR corresponding to the bending area BA as illustrated in FIG. 3”) defining a groove (GR – Fig. 3 – [0084] – “inorganic insulating layer 125 may include a groove GR corresponding to the bending area BA as illustrated in FIG. 3”) therein in the line areas ([0007] – “wiring unit extending to the second area through the bending area, the wiring unit arranged on the inorganic insulating layer and at least a portion thereof overlapping the opening or the groove”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the inorganic insulating layer and groove structure as taught by Yoon into Choi, Choi-656, and Lin.
An ordinary artisan would have been motivated to use the known technique of Yoon in the manner set forth above to produce the predictable result as stated above in claim 6.
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Choi-656, Lin, and Park.
Regarding claim 17, Choi, as modified by Choi-656, and Lin, teaches claim 11 from which claim 17 depends. Choi, Choi-656, and Lin do not expressly disclose the limitations of claim 17.
However, in an analogous art, Park teaches
(Original) The display apparatus of claim 11, wherein the pixel electrode
(191c – Fig. 3 – [0111] – “pixel electrode 191c”) at least partially overlaps the line areas (171a, 171b, 171c – Fig. 3 – [0078] – “plurality of data lines 171a, 171b, and 171c” – this is a line area) in the plan view.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the pixel electrode structure as taught by Park into Choi, Choi-656, and Lin.
An ordinary artisan would have been motivated to use the known technique of Park in the manner set forth above to produce the predictable result as stated above in claim 7.
Claims 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Choi-656, Lin, and Zhang.
Regarding claim 18, Choi, as modified by Choi-656, and Lin, teaches claim 11 from which claim 18 depends. Choi, Choi-656, and Lin do not expressly disclose the limitations of claim 18.
However, in an analogous art, Zhang teaches
(Original) The display apparatus of claim 11, wherein the plurality of lines
([0016] – “a plurality of pixel driving circuits, wherein the plurality of pixel driving circuits and the plurality of anodes are disposed in a one-one-to correspondence manner, each of the plurality of anodes is electrically connected to a corresponding one of the plurality of pixel driving circuit” – this infers a plurality of lines as they are necessary to connect the drive circuits) comprises a first line (131 – Fig. 8B – [0132] – “reset signal line 131 extending along the first direction”) extending in a first direction (First Direction – Fig. 8B – [0132] – “reset signal line 131 extending along the first direction”) and a second line (152 – Fig. 8D – [0135] – “first conductive layer 150 (that is, the first source-drain metal layer) includes a power wire 151, a data line 152”) extending in a second direction (Second Direction – Fig. 8D shows this”) intersecting with the first direction, the first line (131) is arranged in a same layer as a gate electrode (130 – Fig. 8B – [0113] – “first gate electrode layer 130” – Fig. 8B shows this) of the thin film transistor ([0025] – “gate electrode of a drive thin film transistor” – although not shown, it is specified that it exists in the device), and the second line (152) is arranged in a different layer from the first line (131).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the first and second line structure as taught by Zhang into Choi, Choi-656, and Lin.
An ordinary artisan would have been motivated to use the known technique of Zhang in the manner set forth above to produce the predictable result as stated above I claim 8.
Regarding claim 19, Choi, as modified by Choi-656, Lin, and Zhang, teaches claim 18 from which claim 19 depends. Choi, Choi-656, and Lin do not expressly disclose the limitations of claim 19.
However, in an analogous art, Zhang teaches
(Original) The display apparatus of claim 18, wherein the second line (152) is arranged farther from an upper surface of the substrate (110 – Fig. 18A – [0090] – “base substrate 110”) than the first line (131) in a thickness direction (Fig. 18A annotated, shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the first and second line structure as taught by Zhang into Choi, Choi-656, and Lin.
An ordinary artisan would have been motivated to use the known technique of Zhang in the manner set forth above to produce the predictable result as stated above in claim 8.
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Choi in view of Choi-656, Lin, Zhang, and Park.
Regarding claim 20, Choi, as modified by Choi-656, Lin, and Zhang, teaches claim 18 from which claim 20 depends. Choi, Choi-656, Lin, and Zhang do not expressly disclose the limitations of claim 20.
However, in an analogous art, Park teaches
(Original) The display apparatus of claim 18, wherein the first line
comprises a scan line (151 – Fig. – [0072] – “First and second scan lines 151 and 152 … may extend to the first direction DR1), and the second line comprises a data line (171a – [0082] – “data lines 171a, 171b, and 171c may be arranged on a first side of the pixel circuit portions PX1, PX2 and PX3 and disposed adjacent to each other in the first direction DR1”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the first and second line structure as taught by Park into Choi, Choi-656, Lin, and Zhang.
An ordinary artisan would have been motivated to use the known technique of Park in the manner set forth above to produce the predictable result of a display device.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Pertinent Art
For the benefits of the Applicant, US 11251381 B2, US 20230209952 A1, and US 20220302238 A1 are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. These references fail to disclose the combination of limitations including "pixel circuit areas".
Conclusion
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/GRA/
Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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