Prosecution Insights
Last updated: October 02, 2026
Application No. 18/122,646

HIGH VOLTAGE NOISE CANCELLATION

Non-Final OA §102§103
Filed
Mar 16, 2023
Examiner
POOS, JOHN W
Art Unit
2843
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Applied Materials Israel Ltd.
OA Round
2 (Non-Final)
93%
Grant Probability
Favorable
2-3
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 93% — above average
93%
Career Allowance Rate
1312 granted / 1404 resolved
+25.4% vs TC avg
Minimal +5% lift
Without
With
+4.6%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 10m
Avg Prosecution
29 currently pending
Career history
1424
Total Applications
across all art units

Statute-Specific Performance

§101
0.9%
-39.1% vs TC avg
§103
31.2%
-8.8% vs TC avg
§102
54.1%
+14.1% vs TC avg
§112
5.3%
-34.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1404 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments with respect to claim(s) 1-15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-4, 8-11, and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Arndt et al. (US 2020/0044625). In regard to Claim 1: Arndt discloses, in Figure 1, a high voltage noise reduction unit, the high voltage noise reduction unit comprising: an input (4) that is configured to receive a high voltage input signal having a value of at least five hundred volts (¶ 0011); a positive isolated supply unit (4 connected to 6) that is configured to receive the high voltage input signal (4) and to output a positive supply signal that floats on is referenced solely to the high voltage input signal (4) and is electrically isolated from ground (¶ 0049); a negative isolated supply unit (4 connected to 7) that is configured to receive the high voltage input signal (4) and to output a negative supply signal that floats on is referenced solely to the high voltage input signal (4) and is electrically isolated from ground (¶ 0049); a low pass filter (Figure 3: 12 of 2 in Figure 1, ¶ 0017) that is configured to filter the high voltage input signal (4) to provide a filtered high voltage signal (Figure 3: 12 output, ¶ 0017); and an amplifier (Figure 3: 13 of 2 in Figure 1) that is configured to receive the positive supply signal (6 at 8), to receive the negative supply signal (7 at 9), to receive the filtered high voltage signal (Figure 3: 12 output), and amplify the filtered high voltage signal (Figure 3: 12 output) to provide a high voltage output signal (¶ 0051). In regard to Claim 2: Arndt discloses, in Figure 1, the high voltage noise reduction unit according to claim 1, wherein each one of the amplifier (2), the positive isolated supply unit (6) and the negative isolated supply unit (7) are low voltage components that are subjected to low voltage differences that do not exceed 24 volts (¶ 0027-0028). In regard to Claim 3: Arndt discloses, in Figure 3, the high voltage noise reduction unit according to claim 1, wherein a voltage level of the filtered high voltage signal (12 output) equals a voltage level of the high voltage output signal (¶ 0055). In regard to Claim 4: Arndt discloses, in Figure 3, the high voltage noise reduction unit according to claim 1, wherein the low pass filter comprises a resistor and a capacitor (C5,R1; C6,R3; C7, R6). In regard to Claim 8: Arndt discloses, in Figure 1, a method for high voltage noise reduction unit, the method comprising: receiving a high voltage input signal, by (i) an input of the high voltage noise reduction unit, (ii) a positive isolated supply unit (4 connected to 6), (iii) a negative isolated supply unit (4 connected to 7), and (iv) a low pass filter (Figure 3: 12, ¶ 0017); wherein the high voltage input signal (4) has a value of at least five hundred volts (¶ 0011); outputting, by the positive isolated supply unit (6), a positive supply signal that floats on is referenced solely to the high voltage input signal (4) and is electrically isolated from ground (¶ 0049); outputting, by the negative isolated supply unit (7), a negative supply signal that floats on is referenced solely to the high voltage input signal (4) and is electrically isolated from ground (¶ 0049); filtering, by the low pass filter (Figure 3: 12), the high voltage input signal to provide a filtered high voltage signal (Figure 3: 12 output, ¶ 0017); receiving, by an amplifier (Figure 3: 13), the positive supply signal (6 connected to 8), the negative supply signal (7 connected to 9) and the filtered high voltage signal (Figure 3: 12 output); and amplifying the filtered high voltage signal (Figure 3: 12 output), by the amplifier (Figure 3: 13), to provide a high voltage output signal (¶ 0051). In regard to Claim 9: Arndt discloses, in Figure 1, the method according to claim 8, wherein each one of the amplifier (2), the positive isolated supply unit (6) and the negative isolated supply unit (7) are low voltage components that are subjected to low voltage differences that do not exceed 24 volts (¶ 0027-0028). In regard to Claim 10: Arndt discloses, in Figure 1, the method according to claim 8, wherein a voltage level of the filtered high voltage signal (12 output) equals a voltage level of the high voltage output signal (¶ 0055). In regard to Claim 11: Arndt discloses, in Figure 3, the method according to claim 8, wherein the low pass filter comprises a resistor and a capacitor (C5,R1; C6,R3; C7, R6). In regard to Claim 15: Arndt discloses, in Figure 1, a high voltage noise reduction unit, the high voltage noise reduction unit comprising: an input (4) that is configured to receive a high voltage input signal having a value of at least five hundred volts (¶ 0011); a positive isolated supply unit (4 connected to 6) that is configured to receive the high voltage input signal (4) and to output a positive supply signal that floats on is referenced solely to the high voltage input signal (4) and is electrically isolated from ground (¶ 0049); a negative isolated supply unit (4 connected to 7) that is configured to receive the high voltage input signal (4) and to output a negative supply signal that floats on is referenced solely to the high voltage input signal (4) and is electrically isolated from ground (¶ 0049); a low pass filter (Figure 3: 12 of 2 in Figure 1, ¶ 0017) that is configured to filter the high voltage input signal (4) to provide a filtered high voltage signal (Figure 3: 12 output, ¶ 0017); and a buffer (Figure 3: 13) that is configured to receive the positive supply signal (6 connected to 8), to receive the negative supply signal(7 connected to 9), to receive the filtered high voltage signal (Figure 3: 12 output) and to output a high voltage output signal that equals the filtered high voltage signal (¶ 0051). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 5 and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Arndt et al. (US 2020/0044625). In regard to Claim 5: Arndt discloses the claimed invention as discussed with respect to Claims 1 and 4 above, except for wherein an impedance of the resistor is not lower than one megaohms. It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to have an impedance of the resistor that is not lower than one megaohms, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. MPEP 716.02(b) III. In regard to Claim 12: Arndt discloses the claimed invention as discussed with respect to Claims 8 and 11 above, except for wherein an impedance of the resistor is not lower than one megaohms. It would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to have an impedance of the resistor that is not lower than one megaohms, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. MPEP 716.02(b) III. Allowable Subject Matter Claims 6-7, 13-14, and 16-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. In regard to Claim 6: None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims: wherein the amplifier comprises: an inverting input; a noninverting input that is configured to receive filtered high voltage signal; a negative supply port that is configured to receive the negative supply signal; a positive supply port that is configured to receive the positive supply signal; and an output port that is in communication with the inverting input and is configured to output the high voltage output signal. In regard to Claim 13: None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims: wherein the amplifier comprises an inverting input, a noninverting input, a negative supply port, a positive supply port and an output port that is in communication with the inverting input; wherein the method comprises: receiving the negative supply signal by the negative supply port; receiving the positive supply signal by the positive supply port; and outputting, by the output port, the high voltage output signal. In regard to Claim 16: None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims: wherein the amplifier comprises a non-inverting input, an inverting input and an output, and wherein the non- inverting input is coupled to receive the filtered high voltage signal, and the inverting input is coupled to the output. In regard to Claim 18: None of the prior art or combination thereof teaches or fairly suggests the following features in combination with the other limitations of the claims: wherein the amplifier comprises a non- inverting input, an inverting input and an output, and wherein the non-inverting input is coupled to receive the filtered high voltage signal, and the inverting input is coupled to the output. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Wang et al. (US 2018/0088152) discloses a high side current sensing amplifier architecture is simplified and improved over prior art current sensing amplifier circuits by using chopping only, without requiring auto-zeroing, and by using a simpler (and faster) switched capacitor filter instead of an auto-zeroing integrator filter. Also, VIP (positive DC sense node) is merged with the VDDHV (power supply) node, such that the integrated circuit package requires only a single node (package pin) to accommodate both the VIP and VDDHV connections for the current sensing amplifier circuit, resulting in being able to use a smaller integrated circuit package. Herman (US 2024/0364278) discloses a cascoded high-voltage amplifier is disclosed. The amplifier can include a chain of series-coupled low-voltage amplifiers, sometimes with a common gain, where an output of each low-voltage amplifier is coupled to an input of a next low-voltage amplifier, and inputs of adjacent low-voltage amplifiers are coupled via a feedforward connection, and optionally through an impedance component. In this way, a change in the input signal can level shift the entire chain of low-voltage amplifiers through the feedforward connections. The gain of the cascoded high-voltage amplifier can be a function of the number of low-voltage amplifiers, and a high-voltage output can be achieved without seeing high-voltage drops within the amplifier. Rada et al. (US 2011/0148202) discloses power factor correction that includes selectively coupling bit reactive loads with a load having dynamic reactive properties to dynamically correct a power factor. Methods and apparatus for reducing distortion in a power delivery system include a means for determining distortion in a power line, forming a corrective signal according to the distortion and selectively sinking and sourcing current to the power line according to the corrective signal. Any inquiry concerning this communication or earlier communications from the examiner should be directed to John W Poos whose telephone number is (571)270-5077. The examiner can normally be reached M-Th 8-5. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at 571-272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JOHN W POOS/Primary Examiner, Art Unit 2843
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Prosecution Timeline

Mar 16, 2023
Application Filed
Jul 31, 2025
Non-Final Rejection mailed — §102, §103
Oct 28, 2025
Response Filed
Sep 25, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

2-3
Expected OA Rounds
93%
Grant Probability
98%
With Interview (+4.6%)
1y 10m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 1404 resolved cases by this examiner. Grant probability derived from career allowance rate.

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