DETAILED ACTION
This Office Action is in response to Applicant’s Amendment dated 11/25/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 and 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Xie et al [USD 2022/0020688]
► With respect to claim 1, Xie at al (figs 1, 4A-4B, text [0001]-[0068]) discloses the claimed semiconductor interconnect structure, comprising:
a lower level via (Vx-1, text [0011]) that is fully aligned to an upper level metal line (Mx), wherein: the lower level via is elongated along a lower level metal line direction (direction of lower level metal line Mx-1); and a first length of a top portion of the lower level via (Vx-1, fig 4B) running along the lower level metal line direction is less than a second length of a bottom portion of the lower level via running along the lower metal line direction.
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► With respect to claim 2, Xie at al (fig 1) discloses the upper level metal line direction runs perpendicular to the lower level metal line direction.
► With respect to claim 3, Xie at al ( figs 1/4A/4B) discloses the lower level via electrically connects the lower level metal line to the upper level metal line.
► With respect to claim 4, Xie at al (text [0031]) discloses the lower level via is formed from a conductive metal material selected from the group consisting of aluminum (AI), ruthenium (Ru), rhodium (Rh), iridium (Ir), tungsten (W), molybdenum (Mo), and nickel (Ni).
► With respect to claim 5, Xie at al (text [0034]) discloses the upper level metal line is formed from copper (Cu).
► With respect to claim 7, Xie et al (fig 4B) discloses he lower level via includes a first vertical portion, a second vertical portion located adjacent to a first side of the first vertical portion, and a third vertical portion located adjacent to a second side of the first vertical portion;the second and third vertical portions of the lower level via are partially recessed with respect to a top surface the first vertical portion of the lower level via; and the upper level metal line is only located above the first vertical portion of the lower level via.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 8-12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Xie et al [USD 2022/0020688] in view of Huang et al [US 2021/0175125]
► With respect to claims 8-9, Xie et al al (figs 1, 4A-4B, text [0001]-[0068]) discloses a semiconductor interconnect structure, comprising:
a contact via (Vx-1, text [0011]) that is fully aligned to an upper level metal line (Mx), wherein a first length of a top portion of the contact via is less than a second length of a bottom portion of the contact via running along the gate direction.
Xie et al does not expressly teach the contact via is a elongated along a gate direction.
However, Huang et al (figs 11/21C) teaches using the contact via (82/116) is elongated along a gate direction (see fig 11) wherein the contact via located on top of a source drain contact.
Therefore, it would have been obvious for those skilled in art, in view of Huang et al, to have the via contact elongated and on top of source drain contact as being claimed to provide interconnection as being needed for transistor device operation. Combination of Xie et al in view Huang would provide the first length of the top portion of contact via running along the gate direction being less than the second length of the bottom portion of the via contact along the gate direction.
► With respect to claim 10, combination of Xie at al in view of Huang et al would provide the contact via electrically connects the source/drain contact to the upper level metal line.
► With respect to claim 11, Xie at al (text [0031]) discloses the lower level via is formed from a conductive metal material selected from the group consisting of aluminum (Al), ruthenium (Ru), rhodium (Rh), iridium (Ir), tungsten (W), molybdenum (Mo), and nickel (Ni).
► With respect to claim 12, Xie at al (text [0034]) discloses the upper level metal line is formed from copper (Cu).
► With respect to claim 14, Xie et al (fig 4B) discloses the contact via includes a first vertical portion, a second vertical portion located adjacent to a first side of the first vertical portion, and a third vertical portion located adjacent to a second side of the first vertical portion;the second and third vertical portions of the contact via are partially recessed with respect to a top surface the first vertical portion of the contact via; and the upper level metal line is only located above the first vertical portion of the contact via.
Conclusion
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/THANHHA S PHAM/Primary Examiner, Art Unit 2812