DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6 and 10-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by WO 2017/146493 A1 to Lim et al. (hereinafter “Lim” – previously cited reference), with US 2019/0067255 A1 being used as the translation of WO 2017/146493 A1.
Regarding claim 1, Lim discloses an electronic device, comprising:
a driving circuit substrate comprising a plurality of active elements (light emitting device package 100 having substrate 120 with plurality of active elements; Fig. 3; paragraphs [0044] and [0050]-[0051]);
a plurality of chips disposed on the driving circuit substrate and electrically connected to the driving circuit substrate (LED chips 151-153 disposed on substrate 120; Fig. 3; paragraph [0044]);
a passivation layer covering the plurality of chips and the driving circuit substrate (passivation layer 170 covering each of LED chips 151-153 and substrate 120; Fig. 3), and
a wall structure disposed between the driving circuit substrate and the passivation layer, wherein the wall structure has a plurality of openings, at least one of the plurality of chips is disposed in one of the plurality of openings (upper electrode 131-134 wall structure disposed between passivation layer 170 and substrate 120 and under LED chips 151-153 with vertical openings disposed between each electrode 131-134 within which LED chips are disposed and cover the vertical openings; Fig. 3), the plurality of openings penetrate through the wall structure, and orthographic projections in a top view of the plurality of chips and the wall structure do not overlap (vertical openings penetrate through upper electrode 131-134 wall structure and central portion of orthographic projection of chips 151-153 do not overlap with upper electrode 131-134 wall structure; Fig. 3), wherein the passivation layer has a first part on one of the plurality of chips and a second part on a part of the driving circuit substrate, the second part is not overlapped with the plurality of chips, and a first thickness of the first part is less than a second thickness of the second part (passivation layer 170 has first part disposed over LED chips 151-153 and second part disposed over substrate 120, where first part has thickness less than second part; Fig. 3); and wherein a first space between adjacent two of the plurality of chips is different from a second space between another adjacent two of the plurality of chips (space between LED chips 151 and 153 is different than space between LED chips 152 and 153; Fig. 3).
Regarding claim 2, Lim discloses the electronic device of claim 1, wherein the first thickness is greater than 1 micrometer (first part of passivation layer 170 has thickness greater than 1 micron as shown by distance D2 being 75 microns or more; Fig. 3; paragraph [0057]).
Regarding claim 3, Lim discloses the electronic device of claim 1, wherein the first part is directly on the one of the plurality of chips, and the second part is directly on the part of the driving circuit substrate (first part of passivation layer 170 disposed directly on LED chips 151-153 and second part directly on substrate 120; Fig. 3).
Regarding claim 4, Lim discloses the electronic device of claim 3, wherein the passivation layer directly contacts a top surface and two side surfaces of the one of the plurality of chips (passivation layer 170 disposed on top surface and two side surfaces of LED chips 151-153; Fig. 3).
Regarding claim 6, Lim discloses the electronic device of claim 1, further comprising a non-self-emissive panel and a backlight module, wherein the backlight module comprises the driving circuit substrate, the plurality of chips, and the passivation layer (light emitting device package 100 may be used in an LCD as a backlight unit; paragraphs [0006]-[0008] and [0147]).
Regarding claim 10, Lim discloses the electronic device of claim 1, wherein the first thickness of the first part is less than or equal to the first space between adjacent two of the plurality of chips (thickness of first part of passivation layer 170 disposed over LED chips 151-153 may be defined such that it has a smaller thickness than the spacing between any of the chips 151-153; Fig. 3).
Regarding claim 11, Lim discloses the electronic device of claim 1, wherein the plurality of chips do not contact the wall structure in a cross-sectional view (portion of each of the chips 151-153 does not contact the electrode 131-134 wall structure in cross-sectional view; Fig. 3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Lim further in view of US 2017/0373014 A1 to Yen et al. (hereinafter “Yen” – previously cited reference).
Regarding claim 5, Lim discloses the electronic device of claim 1. Lim fails to disclose wherein one of the plurality of active elements comprises a transistor.
However, Yen discloses wherein one of the plurality of active elements comprises a transistor (active elements are thin-film transistor elements; paragraph [0026]).
Lim and Yen are both considered to be analogous to the claimed invention because they are in the same field of display devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Lim to incorporate the teaching of Yen in order to potentially provide precise pixel control, faster response times, and improved power efficiency.
Claims 7 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Lim further in view of US 2014/0153212 A1 to Chen (hereinafter “Chen” – previously cited reference).
Regarding claim 7, Lim discloses the electronic device of claim 1. Lim fails to disclose wherein the passivation layer comprises epoxy resin.
However, Chen discloses wherein the passivation layer comprises epoxy resin (hybrid backlight LCD unit 40 having protective layer 41 made from epoxy resin; paragraphs [0012], [0022]).
Lim and Chen are both considered to be analogous to the claimed invention because they are in the same field of display devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Lim to incorporate the teaching of Chen in order to potentially provide environmental protection, strong adhesion, chemical resistance, and high mechanical strength and durability.
Regarding claim 9, Lim discloses the electronic device of claim 1. Lim fails to disclose a diffuser plate and a brightness enhancement film disposed on the plurality of chips.
However, Chen discloses a diffuser plate and a brightness enhancement film disposed on the plurality of chips (hybrid backlight LCD unit 40 having polarizing film 42, connecting layer 43, and diffusion layer 44 which increases on-axis luminance of incident light for the viewer of the LCD; Fig. 2; paragraph [0022]).
Lim and Chen are both considered to be analogous to the claimed invention because they are in the same field of display devices. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Lim to incorporate the teaching of Chen in order to potentially provide uniform light distribution, improved viewing angles, increased on-axis brightness, and improved power efficiency.
Response to Arguments
Applicant's arguments filed June 24, 2026 have been fully considered. Applicant amended claim 1 and added new claim 10-11 with corresponding arguments. Specifically, Applicant asserts that Lim does not disclose the content amended into claim 1, but Applicant seemingly does not consider that the claim scope of the amended language encompasses a portion of the orthographic projections of chips 151-153 not overlapping with upper electrode 131-134 wall structure. If Applicant intended to claim that an entirety of the orthographic projections of the chips do not overlap the wall structure, then such language (which would overcome the current 35 USC 102 rejection) should be amended into claim 1.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IAN DEGRASSE whose telephone number is (571) 272-0261. The examiner can normally be reached Monday through Friday 8:30a until 5:00p.
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/IAN DEGRASSE/Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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