DETAILED ACTION
This action is responsive to the amendments filed January 21, 2026. Claims 1-3, 5, 11-14 and 16 have been amended. Claims 4 and 15 have been cancelled. Therefore, upon entry of these amendments, claims 1-3, 5-14, and 16-20 are currently pending. Claims 1, 11, and 12 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendments to claims 1-3, 5, 11-14 and 16 replacing the phrase "preferable clock phase" by "clock phase" has been acknowledged and accepted. The 35 USC § 112(b) rejections for indefiniteness due to that issue have been withdrawn.
The amendments to claims 1, 11, and 12 regarding the multiplexers have been acknowledged and accepted. The 35 USC § 112(b) rejections for indefiniteness due to that issue have been withdrawn.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1, 9-12 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Omori (US 20080148092 – of Record) as supported by Han et al. (US 20230082056; “Han” – of Record) in view of Lee et al. (US 20190080730; “Lee”- of Record).
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Regarding independent claims 1, 11 and 12, Omori discloses a memory access interface device, operation method, and a memory system, comprising (Fig. 1:100 illustrates a processing circuit having an interface unit 18 accessing an external memory 200):
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a clock generation circuit (Fig. 1, CLK system input signal, and Fig. 2 delay buffers which combined are analogous to Fig. 2: 200 clock generation circuit of the instant application. It is noted that it is well understood in the art that a system clock is necessarily a component of a memory device as a source, an example of which is illustrated in Han Fig. 1: 100 clock generation circuit);
a transmitting circuit (Fig. 2: 34 (analogous to TX3 of instant application), and 32 (analogous to TX2);
a receiving circuit (Fig. 2:36 data reading section);
a signal training circuit configured for: for one of a plurality of loops of a training process in a training mode, generating a training data signal and a training data strobe signal (Fig. 1: 10, 12, 14, 16. (See Examiner's Markup Omori Fig. 1). It is noted that while not specifically defined in the instant application, the term “training data signal" and the term "training data strobe signal" appear to be directed to symbols DQT and DQST of Fig. 2 respectively (and as further instantiated in Spec. para. 39). Mux2 of Fig. 2 of the instant application appears to associate symbols DQT and WD ("write data" per Spec. para. 23). It is therefore evinced that DQT is effectively modified write data. It is further noted that Omori's circuit 14 generates this analogous signal: "a data value for use in test of the timing adjustment is output to the write data generating section 14" (para. 17). The symbols DQST and WE ("write enable" per Spec. para. 23) are similarly associated with MUX3. It is therefore evinced that DQST is analogous to a write enable signal which is well understood in the art as a necessary memory control signal common to all memories such as the LPDDR memory indicated in the instant application)
such that the transmitting circuit selects the training data signal and the training data strobe signal to be transmitted as an output data signal and an output data strobe signal to a memory device (see DQO and DQSO on Examiner's Markup Omori Fig. 2)
according to a plurality of timing reference signals generated according to the clock generation circuit each having a phase (Fig. 2. where it illustrates delay buffers. It is noted that delay buffers necessarily change the phase of the input timing signal),
wherein the timing reference signals are used as timing references of the transmission of the output data signal and the output data strobe signal, the timing reference signals are not transmitted to the memory device (Fig. 2 where it illustrates that the outputs of the delay buffers which are analogous to the timing reference signals which drive TX2 and TX3 of the instant applications are not transmitted to the memory device);
and controlling the clock generation circuit to modify the phase of one of the timing reference signals, in order to further modify the timing of one of the training data signal and the training data strobe signal (Fig. 2 where it illustrates the incoming signal “TIMING CHANGE” which selects from a plurality of phase adjusted clocks which in turn, modifies the timing of the training data signal),
a data multiplexer coupled to the transmitting circuit such the data multiplexer, selects the training data signal from the signal training circuit (See "Signal training circuit" on Examiner's Markup Omori Fig. 1. and specifically, the output of 14 writing data generation section. See also para 17; "a data value for use in test of the timing adjustment is output to the write data generating section 14". It is noted that Omori's test data value is necessarily analogous to the training data of the instant application as they are both used for the same stated purpose. Further, the location of the claimed data multiplexer is not specified, only that it exists, is coupled to the transmitting circuit and selects the training data signal. It is well understood in the art that a circuit that selects (or chooses) a signal to output is functionally equivalent to a multiplexer and the set of logic gates used to implement is merely a routine engineering choice)
to be transmitted by the transmitting circuit as the output data signal when the memory access interface device is set to operate in the training mode (Fig. 2: 32 (analogous to the transmitting circuit TX2 of the instant application) which outputs Omori's test data value. See Examiner's Markup Omari Fig. 2). It is further noted that Omori's timing adjustment process (see fig. 4) is analogous to the training mode of the instant application),
and selects a write data signal from a memory access controller to be transmitted by the transmitting circuit as the output data signal (Fig. 1 output of 14 "writing data value", and the functional equivalent of a multiplexer for the same reason as above)
according to clock phases of the timing reference signals (Fig. 1 timing change signal going to 18. See also para 17; " a timing change signal for adjusting a timing for writing the data in the external memory 200", "is output to the interface unit 18". It is noted that the electrical nature of the timing reference signals is not explicitly defined in the instant application. It appears directed to DQCLK of Fig. 2 and is understood to simply be the clock (which necessarily has a clock phase) to the transmitting circuit TX)
after being trained in the training process when the memory access interface device is set to operate in an operation mode (It is noted that Omori's test (training mode) is a process separate from nominal operation (operation mode) as indicated by the last step S22 in the flow chart of Fig. 4 where the optimum timing has been selected and the training process ends. Thus, nominal write data would be selected to be transmitted by the transmitting circuit 32);
and a data strobe multiplexer (Fig. 2:34g multiplexer)
coupled to the transmitting circuit (Fig. 2: 34 which transmits the clock strobe (CLKd - analogous to TX3 and DQSO of instant application))
such that the data strobe multiplexer, selects the training data strobe signal from the signal training circuit to be transmitted by the transmitting circuit as the output data strobe signal when the memory access interface device is set to operate in the training mode (Fig. 2 where it depicts the multiplexer selecting the data strobe signal from one of 34a through 34f. It is further noted that Omori's timing adjustment process (see fig. 4) is analogous to the training mode of the instant application),
and selects a write enable signal from the memory access controller to be transmitted by the transmitting circuit as the output data strobe signal according to the clock phases of the timing reference signals after being trained in the training process when the memory access interface device is set to operate in the operation mode (It is noted that Omori's test (training mode) is a process separate from nominal operation (operation mode) as indicated by the last step S22 in the flow chart of Fig. 4 where the optimum timing has been selected and the training process ends. Thus, the write data strobe would be the final phase selected (in S22) and would thereafter be transmitted by the transmitting circuit 34).
While Omori discloses a training process flow and comparing returned training data, it is silent with respect to explicit loops of the training process and also with a separate return data strobe.
However, Lee teaches receiving a read data signal from the receiving circuit, wherein the receiving circuit receives a returned data signal, and a returned data strobe signal generated by the memory device to generate the read data signal accordingly (Fig. 4, where it illustrates the read data signals DQ0-DQ7 being received by the interface circuit. See also para 58, "memory device 120 may transmit the data strobe signal DQS (not illustrated) and the data signals DQ0 to DQ7 to the flash interface 119");
comparing a content of the training data signal and the read data signal to generate a comparison result indicating whether the read data signal matches the content of the training data signal (para. 68, "The controller 110 may compare the transmitted data and the reference pattern to determine whether the rising edge of the data strobe signal DQS corresponds to the left edge LE of the data signal DQ");
storing the comparison result (para. 45, "the buffer 117 may store a training pattern transmitted from the nonvolatile memory device 120 in a read training operation or a write training operation");
to be one of a plurality of under-test phases to execute a new loop of the loops of the training process (Fig. 5, where it illustrates advancing to the next training phase from step_1 to step_2 and so forth, to detect the leading edge of the data eye window).
Omori and Lee are from the same field of endeavor as applicants’ invention being directed to data training of memory signals. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Omori with the teachings of Lee to use circuitry to adjust the phase of the signals within a memory system during a training process. Doing so would allow a precise alignment of the transmitted data with the data eye regardless of device process variation improving both the data integrity and operational frequency of the memory transfer.
Regarding claims 9 and 19, Omori supported by Han, and Lee combined disclose the limitations of claims 1 and 12 respectively.
As applied, Lee further discloses wherein the training data signal and the training data strobe signal are be transmitted as the output data signal and the output data strobe signal to a first-in-first-out (FIFO) circuit having a predetermined depth in the memory device such that the receiving circuit receives the returned data signal and the returned data strobe signal from the first-in-first-out circuit (Fig. 3:123 page buffer. See also para. 53, "The page buffer 123 of the inventive concepts may be used as a first-in first-out (FIFO) buffer that stores a training pattern in a data training operation". It is noted that all FIFO circuits necessarily have a predetermined depth and store data that can be used by other circuits).
Regarding claims 10 and 20, Omori supported by Han, and Lee combined disclose the limitations of claims 1 and 12 respectively.
As applied, Lee further discloses wherein the transmitting circuit, the receiving circuit and the signal training circuit operate according to a command clock signal generated by the clock generation circuit (Fig. 4:119 Flash interface where the receiving registers are clocked by the clock generation circuit 118 (DLL). See also para 47, "The flash interface 119 may include a clock circuit". It is further noted that all synchronous digital circuits necessarily operate from a clock signal generated by a clock generation circuit and the training circuit would necessarily be in the same clock domain as the receiving circuit for data communication to occur).
Claims 2-3, 5-8, 13-14, and 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Omori (US 20080148092 – of Record) as supported by Han et al. (US 20230082056; “Han” – of Record) in view of Lee et al. (US 20190080730; “Lee”- of Record) and further in view of Searles et al (US 20090244997; “Searles” – of Record).
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Regarding claims 2 and 13, Omori supported by Han, and Lee combined disclose the limitations of claims 1 and 12 respectively,
Omori and Lee are silent with respect to internally generated intermediary clock signals.
However, Searles teaches wherein the timing reference signals comprise
a data clock signal corresponding to the training data signal (Fig. 3:346 latch output which corresponds to DQCLK in Fig. 2 of instant application) and
a data strobe clock signal corresponding to the training data strobe signal (Fig. 3:344 latch output which corresponds to DQSCLK in Fig. 2 of instant application),
in which the data clock signal and the data strobe clock signal are provided by the clock generation circuit (Fig. 3:342 DLL and Fig. 3:360 DLL which are clock generation circuits),
the signal training circuit is further configured for:
selecting a first one of the data clock signal and the data strobe clock signal as a selected clock signal and a second one of the data clock signal and the data strobe clock signal as a non-selected clock signal (para. 44, "DLL 342 has a first input for receiving signal PCLK, a second input for receiving a delay selection value. Also, para. 45, "DLL 360 has a first input for receiving a first delay selection value.” Either DLL output signal could be designated as 'first' or 'second'.);
controlling the clock generation circuit to keep the phase of the non-selected clock signal to be a first clock phase of the clock phases (It is well known in the art that DLL (delay locked loop) circuits are used to adjust the phase of an incoming clock. Either DLL in this case could be configured to keep the input phase fixed (i.e., non-selected) while the other DLL adjusted the phase of its input (i.e., selected));
controlling the clock generation circuit to modify the phase of the selected clock signal until all the under-test phases are trained (Id., and for the same reason);
determining one of the under-test phases of the selected clock signal is valid when the corresponding comparison result indicates that the read data signal matches the content of the training data signal (Fig. 6 is a flow chart indicating the function and indicates in step 650 the comparison step and in step 660 the determination of a valid value); and
determining a second clock phase of the selected clock signal of the clock phases according to the valid under-test phases (Fig. 6, step 670 where the phase delay of the test signal is incremented if the previous value is not a pass).
Omori, Lee and Searles are from the same field of endeavor as applicants’ invention being directed to data training of memory signals by incremental clock phase adjustments. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Omori and Lee with the teachings of Searles to use internal clock generation circuitry to adjust the phase of the data signals within a memory system during a training process. Doing so would allow better signal alignment over a plurality of signal domains improving data integrity within the memory system irrespective of manufacturing process variation.
Omori and Lee combined along with Searles are from the same field of endeavor as applicants' invention being directed to training of memory timing signals. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Omori and Lee's use of circuitry to adjust the phase of the signals within a memory system during a training process with Searles timing signal training of an industry standard DDR interface. Doing so would improve memory timing over a plurality of physical memory implementations.
Regarding claims 3 and 14, Omori supported by Han, Lee and Searles combined disclose the limitations of claims 2 and 13 respectively.
As applied, Searles further teaches wherein the memory access interface device is set to operate in the operation mode such that the transmitting circuit selects the write data signal and the write enable signal to be transmitted as the output data signal and the output data strobe signal in the operation mode according to the non-selected clock signal having the first phase and the selected clock signal having the second phase (It is noted that as claimed, this is merely bypassing the normal DQ/DQS signals during normal operation which is necessarily a function of an industry standard memory interface which is well known in the art. See also Fig. 1:100 Data processing system which incorporates industry standard JEDEC DDR interface (para. 9) between the DRAM controller 114 and the DRAM memory 130.
Regarding claims 5 and 16, Omori supported by Han, Lee and Searles combined disclose the limitations of claims 2 and 13 respectively. Examiner further notes the anastrophe of the labels of various circuit elements between the clauses of claims 5 and 16 and will interpret them as linguistically equivalent as there is no differing limiting features or structures recited.
As applied, Searles further teaches wherein the signal training circuit comprises:
a signal generation circuit configured for generating the training data signal and the training data strobe signal (Fig. 2:220 transceiver generating DQS signals);
a comparison circuit configured for comparing the content of the training data signal and the read data signal to generate the comparison result (Fig. 6: step 650. See also para 63, "The flow proceeds to step 650 wherein one of the plurality of measured data values that is not a first of the plurality of measured values is compared to a corresponding one of the plurality of data elements");
a phase control circuit configured for generating a phase control signal to control the clock generation circuit to modify the phase of at least one of a plurality of clock signals to further modify the phase of at least one of the timing reference signals (Fig. 4:410 DLL. See also the flow chart of Fig. 6, step 660 and step 670 where the phase of the timing reference signals may be modified (incremented).);
a scan circuit configured for controlling the signal generation circuit and the phase control circuit to execute the loops of the training process and storing the comparison result (Fig 6, where it illustrates the flow chart with the steps for performing the loops of the training process. It is noted that 'scan circuit' is defined in the instant application as merely controlling the signal generation and phase control to execute the loops of the training process and to store the result of the comparison result (see Spec. para. 50). It is well known in the art that a digital value must be stored in some manner (such as a typical latch or register) for the comparison result in a synchronous digital circuit to be persistent and therefore used in subsequent computations.); and
a control unit configured for providing test data for generating the training data signal and the training data strobe signal and for accessing the comparison result to determine the first clock phase of the non-selected clock signal and the second clock phase of the selected clock signal. (Fig 2:210 controller and Fig. 3 where it illustrates training signals 'FROM CONTROLLER (210)' to the transceivers which comprise the test data and set the various phases involved).
Regarding claims 6, Omori supported by Han, Lee and Searles combined disclose the limitations of claim 5.
As applied, Searles further teaches wherein the control unit is implemented by using software operated by a processor (Fig. 2:210 controller. It is well known in the art that industry standard memory controllers are capable of executing software commands).
Regarding claims 7 and 17, Omori supported by Han, Lee and Searles combined disclose the limitations of claims 5 and 16 respectively.
As applied, Searles further teaches wherein the comparison result comprises a positive edge result and a negative edge result, and further selectively comprises a composite result generated by performing OR logic operation on the positive edge result and the negative edge result (With regard to a 'positive' and 'negative' edge comparison result, Applicant's Specification appears to indicate only that it corresponds to the data strobe (DQS) of an LPDDR memory system (Spec. para. 48). Since it is well known in the art that the data in a DDR memory system is transferred on both edges of the clock (DQS), Examiner will use the broadest reasonable interpretation of this claim to merely indicate that it conforms to the industry standard JEDEC DDR specification as does the memory system in Searles. The generation of a 'composite result' by performing a binary logical OR function is something that all digital memory controllers are capable of performing).
Regarding claims 8 and 18, Omori supported by Han, and Lee combined disclose the limitations of claims 1 and 12 respectively.
As applied, Searles further teaches wherein the signal training circuit is further configured for generating a training command and address signal in the training mode such that the transmitting circuit selects the training command and address signal as an output command and address signal to the memory device according to a command and address clock signal and a chip select clock signal of the timing reference signals (Fig. 1 where it illustrates the industry standard DDR bus (120) transmitting ADDR/CMD as well as communicating to a plurality of DRAM memory devices (130, 140) which, by definition, implies a chip select signal. It is evinced that these signals are utilized in the training mode as the circuitry of the transceivers (Fig. 2:222-228) are used to implement the training mode.); and
the transmitting circuit selects a command and address signal transmitted by a memory access controller to be transmitted as the output command and address signal to the memory device according to the command and address clock signal and the chip select clock signal in the operation mode (Fig. 1:100 where it illustrates the industry standard DDR bus (120) transmitting ADDR/CMD as well as communicating to a plurality of DRAM memory devices (130, 140) which, by definition, implies a chip select signal. It is evinced that these signals are utilized in the operation mode as it discloses a functional data processing system (see para. 27)).
Omori and Lee combined along with Searles are from the same field of endeavor as applicants' invention being directed to training of memory timing signals. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Omori and Lee's use of circuitry to adjust the phase of the signals within a memory system during a training process with Searles timing signal training of an industry standard DDR interface. Doing so would improve memory timing over a plurality of physical memory implementations.
Response to Arguments
Applicant contends on pgs. 19-20 of Remarks, that Searles fails to disclose various features of claims 1, 11, and 12 of the instant application. Applicant’s arguments with respect to claims 1, 11, and 12 have been considered but because different facts from the references are applied to the claims, the arguments are either unpersuasive or moot because the new ground of rejection based on the references cited above, as well as the newly cited portions of the references previously presented.
More specifically, based on Applicant's amendments curing the prior indefiniteness rejections with respect to the data and data strobe multiplexers, those features have been considered in a new light as indicated in the rejections above in which the Searles reference is not cited.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to James S. Wells whose telephone number is (703)756-1413. The examiner can normally be reached M-F 8:30-5.
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/James S. Wells/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825
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