DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Remarks/Arguments
With respect to the rejection of claims 3 and 19 under 35 USC 112(b), Examiner withdraws said rejections due to proper amendments.
With respect to the rejection of claims 1 and 17 under 35 USC 102(a)(1), Applicant's arguments filed 01/08/2026 have been fully considered but are moot in view of new grounds of rejection set forth herein as necessitated by Applicant's amendments.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1,3, 4, 5, 7-9, 17 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Weber (US 2021/0313988 A1).
Regarding claim 1, Weber teaches a system, comprising:
an application specific integrated circuit (ASIC) (Figs. 1 and 2, 102, [0010] base IC die 102) comprising:
a first network on chip (NOC) ([0023] NOC 241)
a fabric sliver comprising programmable logic circuitry ([0024] router circuits 233, [0023] 233 may be programmable), and
a plurality of hardened IP blocks comprising circuitry configured to communicate with the fabric sliver ([0010] non-programmable circuitry, e.g., processor);
a second integrated circuit separate from the ASIC ([0012] main IC die 101), the second integrated circuit comprising a programmable logic fabric ([0014] router circuits 231 that are programmable), wherein the second integrated circuit comprises a field programmable gate array (FPGA) ([0011] most or all of the programmable logic circuits in a separate IC die 101, [0010] IC dies 101 and 102 may include circuitry that is typically located in a single IC die in a previously known FPGA), wherein the programmable logic fabric is part of the FPGA (Fig. 2, 231 is a part of 101); and
inter-die fabric extension connections (Fig. 2, 255) coupled at a first end directly to the fabric sliver and at a second end directly to the programmable logic fabric (Fig. 2, 255, [0024] router circuits 233, router circuits 231, die-to-die connection 255).
Regarding claim 3, all the limitations of claim 1 are taught by Weber.
Weber further teaches the system, wherein the second integrated circuit further comprises:
a second fabric sliver (Fig. 2, 221, [0013] 221, programmable interconnection circuit) containing the programmable logic fabric (Fig. 2, 221 contains 231), and
a second plurality of hardened IP blocks ([0015] 203 may include transceivers) comprising circuitry configured to communicate with the second fabric sliver (203, 205, 221 are within 101).
Regarding claim 4, all the limitations of claim 1 are taught by Weber.
Weber further teaches the system, wherein the plurality of hardened IP blocks are configured to use the fabric sliver and the inter-die fabric extension connections to communicate with the programmable logic fabric in the second integrated circuit ([0008] The circuitry in the first and second IC dies may communicate with each other).
Regarding claim 5, all the limitations of claim 1 are taught by Weber.
Weber further teaches the system, wherein the second integrated circuit further comprises a second NoC ([0014] 204 may include a NOC), the system further comprising:
NoC inter-die bridge connections ([0015] 204 may include die-to-die interface circuit that transmit signals to and receive signals from the base IC die 203) coupled at the first end to the first NoC and at the second end to the second NoC, wherein the plurality of hardened IP blocks are configured to use the first NoC, the NoC inter-die bridge connections, and the second NoC to access compute resources in the second integrated circuit ([0008] The circuitry in the first and second IC dies may communicate with each other).
Regarding claim 7, all the limitations of claim 1 are taught by Weber.
Weber further teaches the system, wherein at least one of the plurality of hardened IP blocks is configured to use the fabric sliver to communicate with the first NoC in the ASIC ([0008] The circuitry in the first and second IC dies may communicate with each other).
Regarding claim 8, all the limitations of claim 1 are taught by Weber.
Weber further teaches the system, wherein a first one of the plurality of hardened IP blocks is configured to use the fabric sliver to communicate with a second one of the plurality of hardened IP blocks ([0008] The circuitry in the first and second IC dies may communicate with each other).
Regarding claim 9, all the limitations of claim 1 are taught by Weber.
Weber further teaches the system, wherein further comprising: a chiplet disposed at a side of the second integrated circuit, wherein the plurality of hardened IP blocks in the ASIC is configured to access compute resources on the chiplet using the fabric sliver, the inter-die fabric extension connections, and the programmable logic fabric ([0012] 291-294).
Regarding claim 17, Weber teaches a system, comprising:
an application specific integrated circuit (ASIC) (Figs. 1 and 2, 102, [0010] base IC die 102) comprising:
a first network on chip (NOC) ([0023] NOC 241)
a fabric sliver comprising programmable logic circuitry ([0024] router circuits 233, [0023] 233 may be programmable), and
a plurality of hardened IP blocks comprising circuitry configured to communicate with the fabric sliver ([0010] non-programmable circuitry, e.g., processor);
a second integrated circuit separate from the ASIC ([0012] main IC die 101), the second integrated circuit comprising a programmable logic fabric ([0014] router circuits 231 that are programmable), wherein the second integrated circuit comprises a field programmable gate array (FPGA) ([0011] most or all of the programmable logic circuits in a separate IC die 101, [0010] IC dies 101 and 102 may include circuitry that is typically located in a single IC die in a previously known FPGA), wherein the programmable logic fabric is part of the FPGA (Fig. 2, 231 is a part of 101); and
inter-die fabric extension connections (Fig. 2, 255) coupled directly to both the fabric sliver and the programmable logic fabric (Fig. 2, 255, [0024] router circuits 233, router circuits 231, die-to-die connection 255), wherein the inter-die fabric extension connections extend the programmable logic fabric so that the programmable logic circuitry in the ASIC is part of the programmable logic in the second integrated circuit ([0008] a single integrated circuit die separated into two IC dies. Therefore, the programmable logic circuitry in 101 is part of the programmable logic fabric in 102).
Regarding claim 19, this claim has substantially the same subject matter as that in claim 3. Therefore, claim 19 is rejected under the same rationale as claim 3 above.
Regarding claim 20, this claim has substantially the same subject matter as that in claim 4. Therefore, claim 20 is rejected under the same rationale as claim 4 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Weber (US 2021/0313988 A1) in view of Li (WO 2017/164872 A1).
Regarding claim 6, all the limitations of claim 1 are taught by Weber.
Weber does not explicitly teach the system, wherein the programmable logic circuitry in the fabric sliver comprises Design for Test (DFT) and debug logic for testing an operation of at least one of the plurality of hardened IP blocks.
Li teaches a system wherein an FPGA comprises Design for Test (DFT) and debug logic for testing an operation of the FPGA (page 13, paragraphs 4, 7).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to include Li’s DFT and debug logic into Weber so that one can improve the reliability (Li, page 1, Background).
Claims 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Weber (US 2021/0313988 A1) in view of Laursen (US 2023/0023258 A1).
Regarding claim 10, all the limitations of claim 1 are taught by Weber.
Weber does not explicitly teach the system wherein the fabric sliver comprises serializers/deserializers (SERDES) coupled to the inter-die fabric extension connections, wherein a chip-to-chip (C2C) interface clock for operating the SERDES is independent of a clock for operating logic circuit in the fabric sliver.
Laursen teaches a system wherein a serializer/deserializer (SERDES) is used in high speed chip-to-chip communication with clock data recovery functionality ([0016]).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to apply Laursen’s SERDES to Weber’s die-to-die interface fabric in order to minimize the number of IO interconnect (Laursen, [0016]) and resulting SERDES is independent of a clock for operating logic circuit in the fabric sliver as the SERDES uses clock recovery function.
Regarding claim 11, all the limitations of claim 10 are taught by Weber in view of Laursen.
Laursen further teaches the system, wherein a wire delay corresponding to the C2C interface is less than a system clock period (SERDES by definition is a serialization of data wherein data sampling is performed. Any wire delay in the data path should be less than the sampling clock to perform sampling properly).
Regarding claim 12, all the limitations of claim 10 are taught by Weber in view of Laursen.
Laursen further teaches the system, wherein the fabric sliver comprises a plurality of SERDES, each of which is an independent unit relative to the other SERDES for timing purposes ([0130] PHY SerDes; [0132] PCS/FEC SerDes).
Allowable Subject Matter
Claims 13, 14 and 16 are allowed. Specifically, the independent claim 13 is allowed over the prior arts. The dependent claims 14 and 16 are allowed due to their dependencies to the said independent claim 13.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 13, the prior arts fail to teach or reasonably suggest a system, comprising an application specific integrated circuit (ASIC) comprising a hardened chip-to-chip (C2C) interface, a field programmable gate array (FPGA) separate from the ASIC; and NoC inter-die bridge connections coupled at the first end to the first NoC and at the second end to the second NoC, wherein the plurality of hardened IP blocks are configured to use the first NoC, the NoC inter-die bridge connections, and the second NoC to access compute resources in the FPGA, in combination with the other limitations of the claim.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEOKJIN KIM whose telephone number is (571)272-1487. The examiner can normally be reached M-F: 8:30am-5:00pm.
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/SEOKJIN KIM/Primary Examiner, Art Unit 2844