Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 07/15/2026 under 37 CFR 1.131 has been considered but is ineffective to overcome the cited references below as shown below.
DETAILED ACTION
This action is responsive to application No. 18123402 filed on 03/20/2023.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 4-5, 10-11, 14, 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim et al. (US 2024/0258245).
Regarding Independent claim 1, Kim et al. teach a microelectronic package (this is an intended use recitation that does not structurally distinguish over prior art) comprising:
PNG
media_image1.png
628
846
media_image1.png
Greyscale
a substrate (Fig. 1A, element 102, paragraph 0018);
a first die (Fig. 1A, element 106, paragraph 0018) and a second die (Fig. 1A, element 106, paragraph 0018) attached to the substrate (Fig. 2, paragraph 0018 discloses dies 106 attached by die attach material 108 or substrate 102); and
a dielectric structure (Fig. 1A, element 120, paragraph 0022) including at least one electrical wiring (Fig. 1A, element 116, paragraph 0018) electrically connecting the first die to the second die,
wherein the at least one electrical wiring includes first portions extending in a vertical direction and a second portion connecting the first portions and extending in a horizontal direction (see annotated figure above).
Regarding claim 4, Kim et al. teach wherein the dielectric structure connects the first die and the second die, and the dielectric structure is formed between the first and second dies in the horizontal direction and is formed between the first die and the substrate in the vertical direction (Fig. 1A).
Regarding claim 5, Kim et al. teach wherein the first die and the second die are between the at least one electrical wiring and the substrate in the vertical direction (Fig. 1A).
Regarding claim 10, Kim et al. teach wherein a separation area between the first die and the second die is filled with a dielectric material of the dielectric structure (Fig. 1A, element 120).
Regarding Independent claim 11, Kim et al. teach a method of manufacturing a microelectronic package, the method comprising:
PNG
media_image1.png
628
846
media_image1.png
Greyscale
attaching (Fig. 2, paragraph 0018 discloses dies 106 attached by die attach material 108 or substrate 102) a first die (Fig. 1A, element 106, paragraph 0018) and a second die (Fig. 1A, element 106, paragraph 0018) to a substrate (Fig. 1A, element 102, paragraph 0018); and
forming a dielectric structure (Fig. 1A, element 120, paragraph 0022) including at least one electrical wiring (Fig. 1A, element 116, paragraph 0018) that electrically connects the first die to the second die.
wherein the at least one electrical wiring includes first portions extending in a vertical direction and a second portion connecting the first portions and extending in a horizontal direction (see annotated figure above).
Regarding claim 14, Kim et al. teach further comprising forming the dielectric structure between the first and second dies in the horizontal direction and between the first die and the substrate in the vertical direction (Fig. 1A).
Regarding claim 20, Kim et al. teach further comprising filling a separation area between the first die and the second die with a dielectric material of the dielectric structure (Fig. 1A, element 120).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 12 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2024/0258245) in view of Arrington et al. (US 2024/0312865).
Regarding claim 2, Kim et al. teach all of the limitations as discussed above.
Kim et al. do not explicitly disclose wherein the dielectric structure comprises at least one dielectric material selected from the group consisting of SiO.sub.2, SiN, SiCN, a polymer, an epoxy, and an organic material.
Before the effective filling date of the invention it would have been obvious to one having ordinary skill in the art to select a known epoxy material for a mold compound as shown by Arrington et al. in paragraph 0071, since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. In re Leshin, 125 USPQ 416.
Regarding claim 12, Kim et al. teach all of the limitations as discussed above.
Kim et al. do not explicitly disclose wherein the dielectric structure comprises at least one dielectric material selected from the group consisting of SiO.sub.2, SiN, SiCN, a polymer, an epoxy, and an organic material.
Before the effective filling date of the invention it would have been obvious to one having ordinary skill in the art to select a known epoxy material for a mold compound as shown by Arrington et al. in paragraph 0071, since it has been held to be within the general skill of a worker in the art to select a known material on the base of its suitability, for its intended use involves only ordinary skill in the art. In re Leshin, 125 USPQ 416.
Claims 3, 13, 15 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2024/0258245) in view of Lan et al. (US 2023/0197554).
Regarding claim 3, Kim et al. teach all of the limitations as discussed above.
Kim et al. do not explicitly disclose wherein the at least one electrical wiring includes at least one through-dielectric via that comprises Cu.
Lan et al. teach a packaging device comprising electrical wiring includes at least one through-dielectric via that comprises Cu (Figs. 1-2, element 142, paragraph 0035) connecting two dies (Figs. 1-2, elements Die-1 & Die-2, paragraph 0035).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Kim et al. according to the teachings of Lan et al. with the motivation to an interconnection with improved electrical conductivity.
Regarding claim 13, Kim et al. teach all of the limitations as discussed above.
Kim et al. do not explicitly disclose wherein the at least one electrical wiring includes at least one through-dielectric via that comprises Cu.
Lan et al. teach a packaging device comprising electrical wiring includes at least one through-dielectric via that comprises Cu (Figs. 1-2, element 142, paragraph 0035) connecting two dies (Figs. 1-2, elements Die-1 & Die-2, paragraph 0035).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Kim et al. according to the teachings of Lan et al. with the motivation to an interconnection with improved electrical conductivity.
Regarding claim 15, Kim et al. modified by Lan et al. teach further comprising forming the first die and the second die between the at least one through-dielectric via and the substrate in the vertical direction (Fig. 1 of Lan).
Claims 6-7, 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2024/0258245) in view of Darmawikarta et al. (US 2024/0006284).
Regarding claim 6, Kim et al. teach further comprising a lid (Fig. 1A, element 118, paragraph 0019) attached to the substrate.
Kim et al. do not explicitly disclose the lid covering the entire dielectric structure, the first die and the second die.
Darmawikarta et al. teach a semiconductor device comprising the lid (Fig. 1, element 112, paragraph 0023) covering the entire dielectric structure (Fig. 1, element 110, paragraph 0023), the first die (Fig. 1, element 108, paragraph 0023) and the second die (Fig. 1, element 106, paragraph 0023).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Kim et al. according to the teachings of Darmawikarta et al. with the motivation to provide protection.
Regarding claim 7, Kim et al. teach wherein the dielectric structure is formed between the first and second dies in the horizontal direction (Fig. 1A of Kim).
Regarding claim 16, Kim et al. teach further comprising attaching a lid (Fig. 1A, element 118, paragraph 0019) to the substrate.
Kim et al. do not explicitly disclose further comprising attaching a lid to the substrate, the lid covering the entire dielectric structure, the first die and the second die.
Darmawikarta et al. teach a semiconductor device comprising the lid (Fig. 1, element 112, paragraph 0023) covering the entire dielectric structure (Fig. 1, element 110, paragraph 0023), the first die (Fig. 1, element 108, paragraph 0023) and the second die (Fig. 1, element 106, paragraph 0023).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Kim et al. according to the teachings of Darmawikarta et al. with the motivation to provide protection.
Regarding claim 17, Kim et al. teach further comprising forming the dielectric structure between the first and second dies in the horizontal direction (Fig. 1A of Kim).
Claims 8, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2024/0258245) in view of Tseng et al. (US 2022/0059498).
Regarding claim 8, Kim et al. teach all of the limitations as discussed above.
Kim et al. do not explicitly disclose wherein at least one of the first die and the second die includes a through-chip via that connects to the at least one electrical wiring.
Tseng et al. teach a packaging device comprising wherein at least one of the first die (Fig. 1, element 120a, paragraph 0027) and the second die (Fig. 1, element 130a, paragraph 0027) includes a through-chip via (Fig. 1, elements 124 & 134, paragraph 0032) that connects to the at least one electrical wiring (Fig. 1, element 140a, paragraph 0027).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Kim et al. according to the teachings of Lan et al. with the motivation to an interconnection between chips.
Regarding claim 18, Kim et al. teach all of the limitations as discussed above.
Kim et al. do not explicitly disclose further comprising forming a through-chip via in at least one of the first die and the second die, the through-chip via connected to the at least one electrical wiring.
Tseng et al. teach a packaging device comprising wherein at least one of the first die (Fig. 1, element 120a, paragraph 0027) and the second die (Fig. 1, element 130a, paragraph 0027) includes a through-chip via (Fig. 1, elements 124 & 134, paragraph 0032) that connects to the at least one electrical wiring (Fig. 1, element 140a, paragraph 0027).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Kim et al. according to the teachings of Lan et al. with the motivation to an interconnection between chips.
Claims 9, 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2024/0258245) in view of Pfister et al. (US 2024/0118508).
Regarding claim 9, Kim et al. teach all of the limitations as discussed above.
Kim et al. do not explicitly disclose wherein the first die and the second die are separated by at least 10 μm.
Pfister et al. disclose a semiconductor device comprising a die pitch with 100 μm (paragraph 0128).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Kim et al. according to the teachings of Pfister et al. with the motivation to increase the number of devices (paragraph 0127).
Regarding claim 19, Kim et al. teach all of the limitations as discussed above.
Kim et al. do not explicitly disclose wherein the first die and the second die are separated by at least 10 μm.
Pfister et al. disclose a semiconductor device comprising a die pitch with 100 μm (paragraph 0128).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to modify the teachings of Kim et al. according to the teachings of Pfister et al. with the motivation to increase the number of devices (paragraph 0127).
Cited Prior Art
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant.
Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAHED AHMED whose telephone number is (571)272-3477. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached on 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SHAHED AHMED/Primary Examiner, Art Unit 2813
Prosecution Insights