DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The Information Disclosure Statement (IDS) submitted on 10/22/2025, 11/13/2025, and 01/14/2026 are in compliance with provisions of 37 CFR 1.97. Accordingly, the information disclosure is being considered by the Examiner.
Response to Amendment
The amendment with respect to claim(s) 1, 15, 20, and 22-24, filed on 01/09/2026 have been fully considered for examination based on their merits. The original claims, 2-13, 16-19, 21, and 25 have been considered. Claim 14 is canceled by the Applicant.
Response to Arguments
Applicant’s arguments, see Remarks, pages 8-10, filed 01/09/2026, with respect to the rejection(s) of claim(s) 1-25 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of LI.
Regarding Independent Claim(s) 1, and 20. Applicant argues (see Remarks, page 9), that the prior art, LAI in view of AZMAT does not disclose or suggest the amended claim features, now recites, “wherein each backside power island…second device track…lower portion having a second width…greater than the first width.” Examiner agrees that the arguments are persuasive and therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made as mentioned in the above paragraph. For instance, the prior art LI teaches in paragraphs [0038-0039] and in the drawings, Figures, 1A-2A, a semiconductor structure (100) comprising: wherein each backside power island (112/114, rails) located in the first device track and the second device track (105/107, PMOS/NMOS) has an upper portion having a first width and a lower portion having a second width that is greater than the first width ([0038-0039]).
Regarding Claims 2-13, 15-19, and 21-25: The dependent claims 2-13, 15-19, and 21-25 follow similar arguments as Claim 1, upon further consideration, a new-grounds of rejection is made based on the prior-art mentioned.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-13, and 15-25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chih-Yu Lai et al, (hereinafter LAI), US 20230067311 A1, in view of Raheel Azmat, (hereinafter AZMAT), US 20170352650 A1, and further in view of Xia Li et al, (hereinafter LI), US 20220013522 A1.
Regarding Claim 1, LAI teaches in Figures 1A and 9A-9B, a semiconductor structure (Fig. 1A, 100, an inverter circuit IC structure, [0026]) comprising:
backside power islands (Figs. 1A-1B/9A-9B, 142B/BPN, side power node/back-side power nodes, [0030], [0062]) located in both a first device track (Fig. 9B, C11/C12/C13, circuit cells, [0063]) and a second device track (Fig. 9B, C21, circuit cells, [0063]), wherein each backside power island (Figs. 1A-1B/9A-9B, 142B/BPN, side power node/back-side power nodes, [0030], [0062]) located in the first device track (Fig. 9B, C11/C12/C13, circuit cells, [0063]) and the second device track (Fig. 9B, C21, circuit cells, [0063]) and is isolated by a first cut region (Figs. 9A-9B, Y-direction), and the backside power islands (Figs. 1A-1B/9A-9B, 142B/BPN, side power node/back-side power nodes, [0030], [0062]) located in the first device track (Fig. 9B, C11/C12/C13, circuit cells, [0063]) are separated from the backside power islands (Figs. 1A-1B/9A-9B, 142B/BPN, side power node/back-side power nodes, [0030], [0062]) located in the second device track (Fig. 9B, C21, circuit cells, [0063]) by a second cut region (Figs. 9A-9B, X-direction), and further wherein the second cut region (Figs. 9A-9B, X-direction) is oriented perpendicular (Figs. 9A-9B, X and Y- directions are perpendicular) to the first cut region (Figs. 9A-9B, Y-direction).
LAI does not explicitly disclose a semiconductor structure comprising: wherein each backside power island located in the first device track and the second device track has an upper portion having a first width and a lower portion having a second width that is greater than the first width.
LI teaches a semiconductor structure (Figs. 1A/2A, 100, semiconductor device) comprising: wherein each backside power island (Figs. 1A/2A, 112/114, rails) located in the first device track (annotated Figure 2A) and the second device track (annotated Figure 2A) has an upper portion having a first width (annotated Figure 1A) and a lower portion having a second width (annotated Figure 1A) that is greater (annotated Figure 1A) than the first width (annotated Figure 1A).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified LAI to incorporate the teachings of LI, such that a semiconductor structure comprising: wherein each backside power island located in the first device track and the second device track has an upper portion having a first width and a lower portion having a second width that is greater than the first width, so that the output signal swings the full voltage between the low and high power rails, and therefore, this strong, more nearly symmetric response also makes CMOS more resistant to noise (LI, [0003]).
LAI as modified LI does not explicitly disclose or demonstrate, a semiconductor structure comprising: backside power islands located in both a first device track and a second device track.
AZMAT teaches in Figures 1-4, a semiconductor structure (Fig. 1, 100, integrated circuit) comprising: backside power islands (Fig. 1, PL, power line structure, [0031]) located in both a first device track and a second device track (Fig. 1, C1, at least six cells within the cell boundary, and the power line structures formed within the cell boundaries, CBL1 and CBL2, [0028-0031]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have LAI as modified by LI to incorporate the teachings of AZMAT, such that a semiconductor structure comprising: backside power islands located in both a first device track and a second device track, so that the at least one cell, C1 may include an active region (e.g. AR1 and AR2), the active region including a plurality of fins extending in a first direction on a substrate, 110 and being parallel to one another and thus all the components of the electronic systems are integrated in a single chip for enhancing the device performance (AZMAT, Figure 1, [0003], [0027]).
Regarding Claim 2, LAI as modified by LI and AZMAT, teaches the semiconductor structure of Claim 1.
LAI further teaches in Figures 1A and 9A-9B, the semiconductor structure (Fig. 1A, 100, an inverter circuit IC structure, [0026]), wherein each of the first device track (Fig. 9B, C11/C12/C13, circuit cells, [0063]) and the second device track (Fig. 9B, C21, circuit cells, [0063]) comprises p-type field effect transistors (Fig. 1A, p-type active-region semiconductor structure, 80p at a channel region of a PMOS transistor, [0026]) and n-type field effect transistors (Fig. 1A, n-type active-region semiconductor structure, 80n at a channel region of a NMOS transistor, [0026]) arranged in rows and columns (Fig. 1A, X-Y direction).
AZMAT further teaches the semiconductor structure (Fig. 1, 100, integrated circuit) of, wherein each of the first device track and the second device track (Fig. 1, C1, cell, [0027]) comprises p-type field effect transistors (Fig. 1, AR2, active region 2, may be P-type impurity-doped regions, [0030]) and n-type field effect transistors (Fig. 1, AR1, active region 1, may be N-type impurity-doped regions, [0030]) arranged in rows and columns (Fig. 1, X-Y direction).
Regarding Claim 3, LAI as modified by LI and AZMAT, teaches the semiconductor structure of Claim 2.
LAI further teaches in Figures 1A and 9A-9B, the semiconductor structure (Fig. 1A, 100, an inverter circuit IC structure, [0026]), wherein the first cut region is located between each n-type field effect transistor (intersections between dummy gate conductor patterns, 210 and the layout pattern of the n-type active-region semiconductor structure, 80n for isolating the n-type active-region in the inverter circuit cell from the active-regions in the neighboring cells, [0036]) to p-type field effect transistor (Fig. 2A, intersections between dummy gate conductor patter, 210 and the layout pattern of the p-active region semiconductor structure, 80p for the isolating p-type active region in the inverter circuit cell, [0036]) pair present in the first device track (Figs. 2A, 200, inverter circuit cell, [0036]; Figs. 9B/10B, C11/C12/C13) and the second device track (Figs. 2A, 200, inverter circuit cell, [0036]; Figs. 9B/10B, C21).
Regarding Claim 4, LAI as modified by LI and AZMAT, teaches the semiconductor structure of Claim 1.
LAI further teaches in Figures 1A and 9A-9B, the semiconductor structure (Fig. 1A, 100, an inverter circuit IC structure, [0026]), wherein the backside power islands (Figs. 1A-1B/9A-9B, 142B/BPN, side power node/back-side power nodes, [0030], [0062]) in the first device track (Fig. 9B, C11/C12/C13, circuit cells, [0063]) have a first width (annotated Figure 9B) and the backside power islands in the second device track (Fig. 9B, C21, circuit cells, [0063]) have a second width (annotated Figure 9B), wherein the first width is less than the second width (annotated Figure 9B).
AZMAT further teaches the semiconductor structure (Fig. 1, 100, integrated circuit), , wherein the backside power islands (Fig. 1, PL, power line structure, [0031]) in the first device track (Fig. 1, C1, at least six cells within the cell boundary, and the power line structures formed within the cell boundaries, CBL1 and CBL2, [0028-0031] have a first width (the cell boundary CB may have a rectangular shape having a first width, CW1 along the first direction (or the X direction), [0028]).
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LI further teaches the semiconductor structure (Figs. 1A/2A, 100, semiconductor device), wherein the backside power islands (Figs. 1A/2A, 112/114, rails) in the second device track (annotated Figure 2A) have a second width (annotated Figure 1A), wherein the first width (annotated Figure 1A) is less than the second width (annotated Figure 1A).
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Regarding Claim 5, LAI as modified by LI and AZMAT, teaches the semiconductor structure of Claim 1.
LAI further teaches in Figures 1A and 9A-9B, the semiconductor structure (Fig. 1A, 100, an inverter circuit IC structure, [0026]), wherein the first device track (Fig. 9B, C11/C12/C13, circuit cells, [0063]) comprises first active areas each of which has a first width (annotated Figure 9B) and the second device track (Fig. 9B, C21, circuit cells, [0063]) comprises second active areas each of which has a second width (annotated Figure 9B) that is greater than the first width (annotated Figure 9B).
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Regarding Claim 6, LAI as modified by LI and AZMAT, teaches the semiconductor structure of Claim 1.
LAI further teaches in Figures 1A and 9A-9B, the semiconductor structure (Fig. 1A, 100, an inverter circuit IC structure, [0026]) of Claim 1, wherein the first cut region and the second cut region are both filled with a backside interconnect dielectric material layer (Fig. 8, step 820 of method 800, depositing a layer of dielectric material covering at least the first-type active region semiconductor structure; step 830 of method 800, fabricate a second-type active-region semiconductor structure atop the layer of dielectric material [0056]).
Regarding Claim 7, LAI as modified by LI and AZMAT, teaches the semiconductor structure of Claim 6.
LAI further teaches in Figures 1A and 9A-9B, the semiconductor structure (Fig. 1A, 100, an inverter circuit IC structure, [0026]), wherein the backside interconnect dielectric material layer in both the first cut region and the second cut region is in direct physical contact with a sidewall of at least one of the backside power islands (Figs. 2A/3A-3C, the p-type active-region semiconductor structure, 80p is fabricated atop the layer of dielectric material which is above the n-type active-region semiconductor structure, 80n; the dielectric material covers the active-regions of the power island that includes the sidewall, [0056]). .
AZMAT further teaches the semiconductor structure (Fig. 1, 100, integrated circuit), , wherein the backside interconnect dielectric material layer (Fig. 4, 124/126, 128, first/second/third insulating interlayer) in both the first cut region and the second cut region is in direct physical contact with a sidewall of at least one of the backside power islands (Fig. 4, 124/126/128, first/second/third insulating interlayer, may be formed on over the upper surfaces and side surfaces of the first signal lines, M1S, and surround side surfaces of the vias, V1S, [0048]).
Regarding Claim 8 LAI as modified by LI and AZMAT, teaches the semiconductor structure of Claim 6.
AZMAT further teaches the semiconductor structure (Fig. 1, 100, integrated circuit), wherein the backside interconnect dielectric material layer contacts a surface of a backside power distribution network (Fig. 4, the third insulating interlayer, 128 connect the second power line, M3P and the via, V2P may be placed to electrically connect the metal island, M2P and the second power line, M3P, [0074]).
Regarding Claim 9, LAI as modified by LI and AZMAT, teaches the semiconductor structure of Claim 8.
LAI further teaches in Figures 1A and 9A-9B, the semiconductor structure (Fig. 1A, 100, an inverter circuit IC structure, [0026]), wherein the backside power distribution network (Fig. 3A, 220B/240B, back-side signal lines/back-side conductive layer, [0037]), is connected to at least one of the backside power islands that are located in both the first device track and second device track (Figs. 9A/10A11A, each back-side power node, BPN in a circuit cells is adjacent to the second horizontal boundary, while the first horizontal boundary is adjacent to a back-side power rail, [0064]) by a metal via contact structure (Fig. 8, 890, forming back-side power rails, back0side signal lines, and back-side power node connected to a top-to-bottom viaconnector, after patterning the back-side metal layer, [0053]).
Regarding Claim 10, LAI as modified by LI and AZMAT, teaches the semiconductor structure of Claim 9.
AZMAT further teaches the semiconductor structure (Fig. 1, 100, integrated circuit), wherein the metal via contact structure comprises a diffusion barrier liner located along a sidewall and a bottom wall of an electrically conductive metal or electrically conductive metal alloy (the first and second contacts may have layered structures including a barrier layer and a conductive layer for wiring respectively; the barrier layer include for example TiN, TaN or a combination thereof, and the conductive layer of wiring may include for example, W, Cu and alloy thereof, or a combination thereof, [0038]).
Regarding Claim 11, LAI as modified by LI and AZMAT, teaches the semiconductor structure of Claim 8.
AZMAT further teaches the semiconductor structure (Fig. 1, 100, integrated circuit), wherein a first surface of each of the backside power islands (Fig. 4, PL, power line structure, [0031]) contacts a diffusion barrier layer the first and second contacts may have layered structures including a barrier layer and a conductive layer for wiring respectively; the barrier layer include for example TiN, TaN or a combination thereof, and the conductive layer of wiring may include for example, W, Cu and alloy thereof, or a combination thereof, [0038]), and a second surface of each of the backside power islands opposite the first surface contacts a hard mask layer, and wherein the first surface of each of the backside power islands is located further from the backside power distribution network (Fig. 3A, 220B/240B, back-side signal lines/back-side conductive layer, [0037]) than the second surface of each of the backside power islands.
Regarding Claim 12, LAI as modified by LI and AZMAT, teaches the semiconductor structure of Claim 1.
LAI further teaches in Figures 1A and 9A-9B, the semiconductor structure (Fig. 1A, 100, an inverter circuit IC structure, [0026]), wherein at least one of the backside power islands is electrically connected to a source/drain region of a p-type field effect transistor or an n-type field effect transistor (Figs. 1A/1B, power VTB connects power island, 142B to 132p, which is the source terminal of the PMOS transistor, [0027]) in at least one of the first device track (Fig. 9B, C11/C12/C13, circuit cells, [0063]) or the second device track (Fig. 9B, C21, circuit cells, [0063]) by a backside source/drain contact structure (Fig. 1A, 132p/132n, source conductive segment/drain conductive segment, [0027]).
Regarding Claim 13, LAI as modified by LI and AZMAT, teaches the semiconductor structure of Claim 1.
LAI further teaches in Figures 1A and 9A-9B, the semiconductor structure (Fig. 1A, 100, an inverter circuit IC structure, [0026]), wherein at least one source/drain region (Fig. 1A, 132p/132n, source conductive segment/drain conductive segment, [0027]) of either a p-type field effect transistor or an n-type field effect transistor (Fig. 3A, drain terminals of the PMOS transistor and the NMOS transistor, [0027]) in at least one of the first device track (Fig. 9B, C11/C12/C13, circuit cells, [0063]) or the second device track (Fig. 9B, C21, circuit cells, [0063]), second device track is electrically connected (Fig. 3A, drain terminals of the PMOS transistor and the NMOS transistor are conductively connected together by the conductive segment inter-connector, MDLI, the source terminal of the PMOS transistor is conductively connected to a front-side power rail, 20F through a front-side terminal via-connector, VD and the source terminal of the NMOS transistor is conductively connected to a back-side power rail, 20B through a back-side terminal via-connector, VB, [0027]) to a frontside back-end-of-the-line (BEOL) structure (Fig. 16, [0092]) by a frontside source/drain contact structure (Fig. 8, 800, process flow of method, [0055]).
Regarding Claim 15, LAI as modified by LI and AZMAT, teaches the semiconductor structure of Claim 13.
LAI further teaches in Figures 1A and 9A-9B, the semiconductor structure (Fig. 1A, 100, an inverter circuit IC structure, [0026]), wherein at least one source/drain region (Fig. 1A, 132p/132n, source conductive segment/drain conductive segment, [0027]) that is electrically connected to the frontside BEOL structure (Fig. 3A, drain terminals of the PMOS transistor and the NMOS transistor are conductively connected together by the conductive segment inter-connector, MDLI, the source terminal of the PMOS transistor is conductively connected to a front-side power rail, 20F through a front-side terminal via-connector, VD and the source terminal of the NMOS transistor is conductively connected to a back-side power rail, 20B through a back-side terminal via-connector, VB, [0027]) is located on a surface of a bottom dielectric isolation layer (Figs. 3A-3C, the p-type region semiconductor structure, 80p is fabricated atop the layer of dielectric material which is above the n-type active-region semiconductor structure, 80n; Figs. 1A/1B, 132p, which is the source is located on bottom dielectric isolation layer (e.g. the one between 132p and 142B), [0027], [0056]).
Regarding Claim 16, LAI as modified by LI and AZMAT, teaches the semiconductor structure of Claim 2.
LAI further teaches in Figures 1A and 9A-9B, the semiconductor structure (Fig. 1A, 100, an inverter circuit IC structure, [0026]), wherein the p-type field effect transistors (Fig. 1A, PMOS transistor, [0026) and the n-type field effect transistors (Fig. 1A, NMOS transistor, [0026) are nanosheet containing transistors (Fig. 1A, nano-sheet transistor, [0026]) comprising a gate structure wrapped around at least one semiconductor channel material nanosheet (Figs. 1A/2A, 150/250, gate-conductor, [0026-], [0033-0034], [0040-0041]).
Regarding Claim 17, LAI as modified by LI and AZMAT, teaches the semiconductor structure of Claim 1.
LAI further teaches in Figures 1A and 9A-9B, the semiconductor structure (Fig. 1A, 100, an inverter circuit IC structure, [0026]), further comprising a diffusion brake break point structure (Fig. 2A, isolation regions in the p-type active-region semiconductor structure, 80p for the isolating the p-type active region in the inverter circuit cell from the active-regions in the neighboring cells; similar case for isolation region, in the n-type active-region semiconductor structure, 80n, [0036]) separating the first device track (Fig. 9B, C11/C12/C13, circuit cells, [0063]) from the second device track (Fig. 9B, C21, circuit cells, [0063]), wherein the second cut region (Figs. 9A-9B, X-direction), is located beneath the diffusion brake break point structure.
Regarding Claim 18, LAI as modified by LI and AZMAT, teaches the semiconductor structure of Claim 17.
LAI further teaches in Figures 1A and 9A-9B, the semiconductor structure (Fig. 1A, 100, an inverter circuit IC structure, [0026]), wherein the diffusion break point structure (Fig. 2A, isolation regions in the p-type active-region semiconductor structure, 80p for the isolating the p-type active region in the inverter circuit cell from the active-regions in the neighboring cells; similar case for isolation region, in the n-type active-region semiconductor structure, 80n, [0036]) is composed of a dielectric material, and the diffusion break point structure extends into a backside interlayer dielectric material layer (the isolation region in the active-region semiconductor structures(80p or 80n) are created based on poly on oxide definition edge (PODE) technology or based on the continuous poly on oxide definition (CPODE) technology, [0036]).
Regarding Claim 19, LAI as modified by LI and AZMAT, teaches the semiconductor structure of Claim 18.
AZMAT further teaches the semiconductor structure (Fig. 1, 100, integrated circuit), wherein the backside interlayer dielectric material layer (Fig. 4, 124/126/128, first/second/third insulating interlayer, [0048])is located above each of the backside power islands (Fig. 4, 124/126/128, first/second/third insulating interlayer, may be formed on over the upper surfaces and side surfaces of the first signal lines, M1S, and surround side surfaces of the vias, V1S, [0048]).
Regarding Claim 20, LAI teaches in Figures 1A and 9A-9B, a semiconductor structure (Fig. 1A, 100, an inverter circuit IC structure, [0026]) comprising:
a first device track (Fig. 9B, C11/C12/C13, circuit cells, [0063]) located laterally adjacent to a second device track (Fig. 9B, C21, circuit cells, [0063]), wherein each of the first device track (Fig. 9B, C11/C12/C13, circuit cells, [0063]) and the second device track (Fig. 9B, C21, circuit cells, [0063]) comprises p-type field effect transistors (Fig. 1A, PMOS transistor) and n-type field effect transistors (Fig. 1A, NMOS transistor) arranged in rows and columns (Fig. 1A, X-Y direction);
a diffusion brake break point structure (Fig. 2A, isolation regions in the p-type active-region semiconductor structure, 80p for the isolating the p-type active region in the inverter circuit cell from the active-regions in the neighboring cells; similar case for isolation region, in the n-type active-region semiconductor structure, 80n, [0036]) separating the first device track (Fig. 9B, C11/C12/C13, circuit cells, [0063]) from the second device track (Fig. 9B, C21, circuit cells, [0063]); and
backside power islands located (Figs. 1A-1B/9A-9B, 142B/BPN, side power node/back-side power nodes, [0030], [0062]) in both the first device track (Figs. 2A, 200, inverter circuit cell, [0036]; Figs. 9B/10B, C11/C12/C13) and the second device track (Figs. 2A, 200, inverter circuit cell, [0036]; Figs. 9B/10B, C21), and are isolated by a first cut region (Figs. 9A-9B, Y-direction), and the backside power islands (Figs. 1A-1B/9A-9B, 142B/BPN, side power node/back-side power nodes, [0030], [0062]) located in the first device track (Fig. 9B, C11/C12/C13, circuit cells, [0063]) are separated from the backside power islands (Figs. 1A-1B/9A-9B, 142B/BPN, side power node/back-side power nodes, [0030], [0062]) located in the second device track (Fig. 9B, C21, circuit cells, [0063]) by a second cut region (Figs. 9A-9B, X-direction), and further wherein the second cut region (Figs. 9A-9B, X-direction) is located beneath the diffusion brake break point structure and is oriented perpendicular (Figs. 9A-9B, X and Y- directions are perpendicular)to the first cut region (Figs. 9A-9B, Y-direction).
LAI does not explicitly disclose a semiconductor structure comprising: wherein each backside power island located in the first device track and the second device track has an upper portion having a first width and a lower portion having a second width that is greater than the first width.
LI teaches a semiconductor structure (Figs. 1A/2A, 100, semiconductor device) comprising: wherein each backside power island (Figs. 1A/2A, 112/114, rails) located in the first device track (annotated Figure 2A) and the second device track (annotated Figure 2A) has an upper portion having a first width (annotated Figure 1A) and a lower portion having a second width (annotated Figure 1A) that is greater (annotated Figure 1A) than the first width (annotated Figure 1A).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have modified LAI to incorporate the teachings of LI, such that a semiconductor structure comprising: wherein each backside power island located in the first device track and the second device track has an upper portion having a first width and a lower portion having a second width that is greater than the first width, so that the output signal swings the full voltage between the low and high power rails, and therefore, this strong, more nearly symmetric response also makes CMOS more resistant to noise (LI, [0003]).
LAI as modified LI does not explicitly disclose or demonstrate, a semiconductor structure comprising: backside power islands located in both a first device track and a second device track.
AZMAT teaches in Figures 1-4, a semiconductor structure (Fig. 1, 100, integrated circuit) comprising: backside power islands (Fig. 1, PL, power line structure, [0031]) located in both a first device track and a second device track (Fig. 1, C1, at least six cells within the cell boundary, and the power line structures formed within the cell boundaries, CBL1 and CBL2, [0028-0031]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to have LAI as modified by LI to incorporate the teachings of AZMAT, such that a semiconductor structure comprising: backside power islands located in both a first device track and a second device track, so that the at least one cell, C1 may include an active region (e.g. AR1 and AR2), the active region including a plurality of fins extending in a first direction on a substrate, 110 and being parallel to one another and thus all the components of the electronic systems are integrated in a single chip for enhancing the device performance (AZMAT, Figure 1, [0003], [0027]).
Regarding Claim 21, LAI as modified by LI and AZMAT, teaches the semiconductor structure of Claim 20.
LAI further teaches in Figures 1A and 9A-9B, the semiconductor structure (Fig. 1A, 100, an inverter circuit IC structure, [0026]), wherein the first cut region is located between each n-type field effect transistor (intersections between dummy gate conductor patterns, 210 and the layout pattern of the n-type active-region semiconductor structure, 80n for isolating the n-type active-region in the inverter circuit cell from the active-regions in the neighboring cells, [0036]) to p-type field effect transistor (Fig. 2A, intersections between dummy gate conductor patter, 210 and the layout pattern of the p-active region semiconductor structure, 80p for the isolating p-type active region in the inverter circuit cell, [0036]) pair present in the first device track (Figs. 2A, 200, inverter circuit cell, [0036]; Figs. 9B/10B, C11/C12/C13) and the second device track (Figs. 2A, 200, inverter circuit cell, [0036]; Figs. 9B/10B, C21).
Regarding Claim 22, LAI as modified by LI and AZMAT, teaches the semiconductor structure of Claim 20.
LI further teaches the semiconductor structure (Figs. 1A/2A, 100, semiconductor device), wherein the backside power islands (Figs. 1A/2A, 112/114, rails) in the first device track (annotated Figure 2A) have a first device track width (annotated Figure 1A) and the backside power islands (Figs. 1A/2A, 112/114, rails) in the second device track (annotated Figure 2A) have a second device track width (annotated Figure 1A), wherein the first device track width (annotated Figure 1A) is less than the second device track width (annotated Figure 1A).
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Regarding Claim 23, LAI as modified by LI and AZMAT, teaches the semiconductor structure of Claim 20.
LAI further teaches in Figures 1A and 9A-9B, the semiconductor structure (Fig. 1A, 100, an inverter circuit IC structure, [0026]), wherein the first device track (Fig. 9B, C11/C12/C13, circuit cells, [0063]) comprises first active areas each of which has a first active area width (annotated Figure 9B) and the second device track (Fig. 9B, C21, circuit cells, [0063]) comprises second active areas each of which has a second active area width (annotated Figure 9B) that is greater than the first active area width (annotated Figure 9B).
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Regarding Claim 24, LAI as modified by LI and AZMAT, teaches the semiconductor structure of Claim 20.
LAI further teaches in Figures 1A and 9A-9B, the semiconductor structure (Fig. 1A, 100, an inverter circuit IC structure, [0026]), wherein the first cut region and the second cut region are both filled with a backside interconnect dielectric material layer (Fig. 8, step 820 of method 800, depositing a layer of dielectric material covering at least the first-type active region semiconductor structure; step 830 of method 800, fabricate a second-type active-region semiconductor structure atop the layer of dielectric material [0056]).
LI further teaches the semiconductor structure (Figs. 1A/2A, 100, semiconductor device), wherein the backside interconnect dielectric material layer (Fig. 1A, 120, oxide layers) directly contacts a sidewall of each of the backside power islands (Fig. 1A, 112/114, rails).
Regarding Claim 25, LAI as modified by LI and AZMAT, teaches the semiconductor structure of Claim 24.
LAI further teaches in Figures 1A and 9A-9B, the semiconductor structure (Fig. 1A, 100, an inverter circuit IC structure, [0026]), wherein the backside interconnect dielectric material layer in both the first cut region and the second cut region is in direct physical contact with a sidewall of at least one of the backside power islands (Figs. 2A/3A-3C, the p-type active-region semiconductor structure, 80p is fabricated atop the layer of dielectric material which is above the n-type active-region semiconductor structure, 80n; the dielectric material covers the active-regions of the power island that includes the sidewall, [0056]).
AZMAT further teaches the semiconductor structure (Fig. 1, 100, integrated circuit), , wherein the backside interconnect dielectric material layer (Fig. 4, 124/126, 128, first/second/third insulating interlayer) in both the first cut region and the second cut region is in direct physical contact with a sidewall of at least one of the backside power islands (Fig. 4, 124/126/128, first/second/third insulating interlayer, may be formed on over the upper surfaces and side surfaces of the first signal lines, M1S, and surround side surfaces of the vias, V1S, [0048]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20200135634 A1 – Figure 8
STATEMENT OF RELEVANCE – The formation of buried power rails (50) located at the same level as some portions of the semiconductor strips (30).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/SESHA SAIRAMAN SRINIVASAN/ Examiner, Art Unit 2817
/MARLON T FLETCHER/ Supervisory Primary Examiner, Art Unit 2817
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