DETAILED ACTION
This Office action is in response to the election filed 23 February 2026. Claims 1-20 are currently pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group I, claims 1-17, in the reply filed on 23 February 2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claims 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6-7, 9-15, and 17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2020/0211972 A1 to Min et al. (hereinafter “Min”).
Regarding independent claim 1, Min (Figs. 7-8) discloses a semiconductor package, comprising:
a film having a first surface 110a (Fig. 7 - layout view of surface 110a; ¶ 0084) and a second surface 110b (Fig. 8 - layout view of surface 110b; ¶ 0084), which are opposite to each other, and comprising a first connection region BR1 (Fig. 7; ¶ 0043) and a second connection region BR2 (Fig. 7; ¶ 0043), which are spaced apart from each other in a first direction (Y-direction, as labeled in Fig. 7);
first connection pads (including 144/244; ¶ 0042) disposed on the first connection region BR1 of the film;
second connection pads (including 164/264; ¶ 0042) disposed on the second connection region BR2 of the film; and
a semiconductor chip (Fig. 7 - disposed in CR, ¶ 0043) disposed on the first surface 110a of the film and between the first connection region BR1 and the second connection region BR2, wherein the semiconductor chip comprises:
input pads (including pads connected to 140; ¶ 0097) disposed on a first pad region PG1 (Fig. 7; ¶ 0051), wherein the first pad region is adjacent to the first connection region BR1;
first output pads (including 152) disposed on the first pad region PG1 (Fig. 7); and
second output pads (unlabeled in Fig. 7, pads in region including bottom row of pads of left chip 310, see Fig. 2 for labeled 310) disposed on a second pad region (Fig. 7 - region including bottom row of pads of left chip 310, labeled in Fig. 2) spaced apart from the first pad region PG1, and at least one of the first output pads 152 (¶ 0088) is electrically connected to a corresponding second connection pad 154 (¶ 0088) of the second connection pads through a first via 150v1 (¶ 0089) and a second via 150v2 (¶ 0089) penetrating the film (Figs. 7, 8).
Regarding claim 2, Min (Figs. 7-8) discloses the semiconductor package of claim 1, further comprising wires, wherein the wires comprise: first wires 140 (¶ 0097) connecting the input pads to the first connection pads (pads in BR1); second wires (including 160; ¶ 0099) connecting the first output pads to the second connection pads 164 (Fig. 7); and third wires connecting the second output pads (Fig. 7 - pads in bottom row of pads of left chip 310) to the second connection pads (pads in BR2), wherein at least one of the second wires (Fig. 8 - wire connecting 150v1 and 150v2; ¶ 0089) is provided on the second surface 110b of the film to electrically connect the first via 150v1 to the second via 150v2.
Regarding claim 3, Min (Figs. 7, 9) discloses the semiconductor package of claim 2, wherein the at least one of the second wires comprises: a first sub-wire 150a (Fig. 9; ¶ 0090) connecting the at least one of the first output pads 152 (Fig. 9, also see Fig. 7) to the first via 150v1; a second sub-wire 150b (Fig. 9; ¶ 0092) connecting the first via 150v1 to the second via 150v2; and a third sub-wire (Fig. 7, unlabeled; sub-wire between 150v2 and 154) connecting the second via 150v2 to the corresponding second connection pad 154, wherein the first sub-wire and the third sub-wire are disposed on the first surface of the film (Fig. 7, 9), and the second sub-wire 150b is disposed on the second surface of the film (Fig. 9).
Regarding claim 4, Min (Fig. 7) discloses the semiconductor package of claim 1, wherein the first pad region comprises output pad regions and an input pad region, the output pad regions (outer side regions of PG1, containing 2 pads on each side) are disposed at opposing sides of the input pad region (central region of PG1, containing 4 central pads), the first output pads (160 connected thereto) are disposed on the output pad region, and the input pads (140 connected thereto) are disposed on the input pad region (¶¶ 0097, 99).
Regarding claim 6, Min (Fig. 7) discloses the semiconductor package of claim 2, wherein the first wires 140 and the third wires (wires connecting pads in bottom row of left chip 310 to pads in BR2) are disposed on the first surface of the film (Fig. 7)
Regarding claim 7, Min (Fig. 7) discloses the semiconductor package of claim 2, wherein the first, second and third wires (140/160/wires connecting pads in bottom row of left chip to pads in BR2) are provided to electrically connect the semiconductor chip (in CR) to the first connection pads (in BR1) and to electrically connect the semiconductor chip (in CR) to the second connection pads (in BR2)(Fig. 7).
Regarding claim 9, Min (Fig. 7) discloses the semiconductor package of claim 2, wherein at least a portion of each of the first, second, and third wires (140/160/wires connecting pads in bottom row of left chip to pads in BR2) is overlapped with the semiconductor chip (Fig. 7).
Regarding claim 10, Min (Fig. 9) discloses the semiconductor package of claim 3, wherein at least a portion of the second sub-wire 150b is overlapped with the semiconductor chip 310 (Fig. 9).
Regarding claim 11, Min (Fig. 7) discloses the semiconductor package of claim 1, wherein the first via 150v1 is disposed between the semiconductor chip (disposed in CR) and the first connection region BR1, and the second via 150v2 is disposed between the semiconductor chip and the second connection region BR2 (Fig. 7 - 150v2 disposed between chip and bottom edge portion of BR2).
Regarding independent claim 12, Min (Figs. 7-8) disclose a semiconductor package, comprising:
a film substrate 110 having a first surface 110a (Fig. 7 - layout view of surface 110a; ¶ 0084) and a second surface 110b (Fig. 8 - layout view of surface 110b; ¶ 0084), which are opposite to each other, wherein the film substrate comprises first connection pads (Fig. 7 - including 144/244 in BR1; ¶ 0042), which are provided on the first surface and are spaced apart from each other in a first direction (X-direction), and second connection pads ((Fig. 7 - including 164/264 in BR2; ¶ 0042), which are spaced apart from the first connection pads in a second direction (Y-direction) crossing the first direction;
a semiconductor chip (Fig. 7 - disposed in CR, ¶ 0043) provided on the first surface and between the first connection pads and the second connection pads;
wires 140/150/160 (¶ 0085) connecting the semiconductor chip to the first connection pads (disposed in BR1) and the second connection pads (disposed in BR2);
first vias 150v1 (Fig. 7 - ¶ 0089) provided between the semiconductor chip (disposed in CR) and the first connection pads (disposed in BR1), wherein the first vias penetrate the film substrate (¶ 0091); and
second vias 150v2 provided between (electrically connected between chip and second connection pads) the semiconductor chip (disposed in CR) and the second connection pads (disposed in BR2), wherein the second vias 150v2 penetrate the film substrate (¶ 0092), wherein the semiconductor chip and the second connection pads (disposed in BR2) are electrically connected to each other through the first vias 150v1 (through wiring 150) and the second vias 150v2.
Regarding claim 13, Min (Figs. 7-8) discloses the semiconductor package of claim 12, wherein the semiconductor chip comprises: first output pads (including 162; ¶ 0099) provided on a bottom surface of the semiconductor chip (Fig. 9 - pads provided on bottom surface of chip 310) and spaced apart from each other in the first direction (Fig. 7 - X-direction); and second output pads (Fig. 7 - pads in bottom row of pads of left chip 310) provided on the bottom surface of the semiconductor chip (Fig. 9 - pads provided on bottom surface of chip 310) and spaced apart from the first output pads in the second direction (Fig. 7 - Y-direction); wherein the first output pads are closer to the first connection pads (in BR1) than the second output pads are, and the first output pads are electrically connected to the second connection pads (through wirings 160; ¶ 0099).
Regarding claim 14, Min (Figs. 7-8) discloses the semiconductor package of claim 13, wherein the first output pads (including 152) are electrically connected to the second connection pads (in BR2) through the first vias 150v1 and the second vias 150v2.
Regarding claim 15, Min (Figs. 7, 9) discloses the semiconductor package of claim 13, further comprising wires 150 connecting the first output pads (including 152) to the second connection pads (in BR2), wherein the wires comprise: first sub-wires 150a (Fig. 9; ¶ 0090) provided on the first surface of the film substrate to connect the first output pads to the first vias 150v1 (Fig. 9), respectively; second sub-wires 150b (Fig. 9; ¶ 0092) provided on the second surface of the film substrate to connect the first vias 150v1 to the second vias 150v2, respectively; and third sub-wires (unlabeled in Fig. 7 - sub-wire between 150v2 and 154) provided on the first surface of the film substrate to connect the second vias 150v2 to the second connection pads (in BR2), respectively (Fig. 7).
Regarding claim 17, Min (Figs. 7-8) discloses the semiconductor package of claim 13, wherein the semiconductor chip further comprises input pads (including 142; ¶ 0097) provided on the bottom surface thereof (see Fig. 11 - cross section along line C-C’, pads on bottom surface of chip 310), and the input pads (including 142) are electrically connected (¶ 0097; through wiring 140) to the first connection pads (in BR1; Fig. 7).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 5, 8, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Min.
Regarding claim 5, Min (Fig. 7) discloses the semiconductor package of claim 4, wherein the first connection pads (including 144/244) and the first output pads (160 connected thereto) are spaced apart from each other by a first width in the first direction (Y-direction; Fig. 7), each of the output pad regions (Fig. 7 - outer side regions of PG1, containing 2 pads on each side) has a second width in a second direction (X-direction) crossing the first direction (Fig. 7).
Min fails to expressly disclose the first width is smaller than or equal to the second width. However, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Here, the limitations “the first width is smaller than or equal to the second width” are considered mere dimensional limitations. The instant disclosure is silent as to a particular unobvious purpose, unexpected result, or criticality of the above dimensional limitations, and thus are found to be prima facie obvious.
Furthermore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the above relationship between the first width and second width, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F .2d 272, 205 USPQ 215 (CCPA 1980). Here, the first width and second width are considered result effective variables because they affect the size and footprint of the semiconductor package. Thus the ordinary artisan would have been motivated to modify the first width and the second width for the purpose of adjusting the semiconductor package size and footprint to meet design requirements.
Regarding claim 8, Min discloses the semiconductor package of claim 2, however fails to expressly disclose further comprising at least one fourth wire, wherein the fourth wire is provided to connect a corresponding one of the first connection pads to a corresponding one of the second connection pads.
Min discloses various wiring configurations of semiconductor packages, see Figs. 7-8, 14-21, in order to provide high-integration density interconnection for semiconductor chips (¶¶ 0002-03). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to provide wirings to connect a corresponding one of the first connection pads to a corresponding one of the second connection pads, since to do so would have been within the ordinary capabilities of one skilled in the art, and for the purpose of forming desired connections in an art recognized way, or providing electrical contacts in a desired package location.
Regarding claim 16, Min (Figs. 7-8) discloses the semiconductor package of claim 13, wherein the first output pads (including 152) are provided in a first output pad region (Fig. 7 - outer right side region of PG1 of left chip) and a second output pad region (Fig. 7 - outer left side region of PG1 of left chip), which are spaced apart from each other on the bottom surface of the semiconductor chip (Figs. 7, 9 - showing pads on bottom surface of chip 310), the first output pads are spaced apart from the first connection pads (in BR1) by a first width in the second direction (Fig. 7 - Y-direction), each of the first and second output pad regions has a second width in the first direction (Fig. 7 - X-direction).
Min fails to expressly disclose: the first width is smaller than or equal to the second width. However, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). Here, the limitations “the first width is smaller than or equal to the second width” are considered mere dimensional limitations. The instant disclosure is silent as to a particular unobvious purpose, unexpected result, or criticality of the above dimensional limitations, and thus are found to be prima facie obvious.
Furthermore, it would have been obvious to one of ordinary skill in the art at the time the invention was made to provide the above relationship between the first width and second width, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F .2d 272, 205 USPQ 215 (CCPA 1980). Here, the first width and second width are considered result effective variables because they affect the size and footprint of the semiconductor package. Thus the ordinary artisan would have been motivated to modify the first width and second width for the purpose of adjusting the semiconductor package size and footprint to meet design requirements.
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US 2016/0351155 A1 to Park et al. disclosing a chip on film package; US 2019/0122943 A1 to Lim et al. disclosing a film for package substrate.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Candice Y. Chan whose telephone number is (571)272-9013. The examiner can normally be reached 8:30 am - 5 pm ET.
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CANDICE Y. CHAN
Examiner
Art Unit 2813
4 April 2026
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
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