Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-12 have been considered but are moot because the new ground of rejection below.
Claim Rejections - 35 USC § 102/Claim Rejections - 35 USC § 103
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 7, 8, 11 and 12 is/are rejected under 35 U.S.C. 102(a1) as anticipated by Li et al (US RE 48407) or, in the alternative, under 35 U.S.C. 103 as obvious over Li et al (US RE 48407) in view of Chou (US 2015/0214431).
Li et al. (US RE 48407 also published as US Patent 8,951,430 on 2/10/15) disclose etched (title, metal assisted chemical etching (MACE)) light emitting diode (LED) structures [col. 7 lines 57-67] comprising heterostructure [col. 7 lines 58-67 and col. 8 lines 1-5] micropillars (1000nm = 1 mm) on a substrate [col. 5 lines 60-68-col. Line 1] each heterostructure micropillar comprising a stack of semiconductor layers separated by heterojunctions [col. 7 lines 57-67] (“the p-type III-V semiconductor can be p-GaAs, the n-type III-V semiconductor can be n-GaAs, and the SI-type III-V semiconductor can be …InGaAs”) wherein sidewalls of the heterostructure micropillars are completely or substantially devoid of ion-induced defects, and wherein the sidewalls of the heterostructure micropillars have an etched surface roughness in a range from 1 nm to 40 nm (the examiner submits the Li et al. would result in “sidewalls of the heterostructure micropillars are completely or substantially devoid of ion-induced defects, and wherein the sidewalls of the heterostructure micropillars have an etched surface roughness in a range from 1 nm to 40 nm” because it discloses the same structure (heterojunction) and produced by the same method (metal assisted chemical etching[Li et al. 2019/0019901 [0031] discloses the structure formed by Macetch (i.e. MACE) would be devoid of ion induced damage] ). MPEP 2112.01 I discloses “[w]here the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977)”.
Ad arguendo, Li et al fails to explicitly disclose the sidewalls of the heterostructure micropillars have an etched surface roughness in a range from 1 nm to 40 nm.
Chou disclose the roughened sidewalls have by controlling a roughness less than 600
nm.
Li and Chou disclose the claimed invention except for an etched surface roughness in a range from 1 nm to 40 nm. It would have been obvious to one of ordinary skill in the art at the time the invention was made to form an etched surface roughness in a range from 1 nm to 40 nm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In Re Aller, 105 USPQ 233.
The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
One of ordinary skill in the art could have combined the elements as claimed by known methods (ie controlling the roughness on a sidewall), and that in combination, each element merely performs the same function as it does separately.
One of ordinary skill in the art would have recognized that the results of the combination were predictable (one could lessen the roughness on a sidewall).
Regarding claim 7, Li et al. disclose each of the heterostructure micropillars includes from 3 of the semiconductor layers [col. 7 lines 57-67] (“the p-type III-V semiconductor can be p-GaAs, the n-type III-V semiconductor can be n-GaAs, and the SI-type III-V semiconductor can be …InGaAs”).
Regarding claim 8, Li et al. disclose each heterostructure micropillar has maximum width or diameter in a range from about 1 mm [col. 7 lines 58-67 and col. 8 lines 1-5] ( micropillars (1000nm = 1 mm)).
Regarding claim 11, Li et al. disclose a semiconductor substrate (n-GaAs)[col. 8 lines 42-48].
Regarding claim 12, Li et al. disclose an LED structure [col. 7 lines 57-67] (“the p-type III-V semiconductor can be p-GaAs, the n-type III-V semiconductor can be n-GaAs, and the SI-type III-V semiconductor can be …InGaAs”).
Claim(s) 2-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al (US RE 48407) in view of Chou (US 2015/0214431) as applied to claim 1 above and further in view of Li et al. (US 2019/0019901) (will be referred to as Li 2019).
Li (RE 48407) and Chou disclose the invention supra.
Li (RE 48407) and Chou fail to explicitly disclose some or all of the semiconductor layers comprise wide-bandgap semiconductor layers having a bandgap above about 3 eV (claim 2) the semiconductor layers include two or more group III-nitride semiconductors (claim 3) the two or more group III- nitride semiconductors comprise gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN) (claim 4) each of the heterostructure micropillars comprises a range of bandgaps (claim 5).
Li 2019 disclose some or all of the semiconductor layers comprise wide-bandgap semiconductor layers having a bandgap above about 3 eV (GaN)[0031] the semiconductor layers include two or more group III-nitride semiconductors (GaN, InGaN) [0031] the two or more group III- nitride semiconductors comprise gallium nitride (GaN, InGaN)[0031], aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN) (claim 4)[0031] each of the heterostructure micropillars comprises a range of bandgaps (claim 5)[0031].
The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
One of ordinary skill in the art could have combined the elements as claimed by known methods (ie forming the heterostructure by using GaN and InGaN and AlGaN), and that in combination, each element merely performs the same function as it does separately.
One of ordinary skill in the art would have recognized that the results of the combination were predictable (one could tailor the bandgap of the structure using different compositions of the heterostructure).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al (US RE 48407) in view of Chou (US 2015/0214431)as applied to claim 1 above in view of Jain et al. (US 2017/0236975).
Li (RE 48407) and Chou disclose the invention supra.
Li (RE 48407) and Chou fail to disclose from 100 to 600,000 heterostructure micropillars are arranged in an array on the substrate.
Jain disclose the heterostructure include one or more multiple quantum wells [0043].
The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
One of ordinary skill in the art could have combined the elements as claimed by known methods (making quantum wells), and that in combination, each element merely performs the same function as it does separately.
One of ordinary skill in the art would have recognized that the results of the combination were predictable (the quantum wells would serve as the active region).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al (US RE 48407) in view of Chou (US 2015/0214431)as applied to claim 1 above in view of Jain et al. (US 2017/0236975).
Li (RE 48407) and Chou disclose the invention supra.
Li (RE 48407) and Chou fail to disclose from 100 to 600,000 heterostructure micropillars are arranged in an array on the substrate.
Jain disclose arrays of hundreds of nano wires [0023].
The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
One of ordinary skill in the art could have combined the elements as claimed by known methods (making an array of nanowires), and that in combination, each element merely performs the same function as it does separately.
One of ordinary skill in the art would have recognized that the results of the combination were predictable (an array would be formed).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al (US RE 48407) in view of Chou (US 2015/0214431)as applied to claim 1 above in view of Jain et al. (US 2017/0236975).
Li (RE 48407) and Chou disclose the invention supra.
Li (RE 48407) and Chou fail to disclose from 100 to 600,000 heterostructure micropillars are arranged in an array on the substrate.
Jain disclose the heterostructure is configured to emit visible light [0040].
The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference.
One of ordinary skill in the art could have combined the elements as claimed by known methods (making and LED emit visible light), and that in combination, each element merely performs the same function as it does separately.
One of ordinary skill in the art would have recognized that the results of the combination were predictable (the LED would emit visible light).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY K SMITH whose telephone number is (571)272-1884. The examiner can normally be reached Monday-Friday, 10am-6pm.
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/BRADLEY SMITH/Primary Examiner, Art Unit 2817