DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
RE: the rejection of claim 25 under 35 USC 112(b), Applicant’s amendments and arguments have been fully considered and overcome the issues of indefiniteness. Accordingly, the rejection of claim 25 under 35 USC 112(b) is withdrawn.
RE: the rejection of claims 20-21, 23-24 under 35 USC 103, Applicant argues According to pending claim 20, a plurality of first openings in the electrically insulative frame expose part of the first structured metal frame or part of the second structured metal frame at opposing first and second sidewalls of the electrically insulative frame. A sidewall is a wall that forms the side of something.1
However, the term side is defined as “a line or surface forming a border or face of an object,” see definition 3b by Merriam-Webster available at https://www.merriam-webster.com/dictionary/side, accessed on April 4, 2026. Accordingly, under a broad reasonable interpretation, the term “sidewall” is interpreted as a wall that forms a surface or face of an object.
Applicant further argues As is plainly shown in Figures 2A-2B of the Grant reference, none of the opposing sidewalls of frame 14 include openings that expose part of lead 28 (the alleged first structured frame) or lead 30 (the alleged second structured frame). Instead, leads 28 and 30 vertically protrude through the same central wall of frame 14 to enable lead contact.
However, as shown in Annotated FIG. 2A below, sidewalls of openings for leads 28 or 30 in molded frame 14 are opposing, these sidewalls form surfaces or faces of the frame 14; at these sidewalls, leads 28, 30 are exposed. In other words, each lead 28,30 is exposed through an opening in molded frame 14, and this opening is defined at least by an upper sidewall of 14 or lower sidewall of 14 as shown in Annotated FIG. 2A below.
Applicant argues In the context of the present application, the electrically insulative frame has sidewalls and each sidewall is a wall that forms a side of the frame. For example, in Figure 1A of the present application, electrically insulative frame 100 has four (4) sides2 and each side is formed by a sidewall. In Figure 1A, first and second sidewalls 140 and 142 of electrically insulative frame 100 form opposite sides of the frame and have openings 138, 144 that expose part 112a, 112b, 114a, 114b, of the structured metal frames 112, 114 embedded in the frame 100.3
However, Examiner notes Though understanding the claim language may be aided by explanations contained in the written description, it is important not to import into a claim limitations that are not part of the claim. For example, a particular embodiment appearing in the written description may not be read into a claim when the claim language is broader than the embodiment, see MPEP 2111.
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Annotated FIG. 2A of Grant
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 20-21, 23-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over US20060290689A1 to Grant et al. (hereinafter “Grant”) in view of US 20090140403 A1 to Lim et al. (hereinafter “Lim”).
RE: Claim 20, Grant discloses A power semiconductor module (power module in FIGs. 2A-2B and 3, [0011]-[0013]), comprising:
a frame (14);
a half bridge circuit housed in the frame and comprising one or more high-side power semiconductor dies and one or more low-side power semiconductor dies (a power module according to the preferred embodiment of the present invention includes a single phase half-bridge circuit 10, which preferably includes four parallel-connected high side MOS-gated semiconductor switches Qh1, Qh2, Qh3, Qh4, and a plurality of parallel connected low side MOS-gated semiconductor switches Ql1, Ql2, Ql3, Ql4, [0015]; Substrate 16 includes a conductive pad 34 for electrically and mechanically receiving (by a conductive adhesive such as solder or the like) the collector electrodes of the low side IGBTs, and the node electrodes of high side diodes, while substrate 18 includes conductive pad 36 for electrically and mechanically receiving (by a conductive adhesive such as solder or the like) the collector electrodes of the high side IGBTs, and the cathode electrodes of the high side diodes, [0018]; substrates 16, and 18 are molded in frame 14, [0018]; Accordingly, the substrates form at least part of the half-bridge circuit and are housed in 14 in FIG. 2B);
a first structured frame (28 in FIG. 2B which shows 28 is a B+ terminal; FIG. 2A shows two leads 28) embedded in the frame and electrically connected to a drain or collector terminal of the one or more high-side power semiconductor dies (B+ bus bar 20, B− bus bar 22, and leads 26 are embedded (molded in) frame 14, [0018]; each B+ bus 20, B− bus 22, and output bus 24 includes a respective lead 28, 30, 32, [0018]; high side IGBTs are connected to the B+ terminal at the collector electrode thereof, [0016]);
a second structured frame (30 in FIG. 2B which shows 30 is a B- terminal; FIG. 2A shows two leads 30) embedded in the frame and electrically connected to a source or emitter terminal of the one or more low-side power semiconductor dies (low side IGBTs are connected to the B− terminal at the emitter electrode thereof, [0016]); and
a plurality of first openings (openings in 14 through which 28, 30 extend; FIG. 2B shows vertical lines in 14 extending from 28, 30 to regions labelled 20, 22; these vertical lines are considered to outline 28, 30 extending through openings in 14) in the frame that expose part of the first structured frame or part of the second structured frame at opposing first and second sidewalls of the frame (sidewalls of openings for 28 or 30 are opposing; at these sidewalls, 28, 30 are exposed).
Grant does not explicitly disclose 14 is an electrically insulative frame.
However, Grant discloses frame 14 is made from a suitable molding plastic, [0021].
In the same field of endeavor, Lim discloses encapsulation material 30 includes epoxy, cross-linked or cross-linkable polymer, plastic, resin, or other electrically insulating material suited for molding, [0022]. Accordingly, plastic is considered an electrically insulating material.
Alternatively, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use an electrically insulating material suited for molding for frame 14 as taught by Lim to prevent short-circuiting.
Grant does not explicitly disclose that leads 28, 30 are metal.
However, Lim discloses Suitable materials for leads 26 include copper, alloys of copper, and other conductive materials, [0020]. Accordingly, before the effective filing date of the claimed invention, there was a need to select a material for leads 28,30 in Grant.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use copper for the leads 28, 30 as this would have been obvious to try since copper is one solution for material in leads taught by Lim and this would have had a reasonable expectation of success, see MPEP 2143. Further, using copper would ensure leads 28, 30 are conductive.
RE: Claim 21, modified Grant discloses The power semiconductor module of claim 20, further comprising:
a first busbar (20 or 22 below 28, 30) attached to the part of the first structured metal frame or the part of the second structured metal frame exposed by the plurality of first openings in the electrically insulative frame.
RE: Claim 23, modified Grant discloses The power semiconductor module of claim 21, wherein the plurality of first openings in the electrically insulative frame expose part of the first structured metal frame at the opposing first and second sidewalls of the electrically insulative frame (FIG. 2A shows a plurality of leads 28, accordingly, a plurality of openings in 14 expose leads 28), and wherein the first busbar electrically interconnects the drain or collector terminal of the one or more high-side power semiconductor dies (20 is a B+ bus, [0018]; high side IGBTs are connected to the B+ terminal at the collector electrode thereof, [0016]).
RE: Claim 24, modified Grant discloses The power semiconductor module of claim 23, further comprising:
a plurality of second openings in the electrically insulative frame that expose part of the second structured metal frame at the opposing first and second sidewalls of the electrically insulative frame (FIG. 2A shows a plurality of leads 30, accordingly, a plurality of openings in 14 expose leads 30); and
a second busbar (22 under 30 in FIG. 2B) attached to the part of the second structured metal frame exposed by the plurality of second openings in the electrically insulative frame, wherein the second busbar electrically interconnects the source or emitter terminal of the one or more low-side power semiconductor dies (20 is a B- bus, [0018]; low side IGBTs are connected to the B− terminal at the emitter electrode thereof, [0016]).
Allowable Subject Matter
The following is an examiner’s statement of reasons for allowance:
Claims 1-19, 26-28 are allowable.
Claims 22, 25 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The prior art of record, either individually or in combination, fails to disclose the limitations of claim 1 or 26.
In particular, the prior art of record fails to disclose a first structured metal frame embedded in the electrically insulative frame and electrically connected to a drain or collector terminal of the one or more high-side power semiconductor dies of each half bridge circuit; a second structured metal frame embedded in the electrically insulative frame and electrically connected to a source or emitter terminal of the one or more low-side power semiconductor dies of each half bridge circuit; and a plurality of first openings in the electrically insulative frame that expose part of the first structured metal frame or part of the second structured metal frame at opposing first and second sidewalls of the electrically insulative frame and between adjacent ones of the half bridge circuits as required by claims 1 and 26.
The reference Grant discloses a power module including a single phase half-bridge circuit 10, which preferably includes four parallel-connected high side MOS-gated semiconductor switches Qh1, Qh2, Qh3, Qh4, and a plurality of parallel connected low side MOS-gated semiconductor switches Ql1, Ql2, Ql3, Ql4, [0015]. Accordingly, Grant discloses a single half-bridge circuit and therefore fails to disclose a plurality of first openings in the electrically insulative frame that expose part of the first structured metal frame or part of the second structured metal frame at opposing first and second sidewalls of the electrically insulative frame and between adjacent ones of the half bridge circuits as required by the claims.
The reference Lim discloses an electronic device 20 according to one embodiment. Electronic device 20 includes a leadframe 22, a chip 24 attached to leadframe 22, leads 26 electrically connected to chip 24 by connectors 28, and encapsulation material 30 disposed over leadframe 22, chip 24, and a portion of leads 26, [0018]. However, no half bridge circuits are disclosed by Lim and therefore Lim fails to disclose a plurality of first openings in the electrically insulative frame that expose part of the first structured metal frame or part of the second structured metal frame at opposing first and second sidewalls of the electrically insulative frame and between adjacent ones of the half bridge circuits as required by the claims.
US20210104957A1 (Naeve) discloses a multiphase inverter circuit 10. The multiphase inverter circuit 10 comprises a plurality of half bridge circuits 11, 12, 13, one for each phase, [0035]. Naeve discloses each half bridge circuit 36, 37, 38 may be positioned laterally adjacent one another on the first surface 33 of the substrate 31. In these embodiments, neighbouring half bridge circuits may be mounted on and electrically coupled to a common voltage bus, [0056]. The leadframe 90 as well as the side faces and first surface 63 of the transistor device 60 are embedded in an insulating material 73, [0097]. However, Naeve fails to disclose another leadframe that is embedded in the same insulating material structure as the leadframe 90 and therefore fails to disclose a first structured metal frame embedded in an electrically insulative frame and electrically connected to a drain or collector terminal of the one or more high-side power semiconductor dies of each half bridge circuit; a second structured metal frame embedded in the electrically insulative frame and electrically connected to a source or emitter terminal of the one or more low-side power semiconductor dies of each half bridge circuit as required by the claims.
US20240007015A1 (Weis) discloses a single-phase module 1, [0028]. In the embodiment represented in FIG. 1, three half-bridges, i.e. 2×3 semiconductor packages 4 are provided. In the embodiment represented in FIG. 2, four half-bridges, i.e. 2×4 semiconductor packages 4 are provided, [0028]. However, Weis fails to disclose a first structured metal frame embedded in an electrically insulative frame and electrically connected to a drain or collector terminal of the one or more high-side power semiconductor dies of each half bridge circuit; a second structured metal frame embedded in the electrically insulative frame and electrically connected to a source or emitter terminal of the one or more low-side power semiconductor dies of each half bridge circuit as required by the claims.
US20190157190A1 (Fuergut) discloses an array of semiconductor device packages 500 each including first and second package bodies 110 and 120, respectively. As shown in FIG. 5, the package bodies 110, 120 of each semiconductor device package 500 are separated by the spacing 140. The intermediate part 132 of the lead frame 130 is exposed from the first and second mold compounds 114, 124 within the spacing 140, [0074]. A semiconductor device package having two mold compounds 114, 124 (package bodies, e.g. a first package body 110 and a second package body 120) may comprise a half-bridge circuitry, wherein the first mold compound 114 (first package body 110) accommodates a low side (LS) switch of the half-bridge circuitry and the second mold compound 124 (second package body 120) accommodates a high side (HS) switch of the half-bridge circuitry, or vice versa, [0097]. However, Fuergut fails to disclose openings in 114 and 124 that are positioned between half bridge circuits and therefore fails to disclose a plurality of first openings in the electrically insulative frame that expose part of the first structured metal frame or part of the second structured metal frame at opposing first and second sidewalls of the electrically insulative frame and between adjacent ones of the half bridge circuits as required by the claims.
US20090294936A1 (Liu) discloses The example shown in FIG. 1 has two P- channel mosfets 10, 12 and two N- channel mosfets 14, 16. However, those skilled in the art understand that a full bridge may be made with four N-channel or four P-channel mosfets. Examples of such bridges are included below. The P-channel mosfet 10 and the N-channel mosfet 14 are the low side of the bridge. The P-channel mosfet 12 and the N-channel mosfet 16 are the high side of the bridge. The drains of the low side mosfets are common as are the drains of the high side mosfets, [0035]. The mosfets 10, 12, 14, 16 are mounted between two lead frames, 30, 40 shown in detail in FIGS. 3-6, [0036]. Howevever, Liu fails to disclose half-bridge circuits and therefore fails to disclose a first structured metal frame embedded in an electrically insulative frame and electrically connected to a drain or collector terminal of the one or more high-side power semiconductor dies of each half bridge circuit; a second structured metal frame embedded in the electrically insulative frame and electrically connected to a source or emitter terminal of the one or more low-side power semiconductor dies of each half bridge circuit as required by the claims.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ANGUIANO whose telephone number is (703)756-1226. The examiner can normally be reached Monday through Friday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached on (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHAEL ANGUIANO/Examiner, Art Unit 2899
/DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899