DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is the initial Office Action based on the application filed 03/21/2023. Claims 1-20 are presented for examination and have been considered below.
Response to Arguments
Applicant’s arguments, filed 07/29/2025, with respect to the rejection of claims 1-10, 19 and 20, have been fully considered but are moot in view of the new ground of rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-7, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Nadeau-Dostie et al., (US 2010/0037109 A1) (“Nadeau-Dostie”), in view of Nguyen et al., (US 7,907,461 B1) (“Nguyen”).
Claim 1: Nadeau-Dostie teaches an apparatus comprising:
a first flip-flop circuit coupled to a data input terminal of a memory circuit (e.g., Nadeau-Dostie teaches input scannable memory elements 18 which apply test data through the input logic to the data inputs of memory 12, and expressly states that the scannable memory elements include flip-flops. Nadeau-Dostie also teaches bypass mechanism 44 having respective scannable flip-flops 46 associated with the memory data inputs. See ¶¶ [0006], [0010]. Nadeau-Dostie further describes memory data inputs as being controllable by scannable memory elements in their fan-in. See ¶ [0019]);
a second flip-flop circuit coupled to a clock terminal of the memory circuit (e.g., Nadeau-Dostie teaches that bypass flip-flops 46 are: “clocked on the same edge of the clock, CK, which clocks the memory. ”See ¶ [0010]. Nadeau-Dostie further states that the observation flip-flops are clocked on the same edge as the memory. See ¶ [0011].Thus, clock CK constitutes a common signal path/node coupled to a clock terminal of the flip-flop circuitry and to the clock terminal of memory 12. The claim merely requires the flip-flop circuit to be “coupled to” the clock terminal of the memory and does not require that an output of the flip-flop directly drive the memory clock terminal.);
a third flip-flop circuit coupled to an output terminal of the memory circuit (e.g., Nadeau-Dostie teaches that the data outputs of memory 12 are applied to output logic 16 and thereafter to output scannable memory elements 20, which include flip-flops. See ¶ [0006]. Nadeau-Dostie further teaches an output timing test in which resulting memory data is captured by output scan chain 20. See ¶ [0013].);
a fourth flip-flop circuit coupled to an enable terminal of the memory circuit (e.g., Nadeau-Dostie expressly provides scannable observation logic 50 for the control input of memory 12, specifically identifying the control as, for example, the write-enable input, and states that the observation logic is implemented as scannable flip-flops. See ¶ [0011]. In the Fig. 6 embodiment, retiming element 84 is associated with the write-enable path. Nadeau-Dostie further states that the output of write-enable selector 38 is applied to a retiming memory element whose output is applied to observation scannable memory element 50. See ¶¶ [0051], [0054]-[0055].).
Not explicitly taught by Nadeau-Dostie is:
an enable delay generator coupled to the fourth flip-flop circuit and the memory circuit, the enable delay generator to receive an enable signal and delay the enable signal to generate a delayed enable signal; and
a reference delay generator coupled to a clock terminal of the first flip-flop circuit, a clock terminal of the second flip-flop circuit, a clock terminal of the third flip-flop circuit, and a clock terminal of the fourth flip-flop circuit.
However, Nguyen expressly teaches receiving a control signal and generating a delayed control signal and further teaches that: “The control signal may be a set, reset, or enable signal.” See col. 11, approximately ll. 35-36; Fig. 11. Thus, Nguyen expressly teaches delaying an enable signal to produce a delayed enable signal. Nguyen’s Fig. 6 additionally teaches a complex flip-flop including Clock Enable CE together with delay circuits in its signal paths and explains that implementation of Clock Enable in the protected circuitry protects against glitches on the Clock Enable signal. See cols. 7-8. Furthermore, Nguyen teaches receiving a reference clock signal and generating a delayed clock signal based on the reference clock signal. See col. 11; Fig. 11. Nguyen’s Fig. 9 further discloses a delay element in which an input signal, such as a clock signal, is passed through delay elements 902/904 and a desired delayed output is selected. The amount of clock delay may be selected or programmed. Nguyen expressly teaches that the delay block used to generate the delayed clock may be programmed to adjust the amount of delay and that non-programmable implementations may alternatively be used. Thus, Nguyen teaches the claimed reference-delay-generator concept.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to apply Nguyen’s known delay-generation technique to the corresponding clock and enable paths of Nadeau-Dostie’s clocked memory-interface circuitry to obtain Nguyen’s expressly taught transient/glitch-suppression benefit while selecting an appropriate delay consistent with the required circuit timing.
As per claim 19, the claimed features are rejected similarly to claim 1 above.
Claim 2: Nadeau-Dostie and Nguyen teach the apparatus of claim 1, further comprising: a data delay generator coupled to the first flip-flop circuit and the memory circuit, the data delay generator to receive a data input signal and delay the data input signal to generate a delayed data input signal. For instance, Nguyen teaches “generating a delayed clock signal based upon the reference clock signal” (col. 2, lines 50–54). Fig. 1 shows that delay element 128 produces CLK1 (delayed clock).
Claim 3: Nadeau-Dostie and Nguyen teach the apparatus of claim 2, but fail to teach that the data delay generator is to communicate the delayed data input signal to a data input terminal of the first flip- flop circuit and the data input terminal of the memory circuit. However, Nguyen teaches that delayed data signals (D1) applied to storage elements (FIG. 2) and data paths feeding latch inputs. Therefore, duplicating a signal to multiple destinations would have been a routine signal routing design choice to a POSITA before the effective filing date of the claimed invention.
As per claim 20, the claimed features are rejected similarly to claim 3 above.
Claim 4: Nadeau-Dostie and Nguyen teach the apparatus of claim 1, further comprising: a clock delay generator coupled to the second flip-flop circuit and the memory circuit, the clock delay generator to receive a memory clock signal and delay the memory clock signal to generate a delayed memory clock signal. For instance, Nguyen teaches generating a delayed clock signal based upon the reference clock signal (col. 2, lines 50–54).
Claim 5: Nadeau-Dostie and Nguyen teach the apparatus of claim 4, wherein the clock delay generator is to communicate the delayed memory clock signal to a data input terminal of the second flip-flop circuit and the clock terminal of the memory circuit. For instance, Nguyen expressly teaches a clock-generation/delay circuit that receives a reference clock and generates a delayed version of the clock. Nguyen further teaches a programmable/selectable delay element for generating a delayed clock signal. Nguyen explains that the amount of delay may be programmed to provide an appropriate delay between the reference and delayed clock signals. It would therefore have been obvious to employ Nguyen’s known clock-delay circuitry in Nadeau-Dostie’s memory clock path, thereby supplying the delayed memory-clock signal to the corresponding memory-clock interface circuitry, including the second flip-flop circuit and the clock terminal of the memory, to obtain Nguyen’s known transient/glitch-suppression benefit.
Claim 6: Nadeau-Dostie and Nguyen teach the apparatus of claim 1, wherein the output terminal of the memory circuit is coupled to a data input terminal of the third flip-flop circuit. However, Nadeau-Dostie discloses that memory data outputs are provided to output logic 16, whose output is supplied to output scannable memory elements 20. Nadeau-Dostie expressly states that the scannable memory elements comprise flip-flops. Nadeau-Dostie further teaches an output timing test in which data propagated through the memory is captured by the output scan-chain flip-flops. Thus, under the claimed “coupled” relationship, the memory output terminal is coupled through the disclosed output circuitry to the data input of the third/output-observation flip-flop.
Claim 7: Nadeau-Dostie and Nguyen teach the apparatus of claim 1, further comprising: a reference signal generator coupled to the reference delay generator, the reference delay generator to receive a reference signal generated by the reference signal generator and delay the reference signal to generate a synchronized clock signal. However, teaches a reference clock signal and delay circuitry generating synchronized clock signals. Furthermore, Nadeau-Dostie uses clock sources feeding delay circuits and sequential elements. Therefore, providing a reference signal generator is an obvious implementation detail and would have been within the knowledge of an artisan in the art. For instance, Nguyen teaches the missing delay function. Nguyen expressly receives a reference clock signal and generates a delayed clock signal based upon the reference clock signal. Nguyen’s Fig. 9 further teaches a programmable delay circuit receiving an input clock signal and selecting a desired delayed output after one or more delay elements. Thus, it would have been obvious to provide Nadeau-Dostie’s common reference-clock architecture with Nguyen’s reference-clock delay generator so that a reference clock generated by the clock source is delayed before distribution to the synchronized interface circuitry. The result would predictably provide the controlled delayed-clock functionality expressly taught by Nguyen while retaining Nadeau-Dostie’s synchronous memory-interface clock architecture.
Claim(s) 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Nadeau-Dostie and Nguyen as applied to claim 7 above, and further in view of Masleid et al (US 5,656,963)(“Masleid”).
Claim 8: Nadeau-Dostie and Nguyen teach the apparatus of claim 7, but fail to further teach comprising: a clock mesh coupled to the reference delay generator, the clock terminal of the first flip-flop circuit, the clock terminal of the second flip-flop circuit, and the clock terminal of the third flip-flop circuit. However, Masleid teaches a clock-distribution architecture combining an H-tree with an X-Y grid, i.e., a clock mesh/grid, to distribute a clock across an integrated circuit with low skew. The H-tree distributes the clock to final drivers and the final drivers are interconnected by the X-Y grid to distribute the clock to circuits on the chip (e.g. Abstract & Fig. 2). It would have been obvious to use this well-known low-skew mesh/grid distribution architecture to distribute the delayed/reference clock of the Nadeau-Dostie/Nguyen combination to the several flip-flops because Masleid expressly teaches the architecture for distributing a common clock to spatially distributed circuit elements while reducing clock skew.
Claim 9: Nadeau-Dostie, Nguyen and Masleid teach the apparatus of claim 8, but fail to teach that the clock mesh further comprising: a plurality of buffer pairs, the plurality of buffer pairs coupled to the reference delay generator via an H-tree network. However, H-tree networks are well-known clock distribution techniques and would have been within the knowledge of an artisan in the art. For instance, Masleid teaches an H-tree clock-distribution network having multiple levels of repower buffers. In particular, the H-tree has buffers at its branching/tip locations for transmitting the clock through successive levels to final drivers, after which the clock is distributed through the X-Y grid/mesh (e.g., Fig. 2).
Claim 10: Nadeau-Dostie, Nguyen and Masleid teach the apparatus of claim 9, wherein the clock mesh is to receive the synchronized clock signal via the H-tree network, and supply the synchronized clock signal to the clock terminal of the first flip-flop circuit, the clock terminal of the second flip-flop circuit, and the clock terminal of the third flip-flop circuit. For instance, Nadeau-Dostie distributes delayed clock signals across multiple latches. For instance, Nguyen teaches generating the delayed/reference clock signal and Nadeau-Dostie teaches supplying a common clock to the corresponding memory-interface flip-flops. Furthermore, Masleid teaches that the H-tree distributes the clock to final drivers and that the X-Y grid then distributes the clock to the circuits while reducing skew. Thus, upon applying Masleid’s known distribution network to the Nadeau-Dostie/Nguyen system, the synchronized clock generated by Nguyen’s reference delay generator would traverse the H-tree to the clock mesh and thereafter be supplied to the corresponding clock terminals of Nadeau-Dostie’s first, second, and third interface flip-flop circuits. The motivation would have been to provide a known low-skew, balanced clock-distribution structure for distributing the synchronized clock to multiple clocked elements, which is precisely the purpose for which Masleid teaches the H-tree/grid architecture.
Allowable Subject Matter
Claims 11-18 are allowed.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/GUERRIER MERANT/Primary Examiner, Art Unit 2111 8/25/2026
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