DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
Amended drawing submitted in Applicants Arguments /Remarks Made in an Amendment dated 12/18/2025 overcomes objections made in Non-Final Office Action mailed on 09/30/2025, therefore drawing objections made in Non-Final Office Action mailed on 09/30/2025 are withdrawn.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 17 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Regarding applicant’s argument that Miyairi ‘343 teaches a semiconductor device with one stacked channel, Examiner respectfully disagrees. Miyairi ‘343 discloses in Para [0205] oxide semiconductor 130A as a stack layer of two or more oxide semiconductors.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 7-8, 17-19 and 21 are rejected under 35 U.S.C. 103 as being unpatentable over Miyairi (US 2016/0233343 A1, hereinafter Miyairi ‘343) in view of Yamazaki et al. (US 2023/0326751 A1, hereinafter Yamazaki ‘751), in view of the following arguments.
With respect to Claim 1 Miyairi ‘343 discloses method for forming a semiconductor device (Fig 1A-1C and 6A-7C), comprising:
providing a substrate (101, Fig 1B, Para [0093]);
performing a first atomic layer deposition cycle (Para [0132] discloses an ALD process to form 130A) to form a first stacked channel layer (first channel layer of 130A, Fig 6A, Para [0132]) on the substrate (101);
performing a second atomic layer deposition cycle (Para [0205] discloses oxide semiconductor (130A per Para [0205]) “may be a stacked layer including two or more of an amorphous oxide semiconductor”, therefore a second ALD deposition cycle is used) to form a second stacked channel layer (second layer of 130A, Fig 6A, Para [0132], Para [0205] discloses 130A as a stacked layer) on the first stacked channel layer (first layer of 130A),
forming a gate dielectric layer (160A, Fig 6A, Para [0147]) on the second stacked channel layer (second channel layer of 130A)(Fig 6A discloses 160A on 130A), wherein the gate dielectric (160A) layer has a U-shaped cross-sectional profile (U-shaped cross sectional profile of 160A disclosed in Fig 6A); and
forming a gate structure (170/183, Fig 6D and 7C, Para [0153 and 0162]) on the gate dielectric layer (160A).
But Miyairi ‘343 fails to explicitly disclose a first atomic layer deposition cycle M times, a second atomic layer deposition cycle N times to form a second stacked channel layer, wherein M and N are positive integers, and a concentration of a metal composition of the second stacked channel layer is greater than a concentration of the metal composition of the first stacked channel layer.
Nevertheless, in a related endeavor (Fig 2 and 6A-23D of Yamazaki ‘751), Yamazaki ‘751 teaches a first atomic layer (230a, Fig 6A of Yamazaki ‘751, Par [0129]) deposition cycle M times (Fig 2 of Yamazaki ‘751 and Para [0110] discloses an ALD process and Fig 2 shows a loop to repeat the deposition cycle to achieve a desired thickness, therefore the cycle is conducted at least one time so M is ≥1), a second atomic layer (Para [0130] of Yamazaki ;751 discloses two or more layers in the stacked oxide semiconductor 230) deposition cycle N times (Fig 2 of Yamazaki ‘751 and Para [0110] discloses an ALD process and Fig 2 shows a loop to repeat the deposition cycle to achieve a desired thickness, therefore the cycle is conducted at least one time so N is ≥1) to form a second stacked channel layer (230b, Fig 6A of Yamazaki ‘751, Para [0129]), wherein M and N are positive integers (as described above M and N are integers ≥1), and a concentration of a metal composition of the second stacked channel layer (230b) is greater than a concentration of the metal composition of the first stacked channel layer (230a)(Para [0138] of Yamazaki ‘751 discloses “the region closer to the channel formation region preferably has a lower concentration of a metal element”, Fig 6B of Yamazaki ‘751 discloses layer 230a (first stacked channel layer) closer to the channel formation region (below 230a as 230a is grown via ALD on layer 224), therefore as 230b (second stacked channel layer) is higher than 230a, the concentration of metal composition of 230b is greater than the metal concentration of 230a).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Yamazaki ‘751’s teaching of a first atomic layer deposition cycle M times, a second atomic layer deposition cycle N times to form a second stacked channel layer, wherein M and N are positive integers, and a concentration of a metal composition of the second stacked channel layer is greater than a concentration of the metal composition of the first stacked channel layer into Miyairi ‘343’s method. Miyairi ‘343 teaches a semiconductor device with semiconductor oxide channel layers formed by ALD but is silent on the details of the ALD process to form the channel layers. Yamazaki ‘751 also teaches a semiconductor device with semiconductor oxide channel layers formed by ALD and provides details on the ALD process to deposit a thickness of multiple channel layers. The ordinary artisan would have been motivated, therefore, to modify Miyairi ‘343’s method in the manner set forth above, at least, because Yamazaki ‘751 teaches details of channel layers by ALD and these details provide the person of ordinary skill in the art details that improve the manufacturing process. Further Miyairi ‘343 is open to different impurity concentrations of the channel layers (evidenced by Para [0058]) and Yamazaki ‘751 teaches that having a higher metal concentration in the second channel layer than the first, which provides a different band gap in those layers, can reduce the off-state current of the transistor (Para [0140] of Yamazaki ‘751). Therefore the person of ordinary skill in the art would be motivated to use the teachings of Yamazaki ‘751 wherein the second channel layer has a higher metal concentration than the first channel layer to take advantage of the improved device performance in the off-state.
As incorporated, the ALD process, with a cycle repeated 1 or more times to achieve the desired thickness, to form channel layers, as taught by Yamazaki ‘751, would be used to form the first channel layer (first channel layer of 130A) and second channel layer (second channel layer of 130A) of Miyairi ‘343 and the concentration of a metal composition being higher in the second channel layer than the first channel layer, as taught by Yamazaki ‘751 would be used as the metal concentration of the first channel layer (first channel layer of 130A) and second channel layer (second channel layer of 130A) in the method of Miyairi ‘343.
With respect to Claim 2 Miyairi ‘343 as modified by Yamazaki ‘751 discloses all limitations of the method for forming a semiconductor device according to claim 1,and Yamazaki ‘751 further teaches wherein a processing temperature of the second atomic layer deposition cycles (230b) is higher than a processing temperature of the first atomic layer deposition cycles (230a), (Para [0146] of Yamazaki ‘751 discloses a higher temp (400C to 600C) than the first cycle (200C to 300C as disclosed in Para [0113]) is used to create a dense metal oxide structure and Para [0161] discloses layer 230b has a denser structure than 230a, therefore the processing temperature of 230b is higher than the processing temperature of 230a).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Yamazaki ‘751’s further teaching of an ALD process of a processing temperature of the second atomic layer deposition cycles is higher than a processing temperature of the first atomic layer deposition cycles into Miyairi ‘343 as modified by Yamazaki ‘751’s method. The ordinary artisan would have been motivated to modify Miyairi ‘343 as modified by Yamazaki ‘751 in the manner set forth above, at least because, as Yamazaki ‘751 teaches in Para [0161], the higher process temperature of the second channel layer creates a denser structure which creates a more stable transistor device with respect to the high temperatures of the manufacturing process. Therefore a motivation exists to use a higher temperature in the second step ALD process improve device stability as it goes through the manufacturing process.
As incorporated, the ALD processing temperature increase between the first and second layer as taught by Yamazaki ‘751 would be used to form the first channel layer (first channel layer of 130A) and second channel layer (second channel layer of 130A) in the method of Miyairi ‘343.
With respect to Claim 3 Miyairi ‘343 as modified by Yamazaki ‘751 discloses all limitations of the method for forming a semiconductor device according to claim 1, and Miyairi ‘343 further discloses wherein the metal composition comprises indium (In) (Para [0134] discloses using In for the oxide semiconductor layer), the first stacked channel layer (first channel layer of 130A) comprises indium oxide (InO), gallium oxide(GaO), and zinc oxide (ZnO) (Para [0135] discloses oxide semiconductor layer 130A as one of Indium, Gallium and Zinc), the second stacked channel layer (second channel layer of 130A) comprises indium oxide (InO) (Para [0134] discloses using In for the oxide semiconductor layers 130A, as described above in Para [0205] 130A comprises stacked channel layers).
With respect to Claim 7 Miyairi ‘343 as modified by Yamazaki ‘751 discloses all limitations of the method for forming a semiconductor device according to claim 1, and Miyairi ‘343 further discloses wherein a material (gallium, Para [0134 and 0148] disclose that layers 160A and 130A both contain gallium. In addition they discloses they both contain zinc) of component layers (layers of 160A) of the second stacked channel layer (160A) and a material of a bottom-most component layer (layer of 130A) of the first stacked channel layer (130A) are the same (gallium, Para [0134 and 0148] disclose that layers 160A and 130A both contain gallium. In addition they discloses they both contain zinc).
With respect to Claim 8 Miyairi ‘343 as modified by Yamazaki ‘751 discloses all limitations of the method for forming a semiconductor device according to claim1, and Miyairi ‘343 discloses further comprising:
forming a source structure (150, Fig 7B of Miyairi ‘343, Para [0074], Para [0019] discloses structure as source if 140 is a drain) and a drain structure (140, Fig 5C of Miyairi ‘343, Para [0074], Para [0019] discloses structure as a drain if 150 is a source) on the substrate (101); and
forming the first stacked channel layer (130A) on the substrate (101) and directly covering the source structure (150) and the drain structure (140)(Fig 7B of Miyairi ‘343 discloses 130A covering 140 and 150).
With respect to Claim 17 Miyairi ‘343 discloses a semiconductor device (Fig 1A-1C and 6A-7C), comprising:
a first stacked channel layer (first channel layer of 130A, Fig 6A, Para [0132]) comprising a first surface (top of first channel layer 130A as shown in Fig 6A) and a second surface (bottom of first channel layer 130A as shown in Fig 6A);
a first gate structure (170/183, Fig 6D and 7C, Para [0153 and 0162]) disposed on the first surface (top of first channel layer 130A as shown in Fig 6A) of the first stacked channel layer (first channel layer 130A);
a first gate dielectric layer (160A, Fig 6A, Para [0147]) disposed between the first gate structure (170/183) and the first stacked channel layer (first channel layer 130A), wherein the first gate dielectric layer has a U-shaped cross-sectional profile (U-shaped cross sectional profile of 160A disclosed in Fig 6A); and
a second stacked channel layer (second layer of 130A, Fig 6A, Para [0132], Para [0205] discloses 130A as a stacked layer) disposed between (disclosed in Fig 7C of Miyairi ‘343) the first gate dielectric layer (160A) and the first stacked channel layer (first channel layer 130A),
But Miyairi ‘343 fails to explicitly disclose wherein a concentration of a metal composition of the second stacked channel layer is greater than a concentration of the metal composition of the first stacked channel layer.
Nevertheless, in a related endeavor (Fig 2 and 6A-23D of Yamazaki ‘751), Yamazaki ‘751 teaches wherein a concentration of a metal composition of the second stacked channel layer (230b, Fig 6A of Yamazaki ‘751, Para [0129]) is greater than a concentration of the metal composition of the first stacked channel layer (230a, Fig 6A of Yamazaki ‘751, Par [0129]) (Para [0138] of Yamazaki ‘751 discloses “the region closer to the channel formation region preferably has a lower concentration of a metal element”, Fig 6B of Yamazaki ‘751 discloses layer 230a (first stacked channel layer) closer to the channel formation region (below 230a as 230a is grown via ALD on layer 224), therefore as 230b (second stacked channel layer) is higher than 230a, the concentration of metal composition of 230b is greater than the metal concentration of 230a).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Yamazaki ‘751’s teaching of a concentration of a metal composition of the second stacked channel layer is greater than a concentration of the metal composition of the first stacked channel layer into Miyairi ‘343’s method. Miyairi ‘343 teaches a semiconductor device with semiconductor oxide channel layers formed by ALD but is silent on the details of the ALD process to form the channel layers. Further Miyairi ‘343 is open to different impurity concentrations of the channel layers (evidenced by Para [0058]). Yamazaki ‘751 also teaches a semiconductor device with semiconductor oxide channel layers formed by ALD and provides details on the ALD process to deposit a thickness of multiple channel layers and Yamazaki ‘751 teaches that having a higher metal concentration in the second channel layer than the first, which provides a different band gap in those layers, can reduce the off-state current of the transistor (Para [0140] of Yamazaki ‘751). The ordinary artisan would have been motivated, therefore, to modify Miyairi ‘343’s method in the manner set forth above, at least, because Yamazaki ‘751 teaches wherein the second channel layer has a higher metal concentration than the first channel layer to take advantage of the improved device performance in the off-state.
As incorporated, the ALD process, as taught by Yamazaki ‘751, of the concentration of a metal composition being higher in the second channel layer than the first channel layer, as taught by Yamazaki ‘751 would be used as the metal concentration of the first channel layer (first channel layer of 130A) and second channel layer (second channel layer of 130A) in the method of Miyairi ‘343.
With respect to Claim 18 Miyairi ‘343 as modified by Yamazaki ‘751 discloses all limitations of the semiconductor device according to claim 17, Miyairi ‘343. further discloses wherein the metal composition comprises indium (In) (Para [0134] discloses using In for the oxide semiconductor layer), the first stacked channel layer (first channel layer of 130A) comprises indium oxide (InO), gallium oxide(GaO), and zinc oxide (ZnO) (Para [0135] discloses oxide semiconductor layer 130A as one of Indium, Gallium and Zinc), the second stacked channel layer (second channel layer of 130A) comprises indium oxide (InO) (Para [0134] discloses using In for the oxide semiconductor layers 130A, as described above in Para [0205] 130A comprises stacked channel layers).
With respect to Claim 19 Miyairi ‘343 as modified by Yamazaki ‘751 discloses all limitations of the semiconductor device according to claim 17, and Miyairi ‘343 further discloses a material (indium, Para [0134 and 0135] discloses that first channel layer of 130A and second channel layer of 130A both contain indium) of a component layer exposed from the second surface (bottom layer of first channel layer 130A) of the first stacked channel layer (first channel layer of 130A) and a material of component layers (components of second channel layers of 130A) of the second stacked channel layer (second channel layer of 130A, Para [0205] discloses oxide semiconductor (130A per Para [0205]) “may be a stacked layer including two or more of an amorphous oxide semiconductor”) are the same (indium, Para [0134 and 0135] discloses that first channel layer of 130A and second channel layer of 130A both contain indium).
With respect to Claim 21 Miyairi ‘343 discloses a semiconductor device (Fig 1A-1C and 5A-7C), comprising:
a substrate (101, Fig 1B, Para [0093]);
a drain structure (140, Fig 1B, Para [0074 and 0075]), an interlayer dielectric layer (120, Fig 1B, Para [0074]), and a source structure (150, Fig 1B, Para [0075 and 0075]) sequentially disposed (disclosed in Fig 1B) on the substrate (101);
an opening vertically extending through (Fig 1B discloses an opening (filled by structure 130 and 170 in Fig 1B) extending through 150) the source structure (150), the interlayer dielectric layer (120) and into the drain structure (140)(Fig 1B discloses an opening (filled by structure 130 and 170 in Fig 1B) extending through 150 and into drain 140);
a first stacked channel layer (first channel layer of 130A, Fig 6A, Para [0132]) disposed (shown in Fig 1B) on the source structure (150) and along sidewalls and bottom surface of the opening (Fig 1B discloses an opening (filled by structure 130 and 170 in Fig 1B) disposed on 150 and further shows first channel layer of 130A is disposed along sidewalls and bottom of the opening);
a first gate structure (170/183, Fig 1B, Para [0077 and 0078]) disposed on the first stacked channel layer (first channel layer of 130A);
a first gate dielectric layer (160A, Fig 6A, Para [0147]) disposed between (shown in Fig 1B) the first gate structure (170/183) and the first stacked channel layer (first channel layer of 130A, Fig 6A, Para [0132]), wherein a bottom surface (bottom of 160A) of the first gate dielectric layer (160A)(Fig 1B discloses a bottom surface of 160A is lower than a bottom surface of source structure 150) is lower than a bottom surface (bottom of 150) of the source structure (150) (Fig 1B discloses a bottom surface of 160A is lower than a bottom surface of source structure 150); and
a second stacked channel layer (second layer of 130A, Fig 6A, Para [0132], Para [0205] discloses 130A as a stacked layer) disposed between the first gate dielectric layer (160A) and the first stacked channel layer (first channel layer of 130A),
But Miyairi ‘343 fails to explicitly disclose wherein a concentration of a metal composition of the second stacked channel layer is greater than a concentration of the metal composition of the first stacked channel layer.
Nevertheless, in a related endeavor (Fig 2 and 6A-23D of Yamazaki ‘751), Yamazaki ‘751 teaches wherein a concentration of a metal composition of the second stacked channel layer (230b, Fig 6A of Yamazaki ‘751, Para [0129]) is greater than a concentration of the metal composition of the first stacked channel layer (230a, Fig 6A of Yamazaki ‘751, Par [0129]) (Para [0138] of Yamazaki ‘751 discloses “the region closer to the channel formation region preferably has a lower concentration of a metal element”, Fig 6B of Yamazaki ‘751 discloses layer 230a (first stacked channel layer) closer to the channel formation region (below 230a as 230a is grown via ALD on layer 224), therefore as 230b (second stacked channel layer) is higher than 230a, the concentration of metal composition of 230b is greater than the metal concentration of 230a).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Yamazaki ‘751’s teaching of a concentration of a metal composition of the second stacked channel layer is greater than a concentration of the metal composition of the first stacked channel layer into Miyairi ‘343’s method. Miyairi ‘343 teaches a semiconductor device with semiconductor oxide channel layers formed by ALD but is silent on the details of the ALD process to form the channel layers. Further Miyairi ‘343 is open to different impurity concentrations of the channel layers (evidenced by Para [0058]). Yamazaki ‘751 also teaches a semiconductor device with semiconductor oxide channel layers formed by ALD and provides details on the ALD process to deposit a thickness of multiple channel layers and Yamazaki ‘751 teaches that having a higher metal concentration in the second channel layer than the first, which provides a different band gap in those layers, can reduce the off-state current of the transistor (Para [0140] of Yamazaki ‘751). The ordinary artisan would have been motivated, therefore, to modify Miyairi ‘343’s method in the manner set forth above, at least, because Yamazaki ‘751 teaches wherein the second channel layer has a higher metal concentration than the first channel layer to take advantage of the improved device performance in the off-state.
As incorporated, the ALD process, as taught by Yamazaki ‘751, of the concentration of a metal composition being higher in the second channel layer than the first channel layer, as taught by Yamazaki ‘751 would be used as the metal concentration of the first channel layer (first channel layer of 130A) and second channel layer (second channel layer of 130A) in the method of Miyairi ‘343.
Claims 4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over Miyairi ‘343 in view of Yamazaki ‘751 in further view of Neishi (JP 2023-097610 A, hereinafter Neishi ‘610), in view of the following arguments.
With respect to Claim 4 Miyairi ‘343 as modified by Yamazaki ‘751 discloses all limitations of the method for forming a semiconductor device according to claim 1, and Miyairi ‘343 further discloses wherein the first atomic layer deposition cycle (Para [0132] discloses an ALD process to form 130A), the second atomic layer deposition cycle (Para [0147] discloses an ALD process to form 160A).
But Miyairi ‘343 as modified by Yamazaki ‘751 fails to explicitly disclose wherein the first atomic layer deposition cycle comprises contacting the substrate alternately with an indium precursor, a gallium precursor, a zinc precursor, and an oxygen reactant, the second atomic layer deposition cycle comprises contacting the substrate alternately with the indium precursor and the oxygen reactant.
Nevertheless, in a related endeavor (Figs 6-14 of Neishi ‘610), Neishi ‘610 teaches wherein the first atomic layer deposition cycle comprises contacting the substrate alternately (Para [0030] of Neishi ‘610 discloses a cycle to deposit films InOx followed by GaOx followed by ZnOx) with an indium precursor, a gallium precursor, a zinc precursor (Para [0030] of Neishi ‘610 discloses ALD formation of an InGaZnO film and Para [0037] of Neishi ‘610 further discloses In, Ga and Zn precursors), and an oxygen reactant (Para [0037] of Neishi ‘610 discloses the use of oxygen gas as an oxidizing agent in the ALD process of the InGaZnO film), the second atomic layer deposition cycle (Para [0063-0067] of Neishi ‘610 discloses an ALD process for forming InOx film) comprises contacting the substrate alternately (Para [0063-0067] of Neishi ‘610 disclose alternating In precursor and oxygen) with the indium precursor (Para [0063] of Neishi ‘610 discloses In precursor) and the oxygen reactant (Para [0065] of Neishi ‘610 discloses oxygen reactant).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Neishi ‘610’s the first atomic layer deposition cycle comprises contacting the substrate alternately with an indium precursor, a gallium precursor, a zinc precursor, and an oxygen reactant, the second atomic layer deposition cycle comprises contacting the substrate alternately with the indium precursor and the oxygen reactant into Miyairi ‘343 as modified by Yamazaki ‘751’s method. Miyairi ‘343 as modified by Yamazaki ‘751’s method teaches an ALD process to form oxide semiconductor channels using precursors, and in Para [0305] is open to the precursors used. Neishi ‘601 teaches an ALD method to form oxide semiconductor channels and teaches specific details on the precursors used. The ordinary artisan would have been motivated to modify Miyairi ‘343 as modified by Yamazaki ‘751 in the manner set forth above, at least because, as Neishi ‘610 teaches in Para [0006], the process presented forms a metal oxide film containing few impurities.
As incorporated, the use of the In, Ga and Zn precursors and oxygen deposited alternatively as taught by Neishi ‘610 would be used in the ALD process of Miyairi ‘343 as modified by Yamazaki ‘751.
With respect to Claim 6 Miyairi ‘343 as modified by Yamazaki ‘751 and further modified by Neishi ‘610 discloses all limitations of the method for forming a semiconductor device according to claim 4, and Neishi ‘610 further discloses wherein each of the first atomic layer deposition cycle (S1-S5, Fig 1 of Neishi ‘610, Para [0011]) comprises sequentially performing the following:
performing a first sub-cycle (S1-S4, Fig 1 of Neishi ‘610, Para [0012], Para [0025] disclose a first cycle of S1-S4 as ST1) m1 times (Para [0025] of Neishi ‘610 discloses steps S1-S4 can be repeated X times), wherein the first sub-cycle (ST1) comprises contacting the substrate (substrate of device disclosed in Para [0005] of Neishi ‘610) with the indium precursor (Para [0015] discloses an indium precursor in S1) and then with the oxygen reactant (Para [0016] discloses oxygen reactant in S3);
performing a second sub-cycle (S1-S4, Fig 1 of Neishi ‘610, Para [0012], Para [0025] discloses the cycle S1-S4 used for second stage ST2) m2 times (Para [0025] of Neishi ‘610 discloses steps S1-S4 can be repeated X times),wherein the second sub-cycle (ST2) comprises contacting the substrate (substrate of device disclosed in Para [0005] of Neishi ‘610)with the gallium precursor (Para [0015] discloses a gallium precursor in S1) and then with the oxygen reactant (Para [0016] discloses oxygen reactant in S3); and
performing a third sub-cycle (S1-S4, Fig 1 of Neishi ‘610, Para [0012], Para [0025] discloses the cycle S1-S4 used for second stage ST3) m3 times (Para [0025] of Neishi ‘610 discloses steps S1-S4 can be repeated X times), wherein the third sub-cycle (ST3) comprising contacting the substrate (substrate of device disclosed in Para [0005] of Neishi ‘610) with the zinc precursor (Para [0015] discloses a zinc precursor in S1) and then with the oxygen reactant (Para [0016] discloses oxygen reactant in S3), wherein ml, m2 and m3 are positive integers (Fig 1 of Neishi ‘610 discloses cycles as >1).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Miyairi ‘343 in view of Yamazaki ‘751, in view of Neishi ‘610 in view of Shenai-Khatkhate et al. (US 2006/0047132 A1, hereinafter Shenai-Khatkhate ‘132) and in further view of Jin et al. (KR 10-2023-0036190, hereinafter Jin ‘190), in view of the following arguments.
With respect to Claim 5 Miyairi ‘343 as modified by Yamazaki ‘751 and further modified by Neishi ‘610 discloses all limitations of the method for forming a semiconductor device according to claim 4, and Miyairi ‘343 as modified by Yamazaki ‘751 and further modified by Neishi ‘610 further discloses the oxygen reactant comprises oxygen. (Para [0065] of Neishi ‘610 discloses oxygen reactant)
But Miyairi ‘343 as modified by Yamazaki ‘751 and further modified by Neishi ‘610 fails to explicitly disclose wherein the indium precursor comprises [3-(dimethylamino) propyl] dimethyl indium (DADI), the gallium precursor comprises tri-methylgallium (TMGa), the zinc precursor comprises diethyl zinc.
Nevertheless in a related endeavor, (Para [0003] of Shenai-Khatkhate ‘132 discloses organometallic compounds for semiconductor devices), Shenai-Khatkhate ‘132 teaches wherein the gallium precursor comprises tri-methylgallium (TMGa) (Para [0046] of Shenai-Khatkhate ‘132 discloses a gallium precursor compound for ALD processes that includes tri-methylgallium (TMGa), the zinc precursor comprises diethyl zinc. (Para [0014] of Shenai-Khatkhate ‘132 discloses a zinc precursor comprises diethyl zinc).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Shenai-Khatkhate ‘132’s teaching wherein the gallium precursor comprises tri-methylgallium (TMGa), the zinc precursor comprises diethyl zinc into Miyairi ‘343 as modified by Yamazaki ‘751 and further modified by Neishi ‘610’s method. Shenai-Khatkhate ‘132 teaches precursors for organometallic compounds for ALD processes used for semiconductors. Therefore, the ordinary artisan would have been motivated to modify Miyairi ‘343 as modified by Yamazaki ‘751 and further modified by Neishi ‘610 in the manner set forth above, at least, as Shenai-Khatkhate ‘132 teaches in Para [0006], organometallic compounds formed by these precursors are “extremely pure”.
As incorporated, the use of the gallium precursor comprises tri-methylgallium (TMGa), the zinc precursor comprises diethyl zinc as taught by Shenai-Khatkhate ‘132 would be used as the precursors to form the gallium and zinc layers in the ALD process of Miyairi ‘343 as modified by Yamazaki ‘751 and further modified by Neishi ‘610.
But Miyairi ‘343 as modified by Yamazaki ‘751 as modified by Neishi ‘610 and further modified by Shenai-Khatkhate ‘132 fails to explicitly disclose wherein the indium precursor comprises [3-(dimethylamino) propyl] dimethyl indium (DADI).
Nevertheless, in a related endeavor (Para [0001] of Jin ‘190 discloses a process to create a IndiumGalliumZinc Oxide layer), Jin ‘190 teaches wherein the indium precursor comprises [3-(dimethylamino) propyl] dimethyl indium (DADI). (Para [0042] discloses a first material layer of Indium Oxide (210) is formed from a first precursor containing (3-Dimethylaminopropyl)dimethylindium (DADI)).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Jin ‘190’s teaching wherein the indium precursor comprises [3-(dimethylamino) propyl] dimethyl indium (DADI) into Miyairi ‘343 as modified by Yamazaki ‘751 and further modified by Neishi ‘610 and further modified by Shenai-Khatkhate ‘132’s device. Jin ‘190 teaches precursors for organometallic compounds for ALD processes used for semiconductors. Therefore, the ordinary artisan would have been motivated to modify Miyairi ‘343 as modified by Yamazaki ‘751 and further modified by Neishi ‘610 and further modified by Shenai-Khatkhate ‘132 in the manner set forth above, at least, as Jin ‘190 teaches in Para [0008], the process presented provides “improved thermal durability” in the semiconductor device.
As incorporated, the use of the indium precursor comprises [3-(dimethylamino) propyl] dimethyl indium (DADI)as taught by Jin ‘190 would be used as the precursor to form the indium oxide layer in the ALD process of Miyairi ‘343 as modified by Yamazaki ‘751 and further modified by Neishi ‘610 and further modified by Shenai-Khatkhate ‘132.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898