DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 11 and 12 is/are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by Takei (US. Pub: 2010/0200875 A1).
Regarding claim 1, Takei discloses (in at least fig. 1) a display apparatus comprising: a substrate (2); a pixel circuit (4; [0032]; fig. 1) disposed on the substrate; a planarization insulating layer (10) which is disposed on the pixel circuit and including a first structure in which an opening or a groove is defined (see at least fig. 1); a bank layer (14; [0037]) which is disposed on an upper surface of the planarization insulating layer (10) opposite to a lower surface of the planarization insulating layer facing the substrate and in which a first opening overlapping the first structure is defined (see fig. 1); and an intermediate layer (15; [0038]-[0040]) disposed in at least a portion of the first structure (i.e. the portion where item 15 is formed or located) and the first opening (see fig. 1), wherein the first opening is defined between portions of the bank layer (14) next to each other, and a maximum width of the first opening is greater than a maximum width of the first structure (see at least fig. 1).
Regarding claim 2, Takei discloses (in at least fig. 1) the first structure and the first opening are spaced apart from the pixel circuit in a plan view.
Regarding claim 11, Takei discloses (in at least fig. 1) a display apparatus comprising: a substrate (2); a pixel circuit (4) disposed on the substrate; a planarization insulating layer (10) disposed on the pixel circuit; a bank layer (14) disposed on an upper surface of the planarization insulating layer opposite to a lower surface of the planarization insulating layer facing the substrate (see fig. 1); and an intermediate layer (15) disposed in a first space disposed in the planarization insulating layer and the bank layer (see fig. 1), wherein the first space includes a first structure defined in the planarization insulating layer (10; see fig. 1) and a first opening defined in the bank layer (see fig. 1), the first opening is defined between portions of the bank layer next to each other, and a maximum width of the first opening is greater than a maximum width of the first structure (see fig. 1).
Regarding claim 12, Takei discloses (in at least fig. 1) the first space is spaced apart from the pixel circuit in a plan view.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3-10 and 13-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takei (US. Pub: 2010/0200875 A1) in view of Park et al. (US. Pub: 2015/0108452 A1~ hereinafter “Park”) of record.
Regarding claim 3, Takei discloses (in at least fig. 1) the planarization insulating layer comprises: a first planarization insulating layer (10); but is silent about a second planarization insulating layer on the first planarization insulating layer.
Park in the same field of a display device discloses (in at least fig. 6 below) comprised of, in part, a planarization insulating layer comprises a first planarization layer (16, 19); and a second planarization insulating layer (19; i.e. the second planarization layer 19) in order to provide suitable planarization to the pixel circuit layer.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the display device of Takei with the second planarization layer of Park in order to provide suitable planarization to the pixel circuit layer. Furthermore, it has been held that mere duplication of the essential working parts of an invention involves only routine skill in the art.
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Regarding claim 4, Park discloses (in at least fig. 6 above) a first groove is defined in the second planarization insulating layer (19) in the first structure (see at least fig. 6 above).
Regarding claim 5, Park discloses (in at least fig. 6 above) a second opening (OP2 or C5) is defined in the second planarization insulating layer (19) in the first structure.
Regarding claim 6, Park discloses (in at least fig. 6 above) a second groove (see at least fig. 6) overlapping the second opening (C5 or OP2) is defined in the first planarization insulating layer (16, 19) in the first structure.
Regarding claim 7, Park discloses (in at least fig. 6 above) a third opening (C1) overlapping the second opening (C5 or OP2) is defined in the first planarization insulating layer (16, 19) in the first structure.
Regarding claim 8, Park discloses (in at least fig. 6 above) a first electrode (120) connected to the intermediate layer (121) and including at least a portion disposed between the second planarization insulating layer (19) and the bank layer (20); and a contact metal (114) connecting the first electrode (120) to the pixel circuit (212) and including at least a portion disposed between the first planarization insulating layer (16) and the second planarization insulating layer (19), wherein the first structure (OP3) and the first opening (OP1) are spaced apart from the contact metal in a plan view (see at least fig. 6 above).
Regarding claim 9, Park discloses (in at least fig. 6 above) the planarization insulating layer further comprises a third planarization insulating layer ([0044]; i.e. item 19 may include many layers) on the second planarization insulating layer.
Regarding claim 10, Park discloses (in at least fig. 6 above) a fourth opening (as evident by at least [0044]) is defined in the third planarization insulating layer in the first structure.
Regarding claim 13, Park discloses (in at least fig. 6 above) the planarization insulating layer comprises: a first planarization insulating layer (16, 19); and a second planarization insulating layer (19) on the first planarization insulating layer (see at least fig. 6 above).
Regarding claim 14, Park discloses (in at least fig. 6 above) the first space comprises: a first groove overlapping the first opening (OP1) and defined in the second planarization insulating layer (19).
Regarding claim 15, Park discloses (in at least fig. 6 above) the first space comprises: the first opening (C8 or OP1) defined in the bank layer (20); and a second opening (C5 or OP2) overlapping the first opening and defined in the second planarization insulating layer (19).
Regarding claim 16, Park discloses (in at least fig. 6 above) the first space further comprises a second groove (see fig. 6) overlapping the second opening (C5 or OP2) and defined in the first planarization insulating layer (19).
Regarding claim 17, Park discloses (in at least fig. 6 above) the first space further comprises a third opening (C1) overlapping the second opening (C5 or OP2) and defined in the first planarization insulating layer (19).
Regarding claim 18, Park discloses (in at least fig. 6 above) the planarization insulating layer further comprises a third planarization insulating layer ([0044]; i.e. item 19 may include many layers) on the second planarization insulating layer.
Regarding claim 19, Park discloses (in at least fig. 6 above) a fourth opening (as evident by at least [0044]) is defined in the third planarization insulating layer in the first structure.
Regarding claim 20, Park discloses (in at least fig. 6 above) a first electrode (120) connected to the intermediate layer (121) and including at least a portion disposed between the second planarization insulating layer (19) and the bank layer (20); and a contact metal (114) connecting the first electrode to the pixel circuit and including at least a portion disposed between the first planarization insulating layer (19; i.e. lower portion) and the second planarization insulating layer (19; i.e. upper portion), wherein the first space is spaced apart from the contact metal in a plan view (see at least fig. 6 above).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELMITO BREVAL whose telephone number is (571)270-3099. The examiner can normally be reached M-Th~ 7:30-5:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James R. Greece can be reached at 571-272-3711. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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ELMITO BREVAL
Primary Examiner
Art Unit 2875
/ELMITO BREVAL/Primary Examiner, Art Unit 2875
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