DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/16/2026 has been entered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by Park et al. (US. Pub: 2015/0108452 A1~hereinafter “Park”) of record.
Regarding claim 1, Park discloses (in at least fig. 6 below) a display apparatus comprising: a substrate (10); a pixel circuit (212) disposed on the substrate; a planarization insulating layer (19) which is disposed on the pixel circuit and including a first structure (OP3) in which an opening or a groove (see fig. 6) is defined (see at least fig. 6 below); a bank layer (20) which is disposed on the planarization insulating layer (19) and in which a first opening (PO1) overlapping the first structure is defined (see at least fig. 6 below); and an intermediate layer (121; [0038]) disposed in at least a portion of the first structure (OP3) and the first opening (OP1; see fig. 6 below), wherein the first opening (OP1) is defined between portions of the bank layer (20) next to each other; and a maximum width of the first opening (OP1) is greater than a maximum width of the first structure (OP3).
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Regarding claim 2, Park discloses (in at least fig. 6 above) the first structure (OP3) and the first opening (OP1 or C8) are spaced apart from the pixel circuit in a plan view.
Regarding claim 3, Park discloses (in at least fig. 6 above) the planarization insulating layer (19) comprises: a first planarization insulating layer (16); and a second planarization insulating layer (19) on the first planarization insulating layer (see fig. 6 above).
Regarding claim 4, Park discloses (in at least fig. 6 above) a first groove is defined in the second planarization insulating layer (19) in the first structure (see at least fig. 6 above).
Regarding claim 5, Park discloses (in at least fig. 6 above) a second opening (OP2 or C5) is defined in the second planarization insulating layer (19) in the first structure.
Regarding claim 6, Park discloses (in at least fig. 6 above) a second groove (see at least fig. 6) overlapping the second opening (C5 or OP2) is defined in the first planarization insulating layer (16) in the first structure.
Regarding claim 7, Park discloses (in at least fig. 6 above) a third opening (C1) overlapping the second opening (C5 or OP2) is defined in the first planarization insulating layer (19) in the first structure.
Regarding claim 8, Park discloses (in at least fig. 6 above) a first electrode (120) connected to the intermediate layer (121) and including at least a portion disposed between the second planarization insulating layer (19) and the bank layer (20); and a contact metal (114) connecting the first electrode (120) to the pixel circuit (212) and including at least a portion disposed between the first planarization insulating layer (16) and the second planarization insulating layer (19), wherein the first structure (OP3) and the first opening (OP1) are spaced apart from the contact metal in a plan view (see at least fig. 6 above).
Regarding claim 9, Park discloses (in at least fig. 6 above) the planarization insulating layer further comprises a third planarization insulating layer ([0044]; i.e. item 19 may include many layers) on the second planarization insulating layer.
Regarding claim 10, Park discloses (in at least fig. 6 above) a fourth opening (as evident by at least [0044]) is defined in the third planarization insulating layer in the first structure.
Regarding claim 11, Park discloses (in at least fig. 6 above) a display apparatus comprising: a substrate (10); a pixel circuit (212) disposed on the substrate; a planarization insulating layer (19) disposed on the pixel circuit; a bank layer (20) disposed on the planarization insulating layer; and an intermediate layer (121) disposed in a first space disposed in the planarization insulating layer and the bank layer, wherein a first opening (OP1) defined in the bank layer, and the first opening (OP1) is defined between portions of the bank layer next to each other (see at least fig. 6 above); and a maximum width of the first opening (OP1) is greater than a maximum width of the first structure (OP3).
Regarding claim 12, Park discloses (in at least fig. 6 above) the first space is spaced apart from the pixel circuit in a plan view.
Regarding claim 13, Park discloses (in at least fig. 6 above) the planarization insulating layer comprises: a first planarization insulating layer (19); and a second planarization insulating layer (19) on the first planarization insulating layer (see at least fig. 6 above).
Regarding claim 14, Park discloses (in at least fig. 6 above) the first space comprises: a first groove overlapping the first opening (OP1) and defined in the second planarization insulating layer (19).
Regarding claim 15, Park discloses (in at least fig. 6 above) the first space comprises: the first opening (C8 or OP1) defined in the bank layer (20); and a second opening (C5 or OP2) overlapping the first opening and defined in the second planarization insulating layer (19).
Regarding claim 16, Park discloses (in at least fig. 6 above) the first space further comprises a second groove (see fig. 6) overlapping the second opening (C5 or OP2) and defined in the first planarization insulating layer (19).
Regarding claim 17, Park discloses (in at least fig. 6 above) the first space further comprises a third opening (C1) overlapping the second opening (C5 or OP2) and defined in the first planarization insulating layer (19).
Regarding claim 18, Park discloses (in at least fig. 6 above) the planarization insulating layer further comprises a third planarization insulating layer ([0044]; i.e. item 19 may include many layers) on the second planarization insulating layer.
Regarding claim 19, Park discloses (in at least fig. 6 above) a fourth opening (as evident by at least [0044]) is defined in the third planarization insulating layer in the first structure.
Regarding claim 20, Park discloses (in at least fig. 6 above) a first electrode (120) connected to the intermediate layer (121) and including at least a portion disposed between the second planarization insulating layer (19) and the bank layer (20); and a contact metal (114) connecting the first electrode to the pixel circuit and including at least a portion disposed between the first planarization insulating layer (19; i.e. lower portion) and the second planarization insulating layer (19; i.e. upper portion), wherein the first space is spaced apart from the contact metal in a plan view (see at least fig. 6 above).
Response to Arguments
Applicant's arguments filed 3/12/2026 have been fully considered but they are not persuasive. The Applicant argues that Park’s reference fails to disclose the newly amended limitation “a maximum width of the first opening is greater than a maximum width of the first structure” as cited in claims 1 and 11.
In response to that argument, the Examiner respectfully disagrees. As noted in the fig. 6, Park clearly discloses “a maximum width of the first opening (OP1) is greater than a maximum width of the first structure (OP3).” Also, as can be noted, the Examiner interpretation is consistent with the Applicant “first structure” and “first opening.” Therefore, the argument is not persuasive.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELMITO BREVAL whose telephone number is (571)270-3099. The examiner can normally be reached M-Th~ 7:30-5:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James R. Greece can be reached at 571-272-3711. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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ELMITO BREVAL
Primary Examiner
Art Unit 2875
/ELMITO BREVAL/Primary Examiner, Art Unit 2875
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