Prosecution Insights
Last updated: August 17, 2026
Application No. 18/124,992

LAYOUT DESIGN SYSTEM USING DEEP REINFORCEMENT LEARNING AND LEARNING METHOD THEREOF

Final Rejection §103
Filed
Mar 22, 2023
Priority
Oct 14, 2022 — RE 10-2022-0132289
Examiner
SOUNDRANAYAGAM, RAYAPPU NMN
Art Unit
2851
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
2 (Final)
100%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 100% — above average
100%
Career Allowance Rate
2 granted / 2 resolved
+32.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
12 currently pending
Career history
13
Total Applications
across all art units

Statute-Specific Performance

§103
42.0%
+2.0% vs TC avg
§102
46.0%
+6.0% vs TC avg
§112
12.0%
-28.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 2 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification Previous objections to the specification are withdrawn in view of Applicant’s Amendments filed 05/12/2026. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 9-15 are rejected under 35 U.S.C. 103 as being unpatentable over Sooyong LEE et. al., hereinafter LEE, (20210334444) in view of NAOAKI TSUTSUI et. al. (US 20200184137 A1), hereinafter TSUTSUI. Regarding claim 9 LEE teaches sections a, b, c, and e part of claim 9 A learning method of a layout optimization system, the learning method comprising (LEE, p. 1, “[0007] According to some example embodiments, a method for fabricating of a semiconductor device includes.”) receiving a target layout comprising a plurality of target layout patterns (LEE, p. 1 “[0007] According to some example embodiments, a method for fabricating of a semiconductor device includes receiving a first layout including patterns for the fabrication of the semiconductor device.”) (LEE, p. 3, [0054] “Referring to FIGS. 2 through 5, the machine learning module 220 may receive a first layout L1. For example, the first layout L1 may specify a target layout required to be obtained in after-cleaning inspection (ACI).”) generating, by a deep reinforcement learning (DRL) module, a prediction layout comprising a plurality of prediction layout patterns respectively corresponding to the plurality of target layout patterns (LEE, p. 3, [0054] “… The machine learning module 220 and the correction module 240 may perform the PPC with respect to the first layout L1 to generate a second layout L2. The PPC may be performed through inference based on machine learning with respect to features of patterns in the first layout L1. For example, the second layout L2 may be a target layout of photo resist patterns in after development inspection (ADI).”) Machine learning module is a general term covering all different kinds including deep reinforcement learning module. receiving, by the DRL module, a change to at least one prediction layout pattern of the plurality of prediction layout patterns as an action input (LEE, p. 2, [0036] “In operation S120, the semiconductor process machine learning module 200 may perform process proximity correction (PPC) on the first layout to generate a second layout. The process proximity correction may be made by performing a machine learning-based inference on features of patterns of the first layout. The second layout may be a target layout of a photo resist, which the operator/technician/engineer wants to or intends to obtain in ADI (after development inspection).”) (LEE, p. 2, [0038] “In operation S130, the semiconductor process machine learning module 200 may perform optical proximity correction (OPC) on the second layout to generate a third layout.”) (LEE, p.4, [0057] “When the inferred ACI image is not acceptable, in operation S260 the semiconductor process machine learning module 200 may adjust the features. For example, the semiconductor process machine learning module 200 may adjust patterns' own features such as sizes and/or shapes of the patterns.”) LEE does not teach sections d and f-g of claim 9 generating, by the DRL module, a plurality of action values based on the prediction layout selecting, by the DRL module, a first action value of the plurality of action values corresponding to the action input and determining a loss function by comparing the selected first action value with a second action value corresponding to at least one target layout pattern of the plurality of target layout patterns. However, TSUTSUI teaches section d and f-g of claim 9. generating, by the DRL module, a plurality of action values based on the prediction layout (TSUTSUI, p. 8, [0153] “Step S27 is a step of estimating the action value function Q( s t , a t ) by the processing portion 103.”) (TSUTSUI, p. 8, [0154] “The processing portion 103 includes a first neural network 520 and estimates the action value function Q( s t , a t ) with the first neural network 520. In the first neural network 520, the input data is the image data L I M G t of the layout generated in Step S26 and the output data is the action value function Q( s t , a t ). For the first neural network 520, a convolutional neural network (CNN) configuration is preferably employed.”) selecting, by the DRL module, a first action value of the plurality of action values corresponding to the action input (TSUTSUI, p. 11, [0182] “The processing portion 103 includes a second neural network 530 and estimates the action value function Q( s t + 1 , a t + 1 ) with the second neural network 530. In the second neural network 530, the input data is the image data L I M G t + 1 of the layout generated in Step S31 and the output data is the action value function Q( s t + 1 , a t + 1 ).”) (TSUTSUI, p. 11, [0178] “Step S31 is a step of observing the layout state S t   of an abstract by the processing portion 103.”) and determining a loss function by comparing the selected first action value with a second action value corresponding to at least one target layout pattern of the plurality of target layout patterns. (TSUTSUI, p. 11 [0181] “In general, in learning of deep learning, the weight coefficient of a neural network is updated such that an error between output data and teacher data becomes small. The update of a weight coefficient is repeated until the error between the output data and the teacher data becomes a certain value. In Q learning, which is a kind of reinforcement learning, the purpose of the learning is to search for the optimal Q function; however, the optimal Q function is not found during the learning. Thus, an action value function Q( s t + 1 , a t + 1 ) at the next time t+1 is estimated, and r t + 1 +maxQ( s t + 1 , a t + 1 ) is regarded as teacher data. The first neural network 520 performs learning by using the teacher data for a loss function.”) (TSUTSUI, p. 11 [0189] “Results of the inference of the action value function Q( s t , a t ) by the first neural network 520 and the teacher data generated by the second neural network 530 are used to calculate a loss function.”) (TSUTSUI, p. 10, [0174] “In the case where the layout of the pattern satisfies the design rule (Yes), the process goes to Step S30. In the case where the design rule is not satisfied (No), the process goes to Step S36.”) Therefore, it would have been obvious before the effective priority date of the claim to a person having ordinary skill in the art to combine the teachings of LEE and TSUTSUI to train the deep reinforcement learning module using simulations iteratively, as it is very effective in refining trained concepts, and further to generate action values followed by determining loss function to eventually updating the weighting factors of the neural network so that the value of the loss function becomes smaller. A well-trained neural network is essential for producing optimal layout. Regarding claim 11 LEE and TSUTSUI teach all the features of claim 9 as disclosed above. LEE does not teach The learning method of claim 9, further comprising: receiving, by the DRL module, the target layout as an input layer; and outputting, by the DRL module, the plurality of action values from an output layer. (TSUTSUI, p. 11, [0181] “… In Q learning, which is a kind of reinforcement learning, the purpose of the learning is to search for the optimal Q function; however, the optimal Q function is not found during the learning. Thus, an action value function Q( s t + 1 , a t + 1 ) at the next time t+1 is estimated, and r t + 1 +maxQ( s t + 1 , a t + 1 ) is regarded as teacher data.”) (TSUTSUI, p. 11, [0182] “The processing portion 103 includes a second neural network 530 and estimates the action value function Q( s t + 1 , a t + 1 ) with the second neural network 530. In the second neural network 530, the input data is the image data L I M G t + 1 of the layout generated in Step S31, and the output data is the action value function Q( s t + 1 , a t + 1 ).”) Therefore, it would have been obvious before the effective priority date of the claim to a person having ordinary skill in the art to combine the teachings of LEE and TSUTSUI to train the deep reinforcement learning module using simulations iteratively, as it is very effective in refining trained concepts, and further to generate action values followed by determining loss function to eventually updating the weighting factors of the neural network so that the value of the loss function becomes smaller. A well-trained neural network is essential for producing optimal layout. Note that teacher data is considered as the target layout. Regarding claim 12 LEE and TSUTSUI teach all the features of claim 11 as disclosed above. LEE does not teach The learning method of claim 11, wherein the DRL module comprises a weight indicating an effect of a change between patterns of the plurality of prediction layout patterns. However, TSUTSUI teaches The learning method of claim 11, wherein the DRL module comprises a weight indicating an effect of a change between patterns of the plurality of prediction layout patterns. (TSUTSUI , p. 11 [0181] “In general, in learning of deep learning, the weight coefficient of a neural network is updated such that an error between output data and teacher data becomes small.”) Therefore, it would have been obvious before the effective priority date of the claim to a person having ordinary skill in the art to combine the teachings of LEE and TSUTSUI to train the deep reinforcement learning module using simulations iteratively, as it is very effective in refining trained concepts, and further to generate action values followed by determining loss function to eventually updating the weighting factors of the neural network so that the value of the loss function becomes smaller. A well-trained neural network is essential for producing optimal layout. Regarding claim 13 LEE and TSUTSUI teach all the features of claim 9 as disclosed above and LEE further discloses The learning method of claim 9, wherein the action input corresponds to a size adjustment of at least one prediction layout pattern of the plurality of prediction layout patterns. (LEE, p. 5, [0082] “In operation S460, when the inferred ACI image is not acceptable, the correction module 240 may modify the first layout L1. For example, the correction module 240 may adjust the features of the patterns corresponding to pattern dimensions, such as sizes, shapes, etc.”) (LEE, p. 5, [0083] “In some example embodiments, the adjustment of the features of the patterns may be performed by the inference based on machine learning. The correction module 240 may perform an inference with respect to the difference between the inferred ACI image and the target ACI image to adjust the first layout L1. For example, the correction module 240 may perform an inference with respect to each of the patterns, with respect to a group of patterns, or an image of patterns.”) (LEE, p. 3, [0054] “… The machine learning module 220 and the correction module 240 may perform the PPC with respect to the first layout L1 to generate a second layout L2. The PPC may be performed through inference based on machine learning with respect to features of patterns in the first layout L1. For example, the second layout L2 may be a target layout of photo resist patterns in after development inspection (ADI).”) (LEE, p. 4, [0056] “The machine learning module 220 and the correction module 240 may perform the OPC with respect to the second layout L2 to generate a third layout L3. For example, the third layout L3 may be a layout of a photo-mask.”) Regarding claim 14 LEE and TSUTSUI teach all the features of claim 13 as disclosed above and LEE further discloses. The learning method of claim 13, wherein the action input comprises a size adjustment applied a plurality of times at different time points for the at least one prediction layout pattern (LEE, p.9, [0149] “The correction module 240 may compare the size x1/y1 of the pattern in the ACI image 410 and the size x2/y2 of the pattern in the target image 420 to generate an error value dx/dy as shown in an image 430. For example, during the zero-th iteration (e.g., a first iteration), the size x/y of the pattern in the layout image 400 may be 100/100, the size x1/y1 of the pattern in the ACI image 410 may be 120/122, and the size x2/y2 of the pattern in the target image 420 may be 110/110.”) (LEE, p. 9, [0150] “For example, during the first iteration, the size x/y of the pattern in the adjusted layout image 400 may be 90/98, and the size x1/y1 of the pattern in the adjusted ACI image 410 may be 108/109.”) (LEE, p. 9, [0151] “For example, during the second iteration, the size x/y of the pattern in the adjusted layout image 400 may be 92/89, and the size x1/y1 of the pattern in the adjusted ACI image 410 may be 110.2/110.3.”) (LEE, p. 9, [0152] “For example, during the N-th iteration, the size x/y of the pattern in the adjusted layout image 400 may be 92.2/89.4, and the size x1/y1 of the pattern in the adjusted ACI image 410 may be 110/110.”) (LEE, p. 4, [0056] “The machine learning module 220 and the correction module 240 may perform the OPC with respect to the second layout L2 to generate a third layout L3. For example, the third layout L3 may be a layout of a photo-mask.”) (LEE, p. 4, [0064] “The procedure to generate the second layout L2 of FIG. 4 from the first layout L1 of FIG. 3 may be based on the PPC. In some example embodiments, as will be described below with reference to FIGS. 11 through 15, the PPC may be performed based on features generated from an initial layout, such as an initial layout image or set of layout data. The feature-based PPC may be performed at least in part based on edge information of patterns such as widths and spaces of the patterns. In some example embodiments, as will be described below with reference to FIGS. 16 through 24, the PPC may be performed based on images. The image-based PPC may be performed such that the images of the layout are processed to predict a critical dimension (CD), and the processed images of the layout may be corrected based on the predicted CD.”) Regarding claim 15 LEE and TSUTSUI teach all features of claim 9 as disclosed above. LEE teaches section a of claim 15 The learning method of claim 9, further comprising: receiving a size adjustment as an action input (LEE, p. 5, [0082] “In operation S460, when the inferred ACI image is not acceptable, the correction module 240 may modify the first layout L1. For example, the correction module 240 may adjust the features of the patterns corresponding to pattern dimensions, such as sizes, shapes, etc.”) LEE does not teach sections b-c of claim 15 selecting one of the plurality of action values and determining the loss function in an operation loop However, TSUTSUI discloses selecting one of the plurality of action values (TSUTSUI, p. 11, [0180] “Step S32 is a step of estimating the action value function Q( s t + 1 , a t + 1 ) by the processing portion 103.”) and determining the loss function in an operation loop (TSUTSUI, p. 11 [0181] “In general, in learning of deep learning, the weight coefficient of a neural network is updated such that an error between output data and teacher data becomes small.”) (TSUTSUI, p. 8, [0153] “Step S27 is a step of estimating the action value function Q( s t , a t ) by the processing portion 103..”) (TSUTSUI, p. 8, [0154] “The processing portion 103 includes a first neural network 520 and estimates the action value function Q( s t , a t ) with the first neural network 520. In the first neural network 520, the input data is the image data L I M G t of the layout generated in Step S26 and the output data is the action value function Q( s t , a t ).”) (TSUTSUI, p. 11, [0181] “… The first neural network 520 performs learning by using the teacher data for a loss function.”) (TSUTSUI, p. 11 [0189] “Results of the inference of the action value function Q( s t , a t ) by the first neural network 520 and the teacher data generated by the second neural network 530 are used to calculate a loss function. With the use of a stochastic gradient descent (SGD), the weight coefficient of the first neural network 520 is updated such that the value of the loss function becomes small.”) Therefore, it would have been obvious before the effective priority date of the claim to a person having ordinary skill in the art to combine the teachings of LEE and TSUTSUI to train the deep reinforcement learning module using simulations iteratively, as it is very effective in refining trained concepts, and further to generate action values followed by determining loss function to eventually updating the weighting factors of the neural network so that the value of the loss function becomes smaller. A well-trained neural network is essential for producing optimal layout. Allowable Subject Matter Claims 1-8 and 16-21 allowed. The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 1 LEE discloses A layout optimization system, the system comprising (LEE, p. 1, [0006] “Example embodiments of inventive concepts provide a method and/or a computing device for generating a layout for manufacturing/fabrication of a semiconductor device, such as semiconductor chip, having improved reliability and/or reduced amount of computation.”) a deep reinforcement learning (DRL) module (LEE, p. 1, [0016] “FIG. 6 illustrates an example in which a semiconductor process machine learning module according to some example embodiments of inventive concept executes process proximity correction.”) Machine learning module is a general term covering all different kinds including deep reinforcement learning module. a memory storing instructions (LEE, p. 2, [0026] “FIG. 1 is a block diagram illustrating a computing device 100 according to some example embodiments of inventive concepts. Referring to FIG. 1, the computing device 100 may include one or more processors 110, a random access memory 120, one or more device drivers 130, one or more storage devices 140, one or more modem 150, and one or more user interfaces 160.”) (LEE, p. 2, [0027]” ... In this case, the at least one processor may load the instructions (or codes) of the semiconductor process machine learning module 200 onto the random access memory 120.”) and a processor configured to execute the instructions to (LEE, p. 2, [0026] “FIG. 1 is a block diagram illustrating a computing device 100 according to some example embodiments of inventive concepts. Referring to FIG. 1, the computing device 100 may include one or more processors 110, a random access memory 120, one or more device drivers 130, one or more storage devices 140, one or more modem 150, and one or more user interfaces 160.”) receive a target layout comprising a plurality of target layout patterns (LEE, p. 1, [0007] “According to example embodiments, a method of correcting a layout for semiconductor processes includes receiving a layout, wherein the layout comprises schematic information for semiconductor processes to form process patterns of a semiconductor device, and further comprises a plurality of layout patterns;”) (LEE, p. 3, [0054] “Referring to FIGS. 2 through 5, the machine learning module 220 may receive a first layout L1. For example, the first layout L1 may specify a target layout required to be obtained in after-cleaning inspection (ACI).”) generate, by the DRL module, a prediction layout comprising a plurality of prediction layout patterns respectively corresponding to the plurality of target layout patterns (LEE, p. 3, [0054] “… The machine learning module 220 and the correction module 240 may perform the PPC with respect to the first layout L1 to generate a second layout L2. The PPC may be performed through inference based on machine learning with respect to features of patterns in the first layout L1. For example, the second layout L2 may be a target layout of photo resist patterns in after development inspection (ADI).”) Machine learning module is a general term covering all different kinds including deep reinforcement learning module. Neither LEE nor any prior art teaches sections f and g of claim 1 determine, by the DRL module, an optimal layout pattern correction sequence for correcting the prediction layout through reinforcement learning and generate, by the DRL module, an optimal predictive layout by applying the optimal layout pattern correction sequence to the prediction layout. Claims 2-8 and 21 are allowed based on their dependency to claim 1. Regarding claim 16 LEE and TSUTSUI teach all features of claim 15 as disclosed above. Neither LEE nor any prior art teaches claim 16 The learning method of claim 15, further comprising selecting, in the operation loop, an optimal layout pattern correction sequence for correcting the prediction layout a layout pattern corresponding to an at least one action value that minimizes the loss function Regarding claim 17 LEE teaches sections a of claim 17 A method, comprising receiving a target layout comprising a plurality of target layout patterns (LEE, p. 1 “[0007] According to some example embodiments, a method for fabricating of a semiconductor device includes receiving a first layout including patterns for the fabrication of the semiconductor device.”) (LEE, p. 3, [0054] “Referring to FIGS. 2 through 5, the machine learning module 220 may receive a first layout L1. For example, the first layout L1 may specify a target layout required to be obtained in after-cleaning inspection (ACI).”) generating, by a deep reinforcement learning (DRL) module, a prediction layout comprising a plurality of prediction layout patterns respectively corresponding to the plurality of target layout patterns (LEE, p. 3, [0054] “… The machine learning module 220 and the correction module 240 may perform the PPC with respect to the first layout L1 to generate a second layout L2. The PPC may be performed through inference based on machine learning with respect to features of patterns in the first layout L1. For example, the second layout L2 may be a target layout of photo resist patterns in after development inspection (ADI).”) Machine learning module is a general term covering all different kinds including deep reinforcement learning module. Neither LEE nor any other prior art teaches sections c-d of claim 17 determine, by the DRL module, an optimal layout pattern correction sequence for correcting the prediction layout through reinforcement learning generating, by the DRL module, an optimal predictive layout by applying the optimal layout pattern correction sequence to the prediction layout Claims 18-20 are allowed based on their dependency to claim 17. Response to Arguments Applicant’s arguments, see page 11, under Claim Rejections - 35 USC 103, lines 14-17 filed 05/12/2026, with respect to claim 1 and 17 have been fully considered and are persuasive. The rejection of claim 1 and its dependent claims 2-8 and 21, as well as claim 17 and its dependent claims 18-20 have been withdrawn. With respect to claim 9, the persuasiveness of the argument which stem from the inclusion of “correction sequence” in the independent claims 1 and 17 is not present in claim 9, and thus it remains rejected, while its dependent claim 16 is allowed. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to RAYAPPU SOUNDRANAYAGAM whose telephone number is (571)272-0629. The examiner can normally be reached Mon-Fri:8:00 AM-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at (571) 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /R.S./Examiner, Art Unit 2851 /JACK CHIANG/Supervisory Patent Examiner, Art Unit 2851
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Prosecution Timeline

Mar 22, 2023
Application Filed
Feb 12, 2026
Non-Final Rejection mailed — §103
Mar 15, 2026
Interview Requested
Mar 24, 2026
Applicant Interview (Telephonic)
Mar 24, 2026
Examiner Interview Summary
May 12, 2026
Response Filed
Jul 02, 2026
Final Rejection mailed — §103
Jul 20, 2026
Interview Requested

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Prosecution Projections

3-4
Expected OA Rounds
100%
Grant Probability
99%
With Interview (+0.0%)
3y 3m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 2 resolved cases by this examiner. Grant probability derived from career allowance rate.

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