DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Invention Group I, claims 1-16, in the reply filed on 02/25/2026 is acknowledged. Claims 17-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Invention Group II, there being no allowable generic or linking claim.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 5-16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Gui et al. (US PG-Pub No.: 2022/0320212 A1, hereinafter, “Gui”).
Regarding claim 1, Gui discloses a display device (see Gui, FIG. 15) comprising:
a base substrate (GI1, FIG. 15);
a barrier layer (GI2, FIG. 15) disposed on the base substrate (GI1);
a first metal layer (40, FIG. 15) disposed on the barrier layer (GI2);
a second metal layer (30, FIG. 15) disposed on the base substrate (GI1) and spaced apart from the first metal layer (40);
a buffer layer (GI3, FIG. 15) disposed on the first metal layer (40) and the second metal layer (30); and
a plurality of thin film transistors (FIG. 15 shows one pixel and one transistor above 40; FIGs. 1 and 2 show a plurality of pixels, therefore, a plurality of transistors) disposed on the buffer layer (GI3, FIG. 15),
wherein an angle between a side surface of the barrier layer (GI2) and a bottom surface of the barrier layer (GI2) is equal to or more than 90 degrees and less than or equal to 150 degrees (FIG. 15).
Regarding claim 5, Gui discloses the display device of claim 1, wherein the first metal layer and the second metal layer contain a same material (to meet this limitation, the first metal layer is left 40 in FIG. 15 and the second metal layer is right 40 in FIG. 15).
Regarding claim 6, Gui discloses the display device of claim 1, wherein the first metal layer (40) is in contact with a top surface of the barrier layer (to meet this limitation, the barrier layer is 163+GI2) and the second metal layer (30) is in contact with a top surface of the base substrate (GI1, FIG. 15).
Regarding claim 7, Gui discloses the display device of claim I. wherein the second metal layer (to meet this limitation, the first metal layer is left 40 in FIG. 15 and the second metal layer is right 40 in FIG. 15) is spaced apart from the side surface of the barrier layer (GI2).
Regarding claim 8, Gui discloses the display device of claim 1, wherein a planar area (bottom) of the first metal layer (40) is the same as a planar area (top) of the barrier layer (to meet this limitation, the barrier layer is 163+GI2, FIG. 15).
Regarding claim 9, Gui discloses the display device of claim 1, wherein each of thicknesses of the first metal layer (40) and a second metal layer (30) is smaller than a thickness of the barrier layer (GI2, FIG.15).
Regarding claim 10, Gui discloses the display device of claim 1, wherein a height of a top surface of the second metal layer (30) is smaller than a height of a bottom surface of the first metal layer (40), and the heights are measured in a direction perpendicular to a top surface of the base substrate (GI1, FIG. 15).
Regarding claim 11, Gui discloses the display device of claim 1, wherein the first metal layer (to meet this limitation, the first metal layer is left 40 in FIG. 15) and the second metal layer (30) do not overlap each other in a plan view (FIG. 15).
Regarding claim 12, Gui discloses a display device (see Gui, FIG. 15) comprising:
a first base substrate (GI1, FIG. 15);
a first barrier layer ((GI2, FIG. 15) disposed on the first base substrate (GI1);
a first metal layer (40, FIG. 15) disposed on the first barrier layer (GI2);
a second metal layer (30, FIG. 15) disposed on the first base substrate (GI1) and spaced apart from the first metal layer (40);
a buffer layer (GI3, FIG. 15) disposed on the first metal layer (40) and the second metal layer (30); and
a plurality of thin film transistors (FIG. 15 shows one pixel and one transistor above 40; FIGs. 1 and 2 show a plurality of pixels, therefore, a plurality of transistors) disposed on the buffer layer (GI3, FIG. 15),
wherein an angle between a side surface of the first barrier layer (GI2) and a top surface of the first base substrate (GI1) is about 90 degrees (FIG. 15).
Regarding claim 13, Gui discloses the display device of claim 12, wherein the second metal layer (30) is in contact with the side surface of the first barrier layer (GI2, FIG. 15).
Regarding claim 14, Gui disclosed the display device of claim 12, wherein the side surface of the first barrier layer (GI2) and a side surface of the first metal layer (to meet the limitation, the first metal layer is right 40) are aligned and coincide with each other (FIG. 15).
Regarding claim 15, Gui discloses the display device of claim 12, wherein the plurality of thin film transistors comprises an active layer (FIG. 15), a gate electrode (60, FIG. 15), a source electrode (70, FIG. 15), and a drain electrode (70), and wherein the active layer overlaps the first metal layer (left 40) in a plan view (FIG. 15).
Regarding claim 16, Gui discloses the display device of claim 12, further comprising: a second base substrate (161, FIG. 15) disposed under the first base substrate (GI1); and a second barrier layer (162, FIG. 15) disposed between the first base substrate (GI1) and the second base substrate (161).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 2-4 are rejected under 35 U.S.C. 103 as being unpatentable over Gui et al. (US PG-Pub No.: 2022/0320212 A1, hereinafter, “Gui”), as applied to claim 1 above, further in view of Duan (US PG-Pub No.: 2024/0164186 A1, hereinafter, “Duan”).
Regarding claim 2, Gui discloses the display device of claim 1.
Gui is silent regarding that the barrier layer (GI2) has a reversed-tapered shape.
Duan, however, discloses a display device (see Duan, FIG. 2), wherein a conductive layer (c1, FIG. 2) has an incline sidewall (FIG. 2).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to form Gui’s second conductive layer 30 having an inclined sidewall, as taught by Duan, since it is an alternative design. Accordingly, Gui’s barrier layer GI2 has a reversed-tapered shape.
Regarding claim 3, Gui in view of Duan discloses the display device of claim 2. wherein the angle between the side surface of the barrier layer (GI2) and the bottom surface of the barrier layer (GI2) is greater than 90 degrees and less than or equal to 150 degrees (Duan, FIG. 2 and statement above regarding claim 2).
Regarding claim 4, Gui in view of Duan discloses the display device of claim 2, wherein a width of the bottom surface of the barrier layer (GI2) is smaller than a width of a top surface of the barrier layer (GI2, see statement above regarding claim 2).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIA L. CROSS whose telephone number is (571)270-3273. The examiner can normally be reached 9 am-5:30 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/XIA L CROSS/Primary Examiner, Art Unit 2892
Prosecution Insights