DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-10, 12-18 and 20 have been considered but are moot on grounds of new rejection.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2019/0027441 A1) in view of Co et al. (Co) (US 2015/0017765 A1).
Claim(s) 1-10 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chen et al. (US 2019/0027441 A1).
In regards to claim 1, Chen (Figs. 1A, 6F and associated text and items) discloses a semiconductor package (item 1), comprising: a first substrate (items 10, 65); a semiconductor chip (items 12a, 62a) on the first substrate (items 10, 65); a second substrate (item shown but not labeled where items 12b and 65b reside) spaced apart from the first substrate (items 10, 65); a wire (items 13v, 63v) spaced apart from a lateral surface of the semiconductor chip (items 12a, 62a), wherein the wire (items 13v, 63v) connects the first substrate (items 10, 65) to the second substrate (item shown but not labeled where items 12b and 65b reside); a mold structure (items 11, 13, 13p, 11 plus 13 or 11 plus 13 plus 13p or 63) comprising a first dielectric material (items 11, 13, 13p, 11 plus 13 or 11 plus 13 plus 13p, 61, 63 or 61 plus 63, paragraphs 41, 43, 79) on the lateral surface of the semiconductor chip (items 12a, 62a), and a lateral surface of the wire (items 13v, 63v); and an under-fill pattern (items 13o1, 13o2, 63o) comprising a second dielectric material (items 13o1, 13o2, 63o, paragraph 40) different from the first dielectric material (items 11, 13, 13p, 11 plus 13 or 11 plus 13 plus 13p, 61, 63 or 61 plus 63, paragraphs 41, 43, 79) of the mold structure (items 11, 13, 13p, 11 plus 13 or 11 plus 13 plus 13p, 61, 63 or 61 plus 63), wherein the underfill pattern (items 13o1, 13o2, 63o) surrounds the lateral surface of the wire (items 13v, 63v) and is disposed between the wire (items 13v, 63v) and the mold structure (items 11, 13, 13p, 11 plus 13 or 11 plus 13 plus 13p or 63); and wherein the underfill is in direct contact with the mold structure (items 11, 13, 13p, 11 plus 13 or 11 plus 13 plus 13p or 63), but does not specifically disclose a mold structure (items 11, 13, 13p, 11 plus 13 or 11 plus 13 plus 13p or 63) comprising a first dielectric material (items 11, 13, 13p, 11 plus 13 or 11 plus 13 plus 13p, 61, 63 or 61 plus 63, paragraphs 41, 43, 79) on a top surface of the semiconductor chip (items 12a, 62a),
Co (paragraph 88, Figs. 1, 6, 7, 17A, and associated text and items) discloses a mold structure (item 42) comprising a first dielectric material (items 42, paragraph 71) on a top surface of the semiconductor chip (items 22), the lateral surface of the semiconductor chip (item 22), and a lateral surface of the wire (items 34, 32).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Co for the purpose of protection and design choice.
In regards to claim 2, Chen (Figs. 1A, 6F and associated text and items) discloses wherein the mold structure (items 11, 13, 13p, 11 plus 13 or 11 plus 13 plus 13p, 61, 63 or 61 plus 63) and the under-fill pattern (items 13o1, 13o2, 63o) have an interface therebetween.
In regards to claim 3, Chen (Figs. 1A, 6F and associated text and items) as modified by Co (paragraph 88, Figs. 1, 5, 6, 7, 13, 17A, and associated text and items) discloses wherein: the first substrate (items 10, 65, Chen, item 12, Co) comprises an upper pad (items shown but not labeled on items 10, 65, Chen, items 28, 328, Co) on a top surface of the first substrate (items 10, 65, Chen, item 12, Co), and the under-fill pattern (items 13o1, 13o2, 63o) contacts the upper pad (items shown but not labeled on items 10, 65, Chen, items 28, 328, Co). Examiner notes that the Applicant has not given a special definition to the term “contact(s)”, therefore certain features can be in “direct” or “indirect” contact with one another.
In regards to claim 4, Chen (Figs. 1A, 4B, 4C 4D, 4E, 6F and associated text and items) discloses wherein: when viewed in plan (Figs. 4B, 4C 4D, 4E), the under-fill pattern (items 13o1, 13o2, 43o, 63o) has a ring shape around the wire (items 13v, 43v, 63v), and an upper surface of the wire (items 13v, 43v, 63v) is exposed from the under-fill pattern (items 13o1, 13o2, 43o, 63o).
In regards to claim 5, Chen (Figs. 1A, 6F and associated text and items) as modified by Co (paragraph 88, Figs. 1, 5, 6, 7, 13, 17A, and associated text and items) discloses the under-fill pattern (items 13o1, 13o2, 43o, 63o, Chen, item 78, Co) has a first width in a first direction parallel to a top surface of the first substrate (items 10, 65, Chen, item 12, Co), but does not specifically disclose the first width increases with decreasing distance from the first substrate (items 10, 65, Chen, item 12, Co).
It would have been obvious to modify the invention to include a first width that increases with decreasing distance from the first substrate, since such a modification would have involved a mere change in the size/shape of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
In regards to claim 6, Chen (Figs. 1A, 6F and associated text and items) and Co (paragraph 88, Figs. 1, 5, 6, 7, 13, 17A, and associated text and items) both discloses wherein an upper surface of the wire (items 13v, 43v, 63v, Chen, items 34, 32, Co), and upper surface of the under-fill pattern (items 13o1, 13o2, 43o, 63o, Chen, item 78, Co), and an upper surface of the mold structure (items 11, 13, 13p, 11 plus 13 or 11 plus 13 plus 13p, 61, 63 or 61 plus 63, Chen, item 42, Co) are coplanar.
In regards to claim 7, Chen (Figs. 1A, 6F and associated text and items) as modified by Co (paragraph 88, Figs. 1, 5, 6, 7, 13, 17A, and associated text and items) discloses wherein: the first substrate (items 10, 65, Chen, item 12, Co) comprises a printed circuit board (PCB) (paragraph 62, Co), and the second substrate (shown but not labeled, Chen, item 54, Co) comprises a redistribution substrate.
It would have been obvious to one of ordinary skill in the art before the effective filing date seeking a package of Co as defined in paragraph 62 to use a PCB as a substrate (See written search report as well).
In regards to claim 8, Chen (Figs. 1A, 6F and associated text and items) as modified by Co (paragraph 88, Figs. 1, 5, 6, 7, 13, 17A, and associated text and items) discloses wherein each of the first substrate (items 10, 65, Chen, item 12, Co) and the second substrate (item 54, Co) comprises a redistribution substrate (items 12, 54).
Claim(s) 9, 10, 12-18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (US 2019/0027441 A1) in view of Co et al. (Co) (US 2015/0017765 A1) as evidenced by or in view of Kim et al. (Kim) (US 2021/0398890 A1).
In regards to claim 9, Chen (Figs. 1A, 6F and associated text and items) discloses a semiconductor package (Figs. 1A, 6F), comprising: a first sub-semiconductor package (items 11 plus 12a plus 10, items 11 plus 12a plus 10 plus substrate shown but not labeled, items 62a plus 65 plus 63 or items 62a plus 65 plus 63 plus substrate shown but not labeled); and a second sub-semiconductor package (items 12b or 12b plus substrate not labeled, items 62b or 62b plus substrate not labeled) on the first sub-semiconductor package (items 11 plus 12a plus 10, items 11 plus 12a plus 10 plus substrate shown but not labeled, items 62a plus 65 plus 63 or items 62a plus 65 plus 63 plus substrate shown but not labeled), wherein the first sub-semiconductor package (items 11 plus 12a plus 10, items 11 plus 12a plus 10 plus substrate shown but not labeled, items 62a plus 65 plus 63 or items 62a plus 65 plus 63 plus substrate shown but not labeled) comprises: a lower substrate (items 10, 65); a first semiconductor chip (items 12a, 62a) on the lower substrate (items 10, 65); an upper substrate (substrate shown but not labeled) spaced apart from the lower substrate (items 10, 65); a plurality of wires (items 13v, 43v, 63v) horizontally spaced apart from a lateral surface of the first semiconductor chip (items 12a, 62a), wherein the plurality of wires (items 13v, 43v, 63v) vertically extend from the lower substrate (items 10, 65) toward the upper substrate (substrate shown but not labeled); an under-fill pattern (shown but no labeled under items 12a and 62a plus items 13o1, 13o2, 43o, 63o) comprising: a plurality of first under-fill patterns (items 13o1, 13o2, 43o, 63o) that cover lateral surfaces of the plurality of wires (items 13v, 43v, 63v); and a second under-fill pattern (shown but no labeled under items 12a and 62a) between the lower substrate (items 10, 65) and the first semiconductor chip (items 12a, 62a); and a mold structure (items 11, 13, 13p, 11 plus 13 or 11 plus 13 plus 13p or 63) covering the first semiconductor chip (items 12a, 62a) and a lateral surface of the under-fill pattern (shown but no labeled under items 12a and 62a plus items 13o1, 13o2, 43o, 63o), wherein the plurality of first under-fill patterns (items 13o1, 13o2, 43o, 63o) are spaced apart from the first semiconductor chip (items 12a, 62a), wherein the plurality of first under-fill patterns (items 13o1, 13o2, 43o, 63o) and the second under-fill pattern (shown but not labeled under items 12a, 62a) are spaced apart, and wherein the under-fill pattern (shown but no labeled under items 12a and 62a plus items 13o1, 13o2, 43o, 63o) comprises a material (Cu.sub.xO.sub.y, Ag.sub.xO.sub.y, Cr.sub.xO.sub.y, Al.sub.xO.sub.y, other metal oxides or other suitable materials, or a combination of two or more thereof ) different from a material (e.g., an epoxy molding compound or other molding compound), a polyimide, a phenolic compound or material, a material with a silicone dispersed therein, or a combination of two or more thereof) of the mold structure (items 11, 13, 13p, 11 plus 13 or 11 plus 13 plus 13p or 63), but does not specifically disclose the plurality of first under-fill patterns (items 13o1, 13o2, 43o, 63o) and the second under-fill pattern (shown but not labeled under items 12a, 62a) are formed of the same material.
It would have been obvious to modify the invention to include a plurality of first under-fill and a second underfill formed of the same material, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use (In re Leshin, 125 USPQ 416).
Chen does not specifically disclose the first sub-semiconductor package comprises a upper substrate.
In regards to claim 9, Co (paragraph 88, Figs. 3, 6, 7, 13, 14, 17A, 24, 25 and associated text and items) discloses a semiconductor package, comprising: a first sub-semiconductor package (Fig. 7, item 410); and a second sub-semiconductor package (item 488) on the first sub-semiconductor package (Fig. 7, item 410), wherein the first sub-semiconductor package (Fig. 6, 7, 14, items 10, 410) comprises: a lower substrate (item 12); a first semiconductor chip (item 22) on the lower substrate (item 12); an upper substrate (item 54) spaced apart from the lower substrate (item 12); a plurality of wires (items 36, 34, 32) horizontally spaced apart from a lateral surface of the first semiconductor chip (item 22), wherein the wires (items 36, 34, 32) vertically extend from the lower substrate (item 12) toward the upper substrate (item 54); and a second under-fill pattern (item 66, Fig. 14) between the lower substrate (items 10, 65) and the first semiconductor chip (items 12a, 62a). As evidence by Co, chips/die can be void of underfill or include underfill. This is merely a design choice.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate features and/or teachings from various embodiments of Co for the purpose of protection and design choice.
Also, as evidence by Kim (Figs. 1, 4 and associated text), chips/die can be void of underfill or include underfill.
In regards to claim 10, Chen (Figs. 1A, 6F and associated text and items) discloses wherein: the plurality of wires (items 13v, 43v, 63v) are disposed along a first direction (vertical) and a second direction (horizontal) that are parallel to an upper surface of the lower substrate (items 10, 65), wherein the second direction (horizontal) intersects the first direction (vertical), each of the first plurality of under-fill patterns (items 13o1, 13o2, 43o, 63o) extends along the first direction (vertical) to contact at least one of the wires (items 13v, 43v, 63v), and the first under-fill patterns (items 13o1, 13o2, 43o, 63o) are spaced apart from each other along the second direction (horizontal).
In regards to claim 12, Chen (Figs. 1A, 4B, 4C 4D, 4E, 6F and associated text and items) discloses wherein each of the first under-fill patterns items 13o1, 13o2, 43o, 63o) has a ring shape when viewed in plan (Fig. 4B-4E).
In regards to claim 13, Chen (Figs. 1A, 4B, 4C 4D, 4E, 6F and associated text and items) as modified by Co (paragraph 88, Figs. 3, 6, 7, 13, 14, 17A, 24, 25 and associated text and items) discloses wherein the first sub-semiconductor package (items 11 plus 12a plus 10, items 11 plus 12a plus 10 plus substrate shown but not labeled, items 62a plus 65 plus 63 or items 62a plus 65 plus 63 plus substrate shown but not labeled) further comprises: a plurality of connection terminals (items 62a1, Chen, item 26, Co) on an active surface of the first semiconductor chip (items 12a, 62a, Chen, item 22, Co); and a second under-fill pattern (shown but not labeled, Chen, item 66, Co) that covers lateral surfaces of the connection terminals (item 62a1, Chen, item 26, Co).
In regards to claim 14, Chen as modified by Co (paragraph 88, Figs. 1, 2, 5, 6, 7, 11, 13, 17A, and associated text and items) discloses wherein: each of the wires (items 36, 34, 32) includes a first portion (items 34 or 36), a second portion (item 32), and a third portion (item 36 or 34), the second portion (item 32) is between the first portion (items 34 or 36) and the third portion (item 36 or 34), and a height of the first portion (item 36) is greater than a sum of a height of the second portion (item 32) and a height of the third portion (item 34).
In regards to claim 15, Chen as modified by Co (paragraph 88, Figs. 1, 2, 5, 6, 7, 11, 13, 17A, and associated text and items) discloses wherein: the first portion (item 36, Co) has a first diameter, the second portion (item 32, Co) has a second diameter, and the third portion (item 34, Co) has a third diameter, the third diameter is greater than the second diameter, but does not specifically disclose the second diameter is greater than the first diameter.
It would have been obvious to modify the invention to include a second diameter that is greater than a first diameter, since such a modification would have involved a mere change in the size/shape of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
In regards to claim 16, Chen (Figs. 1A, 6F and associated text and items) discloses a semiconductor package (Figs. 1A, 6F), comprising: a first sub-semiconductor package (items 11 plus 12a plus 10, items 11 plus 12a plus 10 plus substrate shown but not labeled, items 62a plus 65 plus 63 or items 62a plus 65 plus 63 plus substrate shown but not labeled); and a second sub-semiconductor package (items 12b or 12b plus substrate not labeled, items 62b or 62b plus substrate not labeled) on the first sub-semiconductor package (items 11 plus 12a plus 10, items 11 plus 12a plus 10 plus substrate shown but not labeled, items 62a plus 65 plus 63 or items 62a plus 65 plus 63 plus substrate shown but not labeled), wherein the first sub-semiconductor package (items 11 plus 12a plus 10, items 11 plus 12a plus 10 plus substrate shown but not labeled, items 62a plus 65 plus 63 or items 62a plus 65 plus 63 plus substrate shown but not labeled) comprises: a lower substrate (items 10, 65); a first semiconductor chip (items 12a, 62a) on the lower substrate (items 10, 65); under-fill pattern (shown but no labeled under items 12a and 62a plus items 13o1, 13o2, 43o, 63o) comprising: a first under-fill pattern (items 13o1, 13o2, 43o, 63o) that cover lateral surfaces of the plurality of wires (items 13v, 43v, 63v); and a second under-fill pattern (shown but no labeled under items 12a and 62a) between the first semiconductor chip (items 12a, 62a) and the lower substrate (items 10, 65); a first mold structure (items 11, 13, 13p, 11 plus 13 or 11 plus 13 plus 13p or 63) on the lower substrate (items 10, 65), wherein the first mold structure (items 11, 13, 13p, 11 plus 13 or 11 plus 13 plus 13p or 63) is disposed on lateral surfaces of the first chip (items 12a, 62a) and lateral surfaces of the first under-fill pattern (items 13o1, 13o2, 43o, 63o), wherein the second sub-package comprises: a package substrate (substrate shown but not labeled); a second semiconductor chip (items 12b, 62b) on the package substrate (substrate shown but not labeled); wherein an upper surface of the first under-fill pattern (items 13o1, 13o2, 43o, 63o) is horizontally coplanar with an upper surface of the first semiconductor chip (items 12a, 62a), wherein the plurality of first under-fill patterns (items 13o1, 13o2, 43o, 63o) and the second under-fill pattern (shown but not labeled under items 12a, 62a) are spaced apart, and wherein the under-fill pattern (shown but no labeled under items 12a and 62a plus items 13o1, 13o2, 43o, 63o) comprises a material (Cu.sub.xO.sub.y, Ag.sub.xO.sub.y, Cr.sub.xO.sub.y, Al.sub.xO.sub.y, other metal oxides or other suitable materials, or a combination of two or more thereof ) different from a material (e.g., an epoxy molding compound or other molding compound), a polyimide, a phenolic compound or material, a material with a silicone dispersed therein, or a combination of two or more thereof) of the mold structure (items 11, 13, 13p, 11 plus 13 or 11 plus 13 plus 13p or 63), but does not specifically disclose the plurality of first under-fill patterns (items 13o1, 13o2, 43o, 63o) and the second under-fill pattern (shown but not labeled under items 12a, 62a) are formed of the same material.
It would have been obvious to modify the invention to include a plurality of first under-fill and a second underfill formed of the same material, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use (In re Leshin, 125 USPQ 416).
Chen does not specifically disclose the first sub-package comprises an upper substrate spaced apart from the lower substrate; the first mold is disposed on and upper and lateral surface of the first semiconductor chip; wherein an upper surface of the first under-fill pattern is at a level higher than a level of an upper surface of the first semiconductor chip
In regards to claim 16, Co (paragraph 88, Figs. 1, 2, 5, 6, 7, 11, 13, 17A, and associated text and items) discloses a semiconductor package, comprising: a first sub-package (Fig. 7, item 410); and a second sub-package (item 488) on the first sub-package (Fig. 7, item 410), wherein the first sub-package (Fig. 7, item 410) comprises: a lower substrate (item 12); a first semiconductor chip (item 22) and an upper substrate (item 54) spaced apart from the lower substrate (items 12); and a first mold structure (item 42) between the lower substrate (item 12) and the upper substrate (item 54), wherein the first mold structure (item 42) is disposed on upper and lateral surfaces of the first semiconductor chip (item 22); wherein the second sub-package (item 488) comprises: a package substrate (item 412); a second semiconductor chip (item 489) on the package substrate (item 412); and a second mold structure (item 444) on an upper surface of the package substrate (item 412) and upper and lateral surfaces of the second semiconductor chip (item 489), wherein the top surface of the plurality of wires (items 32, 34) is at a level higher than a level of a top surface of the first semiconductor chip (item 22).
Therefore Chen as modified by Co discloses wherein the top surface of the first under-fill pattern (items 13o1, 13o2, 43o, 63o, Chen) is at a level higher than a level of a top surface of the first semiconductor chip (items 12a, 62a), since Chen discloses the first under-fill pattern (items 13o1, 13o2, 43o, 63o, Chen) extends the full length/height of the plurality of wires (items 13v, 43v, 63v).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to the teachings of Co for the purpose of an electrical connection, protection and design choice.
In regards to claim 17, Chen (Figs. 1A, 6F and associated text and items) as modified by Co (paragraph 88, Figs. 1, 2, 5, 6, 7, 11, 13, 17A, and associated text and items) discloses wherein a height of the wires (items 13v, 43v, 63v, Chen) is substantially the same as a height of the first under-fill pattern (items 13o1, 13o2, 43o, 63o, Chen).
In regards to claim 18, Chen (Figs. 1A, 6F and associated text and items) as modified by Co (paragraph 88, Figs. 1, 2, 5, 6, 7, 11, 13, 17A, and associated text and items) discloses wherein: the first sub-package (items 11 plus 12a plus 10, items 11 plus 12a plus 10 plus substrate shown but not labeled, items 62a plus 65 plus 63 or items 62a plus 65 plus 63 plus substrate shown but not labeled, Chen, Figs. 6, item 410, Co) further comprises a plurality of connection terminals (item 62a1, Chen, item 426, Co) on an active surface of the first semiconductor chip (items 12a, 62a, Chen, item 22, Co), and the first under-fill pattern (items 13o1, 13o2, 43o, 63o, Chen) and the connection terminals (item 62a1, Chen, item 426, Co) are spaced apart from each other.
In regards to claim 20, Chen (Figs. 1A, 6F and associated text and items) discloses wherein: the first under-fill pattern (items 13o1, 13o2, 43o, 63o) is provided in plural, and each of the first under-fill patterns (items 13o1, 13o2, 43o, 63o,) has a ring shape when viewed in plan (Figs 4B-4E).
Claim(s) 1-10, 12-18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (Kim) (US 2021/0398890 A1) in view of Chen et al. (US 2019/0027441 A1).
In regards to claims 1-10, 12-18 and 20, Kim (Fig. 1 and associated text) discloses the Applicant’s claimed invention except under-fill pattern/first under-fill patterns.
Chen (Figs. 1A, 6F and associated text and items) discloses under-fill pattern/first under-fill pattern(s) (items 13o1, 13o2, 43o, 63o) surround lateral surfaces of the plurality of wires (items 13v1, 13v2, 43v, 63v). See teachings of Chen in the above rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TELLY D GREEN whose telephone number is (571)270-3204. The examiner can normally be reached M-F 8am-5pm.
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 January 22, 2026