CTNF 18/125,430 CTNF 78914 DETAILED ACTION 07-03-aia AIA 15-10-aia 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. This Office Action is in response to the communications dated 05/31/2024. Claims 1-20 are pending in this application. Acknowledges 2. Receipt is acknowledged of the following items from the Applicant. Information Disclosure Statement (IDS) filed on 05/31/2024. The references cited on the PTOL 1449 form have been considered. Applicant is requested to cite any relevant prior art if being aware on form PTO-1449 in accordance with the guidelines set for in M.P.E.P. 609. Specification 06-31 AIA 3. The specification has been checked to the extent necessary to determine the presence of possible minor errors. However, the applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 4. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15-03-aia AIA 5. Claim s 1-3, and 5-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Xie et al. (US 2024/0222227) Regarding claim 1, Xie discloses an integrated circuit comprising: a semiconductor device (shown in figures 2A-2B, figures. 5, collectively) having a semiconductor region 254-1 -- 254-3 (fig. 2A) or 420-T/420-B (fig. 5H) extending in a first direction (X direction, fig. 2A) from a first source or drain region 214 to a second source or drain region 214 (fig. 2B, and para. 0053) , and a gate electrode 254-1 -- 254-3 (fig. 2A) or 212-4 (fig. 2B) extending in a second direction (Y1, Y2 direction, fig. 2A) over the semiconductor region; a dielectric wall 456-1 – 456-3 (fig. 2B, fig. 5G) or 430 & 432 (fig. 5H; gate cuts paras. 0077-0081) extending in the first direction (X direction) through an entire thickness of the gate electrode 212-4 (fig. 2B) or 424 (fig. 5D) and extending in the first direction adjacent to the first source or drain region and the second source or drain region; and a conductive via 210 (fig. 2B, paras. 0055, 0058-0059) extending in the first direction through an entire thickness of the gate electrode 212-4 and extending in the first direction adjacent to the first source or drain region and the second source or drain region, such that the semiconductor device 214-T/214-B, fig. 2B is between the dielectric wall (above STI 218 in fig. 2B) and the conductive via 210 along the second direction. Regarding claim 2, Xie discloses the integrated circuit of claim 1, further comprising a liner 220 between the conductive via 210 and the gate electrode 212-4. See fig. 2B, figs. 5. Regarding claim 3, Xie discloses the integrated circuit of claim 2, wherein the liner comprises a low-k dielectric material. See para. 0050. Regarding claim 5, Xie discloses the integrated circuit of claim 1, further comprising a dielectric fill 218 beneath the gate electrode 212-4. See fig. 2B. Regarding claim 6, Xie discloses the integrated circuit of claim 5, wherein the conductive via 210 extends through an entire thickness of the dielectric fill 218. See fig. 2B. Regarding claim 7, Xie discloses the integrated circuit of claim 6, wherein the conductive via 210 contacts a conductive layer 222 beneath the dielectric fill 218. See fig. 2B. Regarding claim 8, Xie discloses an electronic device, comprising: a chip package comprising one or more dies 200 (see figs. 2B, fig. 5 collectively) , at least one of the one or more dies 200 comprising: a semiconductor device (shown in figures 2A-2B, figures. 5, collectively) having a semiconductor region 254-1 -- 254-3 (fig. 2A) or 420-T/420-B (fig. 5H) extending in a first direction (X direction, fig. 2A) from a first source or drain region 214 to a second source or drain region 214 (fig. 2B, and para. 0053) , and a gate electrode 254-1 -- 254-3 (fig. 2A) or 212-4 (fig. 2B) extending in a second direction (Y1, Y2 direction, fig. 2A) over the semiconductor region; a dielectric wall 456-1 – 456-3 (fig. 2B, fig. 5G) or 430 & 432 (fig. 5H; gate cuts paras. 0077-0081) extending in the first direction (X direction) through an entire thickness of the gate electrode 212-4 (fig. 2B) or 424 (fig. 5D) and extending in the first direction adjacent to the first source or drain region and the second source or drain region; and a conductive via 210 (fig. 2B, paras. 0055, 0058-0059) extending in the first direction through an entire thickness of the gate electrode 212-4 and extending in the first direction adjacent to the first source or drain region and the second source or drain region, such that the semiconductor device 214-T/214-B, fig. 2B is between the dielectric wall (above STI 218 in fig. 2B) and the conductive via 210 along the second direction. Regarding claims 9, 10, 11, 12, and 13, Xie discloses the electronic device comprising all claimed limitations. See the rejections of claims 2, 3, 5, 6, and 7, respectively. Regarding claim 14, Xie discloses the electronic device of claim 8, wherein the semiconductor region comprises a plurality of semiconductor nanoribbons. See para. 0052. Regarding claim 15, Xie discloses an integrated circuit comprising: a first semiconductor device 212-T having a first semiconductor region 254-1 -- 254-3 (fig. 2A) or 420-T/420-B (fig. 5H) extending in a first direction (X direction) from a first source or drain region 214-T to a second source or drain region 214-T, and a first gate structure 254-1 -- 254-3 (fig. 2A) or 212-4 (fig. 2B) extending in a second direction (Y1, Y2 direction, fig. 2A) over the first semiconductor region; a second semiconductor device 212-T having a second semiconductor region 54-1 -- 254-3 (fig. 2A) or 420-T/420-B (fig. 5H) extending in the first direction from a third source or drain region 214-T to a fourth source or drain region 214-T, and a second gate structure 254-1 -- 254-3 (fig. 2A) or 212-4 (fig. 2B) extending in the second direction over the second semiconductor region, the third source or drain region 214-T being aligned with the first source or drain region 214-T along the second direction, and the fourth source or drain region 214-T being aligned with the second source or drain region 214-T along the second direction; a dielectric wall 456-1 – 456-3 (fig. 2B, fig. 5G) or 430 & 432 (fig. 5H; gate cuts paras. 0077-0081) extending in the first direction between and contacting the first gate structure and the second gate structure, extending in the first direction between the first and third source or drain regions, and extending in the first direction between the second and fourth source or drain regions; a first conductive via 210 (fig. 2B, paras. 0055, 0058-0059) extending in the first direction through an entire thickness of the first gate structure 212-4 or 424 (fig. 2B, fig. 5) and extending in the first direction adjacent to the first source or drain region and the second source or drain region, such that the first semiconductor device is between the dielectric wall and the first conductive via along the second direction; and a second conductive via 210 extending in the first direction through an entire thickness of the second gate structure and extending in the first direction adjacent to the third source or drain region and the fourth source or drain region, such that the second semiconductor device is between the dielectric wall and the second conductive via along the second direction. Regarding claim 16, Xie discloses the integrated circuit of claim 15, further comprising a first liner 220 between the first conductive via 210 and the first gate structure and a second liner 220 between the second conductive via 210 and the second gate structure, the first and second liners each comprising a low-k dielectric material. See figs. 2B, figs. 5, and para. 0050. Regarding claim 17, Xie discloses the integrated circuit of claim 15, further comprising a dielectric fill 218 beneath the first gate structure 212-4 and the second gate structure 212-4. See fig. 2B. Regarding claim 18, Xie discloses the integrated circuit of claim 17, wherein the first and second conductive vias 210 extend through an entire thickness of the dielectric fill. See fig. 2B. Regarding claim 19, Xie discloses the integrated circuit of claim 15, wherein the dielectric wall comprises silicon and nitrogen. See para. 0079. Regarding claim 20, Xie discloses the integrated circuit of claim 15, wherein the second direction is substantially perpendicular to the first direction. See fig. 2A Claim Rejections - 35 U.S.C. § 103 07-20-aia AIA 6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA 7. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Xie et al. (US 2024/0222227) Regarding claim 4, Xie discloses the integrated circuit of claim 2, comprising all claimed limitations, as discussed above, except for wherein the dielectric wall has a greatest width along the second direction between about 10 nm and about 20 nm, and the conductive via plus the liner has a greatest width along the second direction between about 20 nm and about 30 nm. However, it has been held that where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed element, and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device (MPEP §2144.04). It would have been obvious that a mere change in size of a component is generally recognized as being within the level of ordinary skill in the art. It is to be expected that a change in size, width of a component would be an unpatentable modification. Under some circumstances, however, changes such as these may impart patentability to a process if the particular ranges claimed produce a new and unexpected result which is different in kind and not merely degree from the results of the prior art...such ranges are termed "critical ranges and the applicant has the burden of proving such criticality. See In re Aller, 220 F.2d 454, 105 USPQ 233,235 (CCPA 1955). The instant specification contains no disclosure of either the critical nature of the claimed dimensions/sizes or of any unexpected results arising therefrom. Where patentability is aid to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. (In re Woodruff, 919 F.2d 1575, 1578 (Fed. Cir. 1990).) The claimed limitation regarding to the widths of the dielectric wall and/or the conductive via do/does not bear any critical point that would establish patentability, and is/are not sufficient to patentable distinguish over the prior art, therefore being considered as unpatentable limitation(s) because it would have involve only a mere change in size/thickness of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). See MPEP §2144.04). Conclusion 8. A shortened statutory period for response to this action is set to expire 3 (three) months and 0 (zero) day from the day of this letter. Failure to respond within the period for response will cause the application to become abandoned (see M.P.E.P 710.02(b)). A shortened time for reply may be extended up to the maximum six-month period (35 U.S.C. 133). An extension of time fee is normally required to be paid if the reply period is extended. The amount of the fee is dependent upon the length of the extension. Extensions of time are generally not available after an application has been allowed. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Dao H. Nguyen whose telephone number is (571)272-1791. The examiner can normally be reached on Monday-Friday, 9:00 AM – 5:00 PM. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke, can be reached on (571)272-1657. The fax numbers for all communication(s) is 571-273-8300. Any inquiry of a general nature or relating to the status of this application or proceeding should be directed to the receptionist whose telephone number is (571)272-1633. /DAO H NGUYEN/Primary Examiner, Art Unit 2818 April 22, 2026 Application/Control Number: 18/125,430 Page 2 Art Unit: 2818 Application/Control Number: 18/125,430 Page 3 Art Unit: 2818 Application/Control Number: 18/125,430 Page 4 Art Unit: 2818 Application/Control Number: 18/125,430 Page 5 Art Unit: 2818 Application/Control Number: 18/125,430 Page 6 Art Unit: 2818 Application/Control Number: 18/125,430 Page 7 Art Unit: 2818 Application/Control Number: 18/125,430 Page 8 Art Unit: 2818 Application/Control Number: 18/125,430 Page 9 Art Unit: 2818
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